DS90UH302QSQX/NOPB全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

DS90UH925AQ-Q1 720p 24 位彩色平面显示器-链路 (FPD-Link) III 串化

器，支持高带宽数字内容保护技术 (HDCP)

1 特性

3 说明

1

•

支持片上密钥存储的集成型 HDCP 密码引擎

DS90UH925AQ 串化器，连同 DS90UH926Q 解串器

一起，在汽车娱乐系统内为内容受保护数字视频的安全

分发提供了一款解决方案。这个芯片组将一个并行

RGB 视频接口转换为一个单对高速串行化接口。数字

视频数据采用业界标准的 HDCP 复制保护方案加以保

护。串行总线方案，FPD-Link III，支持通过单个差分

链路实现视频和音频数据传输以及包括 I2C 通信在内

的全双工控制。通过单个差分对实现视频数据和控制

的整合可减少互连线尺寸和重量，同时还消除了偏差问

题并简化了系统设计。

具有 I2C 兼容串行控制总线的双向控制接口通道接

口

•

支持高清 (720p) 数字视频格式

支持 RGB888 + VS，HS，DE 和 I2S 音频

支持 5 至 85MHz 并行时钟 (PCLK)

具有 1.8V 或 3.3V 兼容 LVCMOS I/O 接口的单个

3.3V 电源运行

•

长达 10 米的交流耦合生成树协议 (STP) 互连

并行 LVCMOS 视频输出

具有嵌入式时钟的直流均衡 & 扰频数据

支持 HDCP 中继器应用

DS90UH925AQ 串化器嵌入时钟，内容保护数据有效

载荷，并将信号电平位移至高速低压差分信令。高达

24 位的 RGB 数据位连同 3 个视频控制信号和多达 2

个 I2S 数据输入被一起串化。

针对远程中断的专用中断引脚

内部模式生成

低功率模式最大限度地减少了功率耗散

汽车应用级产品：符合 AEC-Q100 2 级要求

低压差分信令的使用、数据换序和随机生成以及展频定

时兼容性最大限度地减少了电磁干扰 (EMI)。

>8kV 人体模型 (HBM) 和 ISO 10605 静电放电

(ESD) 等级

串化器和解串器上都执行 HDCP 密码引擎。 HDCP 密

钥被存储在片上存储器中。

•

向后兼容模式

2 应用范围

来自下游 DS90UH926Q 解串器的远程中断被映射至一

个本地输出引脚。

•

汽车用触摸显示屏

汽车导航显示屏

后座娱乐系统

器件信息⁽¹⁾

部件号

封装

封装尺寸（标称值）

超薄四方扁平无引线

(WQFN) RHS (48)

DS90UH925AQ-Q1

7.00mm x 7.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型眼图

4 简化电路原理图

V

DD33

V

DDIO

V

DD33

V

DDIO

(1.8Vor3.3V) (3.3V)

(3.3V) (1.8Vor3.3V)

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Pair /AC Coupled

B[7:0]

HS

VS

DE

PCLK

0.1 PF

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

HS

DOUT+

DOUT-

RIN+

RIN-

VS

DE

PCLK

100 ohm STP Cable

DS90UH925AQ

Serializer

DS90UH926Q

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

3

/

I2S AUDIO

(STEREO)

3

/

I2S AUDIO

(STEREO)

MCLK

MODE_SEL

INTB

REM_INTB

INTB_IN

SCL

SDA

IDx

SCL

SDA

IDx

DAP

Time (100 ps/DIV)

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNLS481

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

7.11 Typical Characteristics ........................................ 15

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Device Functional Modes........................................ 23

8.3 Programming........................................................... 27

Application and Implementation ........................ 43

9.1 Application Information............................................ 43

9.2 Typical Application .................................................. 43

1

2

3

4

5

6

7

特性.......................................................................... 1

8

9

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 Handling Ratings....................................................... 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 DC Electrical Characteristics ................................... 8

7.6 AC Electrical Characteristics^{(1) (2) (3)}..................... 10

7.7 Recommended Timing for the Serial Control Bus .. 11

7.8 DC and AC Serial Control Bus Characteristics....... 12

7.9 AC Timing Diagrams and Test Circuits................... 12

7.10 Switching Characteristics...................................... 15

10 Power Supply Recommendations ..................... 46

11 Layout................................................................... 47

11.1 Layout Guidelines ................................................. 47

11.2 Layout Example .................................................... 47

12 器件和文档支持 ..................................................... 50

12.1 Trademarks........................................................... 50

12.2 Electrostatic Discharge Caution............................ 50

12.3 术语表 ................................................................... 50

13 机械封装和可订购信息 .......................................... 50

5 修订历史记录

日期

修订版本

注释

2014 年 6 月

*

最初发布。

2

DS90UH925AQ-Q1

www.ti.com.cn

ZHCSCL3 –JUNE 2014

6 Pin Configuration and Functions

DS90UH925AQ Pin Diagram

48 Pins

Top View

G2

37

MODE_SEL

CMF

24

23

22

21

20

19

18

17

16

15

14

13

G3

38

G4

39

VDD33

PDB

G5

40

G6

41

DOUT+

DOUT-

G7

42

DS90UH925AQ

RES1

B0/GPO_REG4

43

44

45

46

47

48

TOP VIEW

CAPHS12

REM_INTB

RES0

B1/I2S_DB/GPO_REG5

B2

B3

B4

B5

DAP = GND

CAPP12

I2S_CLK

3

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

Pin Functions

PIN NAME

PIN #

I/O, TYPE

DESCRIPTION

LVCMOS PARALLEL INTERFACE

R[7:0]

G[7:0]

B[7:0]

HS

34, 33, 32, 29, I, LVCMOS RED Parallel Interface Data Input Pins

28, 27, 26, 25 w/ pull down Leave open if unused

R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.

42, 41, 40, 39, I, LVCMOS GREEN Parallel Interface Data Input Pins

38, 37, 36, 35 w/ pull down Leave open if unused

G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.

BLUE Parallel Interface Data Input Pins

46, 45, 44, 43 w/ pull down Leave open if unused

B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.

I, LVCMOS Horizontal Sync Input Pin

2, 1, 48, 47,

I, LVCOS

3

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when

the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.

See Table 6

VS

DE

4

5

I, LVCMOS Vertical Sync Input Pin

w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width

is 130 PCLKs.

I, LVCMOS Data Enable Input Pin

w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when

the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.

See Table 6

PCLK

10

I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6

w/ pull down

I2S_CLK,

I2S_WC,

I2S_DA

13, 12, 11

I, LVCMOS Digital Audio Interface Data Input Pins

w/ pull down Leave open if unused

I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as

GPO_REG6.

OPTIONAL PARALLEL INTERFACE

I2S_DB

44

I, LVCMOS

Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by

w/ pull down MODE_SEL pin or configuration register

Leave open if unused

I2S_DB can optionally be used as B1 or GPO_REG5.

GPIO[3:0]

36, 35, 26, 25 I/O, LVCMOS General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or

w/ pull down configuration register. See Table 6

Leave open if unused

Shared with G1, G0, R1 and R0.

GPO_REG[ 12, 11, 44, 43 O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6

7:4]

w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.

CONTROL

PDB

21

I, LVCMOS Power-down Mode Input Pin

w/ pull-down PDB = H, device is enabled (normal operation)

Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is

shutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL

24

6

I, Analog

Device Configuration Select. See Table 4

I2C

IDx

I2C Serial Control Bus Device ID Address Select

External pull-up to V_DD33is required under all conditions, DO NOT FLOAT.

Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 20

SCL

SDA

8

9

I/O, LVCMOS I2C Clock Input / Output Interface

Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.

Recommended pull-up: 4.7 kΩ.

I/O, LVCMOS I2C Data Input / Output Interface

Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.

Recommended pull-up: 4.7 kΩ.

4

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ZHCSCL3 –JUNE 2014

Pin Functions (continued)

PIN NAME

STATUS

INTB

PIN #

I/O, TYPE

DESCRIPTION

31

O, LVCMOS Interrupt. Read ISR register to determine source. Interrupt clears on ISR read.

Open Drain INTB = H, normal

INTB = L, Interrupt request

Recommended pull-up: 4.7 kΩ to V_DDIO

REM_INTB

16

O, LVCMOS Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB will be

driven LOW until lock is achieved with the downstream serializer.

REM_INTB = H, normal

REM_INTB = L, interrupt request

FPD-Link III SERIAL INTERFACE

DOUT+

DOUT-

CMF

20

19

23

O, LVDS

Analog

True Output

The output must be AC-coupled with a 0.1µF capacitor.

Inverting Output

The output must be AC-coupled with a 0.1µF capacitor.

Common Mode Filter.

Connect 0.1µF to GND

POWER⁽¹⁾and GROUND

V_DD33

V_DDIO

GND

22

30

Power

Ground

Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND

LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND

DAP

DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connect to the ground plane (GND) with at least 9 vias.

REGULATOR CAPACITOR

CAPHS12,

CAPP12

17, 14

CAP

Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each

CAP pin.

CAPL12

7

Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this

CAP pin.

OTHERS

RES[1:0]

18, 15

GND

Reserved. Tie to Ground.

(1) The VDD (V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. Refer to Power Up Requirements and

PDB Pin for details.

5

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

MAX

+4.0

UNIT

V

V_DD33

V_DDIO

Supply Voltage

V

V_DDIO

0.3

+

LVCMOS I/O Voltage

–0.3

V

Serializer Output Voltage

Junction Temperature

+2.75

+150

V

T_J

°C

For soldering specifications:

see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN

-65

-8

MAX

+150

+8

UNIT

T_stg

Storage temperature range 48 Lead WQFN Package

Human body model (HBM), per AEC Q100-002⁽¹⁾

°C

kV

V

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per AEC Q100-011

Machine Model

-1.25

-250

-15

-8

+1.25

+250

+15

Air Discharge (D_OUT+, D_OUT-

Contact Discharge (D_OUT+, D_OUT-

Air Discharge (D_OUT+, D_OUT-

Contact Discharge (D_OUT+, D_OUT-

)

ESD Rating (IEC 61000-4-2)

R_D= 330Ω, C_S= 150pF

kV

)

+8

ESD Rating (ISO10605)

R_D= 330Ω, C_S= 150pF

R_D= 2KΩ, C_S= 150pF or 330pF

)

-15

+15

kV

-8

+8

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN

3.0

TYP

3.3

MAX

3.6

UNIT

V

Supply Voltage (V_DD33

)

LVCMOS Supply Voltage (V_DDIO

)

3.0

3.3

3.6

V

OR

LVCMOS Supply Voltage (V_DDIO

1.71

−40

5

1.8

1.89

+105

85

V

Operating Free Air Temperature (T_A)

PCLK Frequency

Supply Noise⁽¹⁾

+25

°C

MHz

mV_P-P

100

(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DD33and V_DDIOsupplies

with amplitude = 100 mVp-p measured at the device V_DD33and V_DDIOpins. Bit error rate testing of input to the Ser and output of the

Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no

error when the noise frequency is less than 50 MHz.

6

DS90UH925AQ-Q1

www.ti.com.cn

ZHCSCL3 –JUNE 2014

7.4 Thermal Information

WQFN

THERMAL METRIC⁽¹⁾

UNIT

48 PINS

35

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.2

5.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

5.5

R_θJC(bot)

1.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

(1) (2) (3)

7.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

LVCMOS I/O DC SPECIFICATIONS

V_IH

V_IL

I_IN

High Level Input Voltage

Low Level Input Voltage

Input Current

V_DDIO= 3.0 to 3.6 V

2.0

GND

−10

2.0

V_DDIO

0.8

V

V_DDIO= 3.0 to 3.6 V

PDB

V_IN= 0 V or V_DDIO= 3.0 to 3.6 V

V_DDIO= 3.0 to 3.6 V

±1

+10

μA

V

V_DDIO

V_IH

High Level Input Voltage

Low Level Input Voltage

0.65*

V_DDIO

V_DDIO= 1.71 to 1.89 V

V_DDIO= 3.0 to 3.6 V

V_DDIO= 1.71 to 1.89 V

V_DDIO

0.8

V

R[7:0], G[7:0],

B[7:0], HS, VS,

DE, PCLK,

I2S_CLK,

GND

V_IL

0.35*

V_DDIO

GND

I2S_WC,

I2S_DA,

I2S_DB

V_DDIO= 3.0

to 3.6 V

−10

2.4

±1

+10

μA

V

I_IN

Input Current

V_IN= 0 V or V_DDIO

V_DDIO= 1.71

to 1.89 V

V_DDIO= 3.0

to 3.6 V

V_DDIO

0.4

V_OH

High Level Output Voltage I_OH= −4 mA

V_DDIO= 1.71

to 1.89 V

V_DDIO

0.45

-

V

V_DDIO= 3.0

to 3.6 V

GND

V

GPIO[3:0],

GPO_REG[7:4],

REM_INTB

V_OL

Low Level Output Voltage I_OL= +4 mA

V_DDIO= 1.71

to 1.89 V

0.35

V

Output Short Circuit

V_OUT= 0 V

I_OS

I_OZ

−50

mA

μA

Current

TRI-STATE® Output

V_OUT= 0 V or V_DDIO, PDB = L,

−10

+10

Current

FPD-LINK III CML DRIVER DC SPECIFICATIONS

Differential Output Voltage

(DOUT+) – (DOUT-)

V_ODp-p

R_L= 100 Ω, Figure 1

1160

1250

1

1340

50

mVp-p

mV

ΔV_OD

Output Voltage Unbalance

2.5-

Offset Voltage – Single-

ended

0.25*V_O

Dp-p

V_OS

R_L= 100 Ω, Figure 1

V

(TYP)

DOUT+, DOUT-

Offset Voltage Unbalance

Single-ended

ΔV_OS

I_OS

1

50

62

mV

mA

Ω

Output Short Circuit

Current

DOUT+/- = 0 V, PDB = L or H

−38

52

Internal Termination

Resistor - Single ended

R_T

40

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD= 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD and ΔVOD, which are differential voltages.

8

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ZHCSCL3 –JUNE 2014

DC Electrical Characteristics ^{(1) (2) (3)}(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_DD1

V_DD33= 3.6 V

V_DDIO= 3.6 V

V_DD33

V_DDIO

V_DD33

V_DDIO

V_DD33

V_DDIO

148

90

170

180

mA

Supply Current

(includes load current)

R_L= 100 Ω, f = 85 MHz

Checker Board Pattern,

Figure 2

μA

I_DDIO1

I_DDS1

I_DDIOS1

I_DDS2

V_DDIO= 1.89

V

1

1.6

mA

V_DD33= 3.6 V

1.2

65

2.4

mA

Supply Current Remote

Auto Power Down Mode

0x01[7] = 1, deserializer V_DDIO= 3.6 V

150

μA

is powered down

V_DDIO= 1.89

55

150

μA

V

V_DD33= 3.6 V

1

2

mA

PDB = L, All LVCMOS

inputs are floating or tied

to GND

Supply Current Power

Down

V_DDIO= 3.6 V

65

150

μA

I_DDIOS2

V_DDIO= 1.89

V

50

150

μA

9

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ZHCSCL3 –JUNE 2014

www.ti.com.cn

7.6 AC Electrical Characteristics^{(1) (2) (3)}

Over recommended operating supply and temperature ranges unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

GPIO BIT RATE

Forward Channel Bit Rate

Back Channel Bit Rate

f = 5 – 85

MHz

GPIO[3:0]

0.25* f

75

Mbps

kbps

B_R

See^{(4) (5)}

RECOMMENDED TIMING FOR PCLK

t_TCP

t_CIH

t_CIL

PCLK Period

11.76

0.4*T

4.0

T

200

ns

PCLK Input High Time

PCLK Input Low Time

PCLK Input Transition Time

See^{(4) (5)}

PCLK

0.5*T

0.6*T

f = 5 MHz

(4) (5)

t_CLKT

t_IJIT

Figure 3

f = 85 MHz

0.5

PCLK Input Jitter Tolerance,

f = 5 – 78

MHz

f / 40 < Jitter Freq < f / 20^{(4) (6)}

0.4

0.6

UI

Bit Error Rate ≤10^-10

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD= 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD and ΔVOD, which are differential voltages.

(4) Specification is ensured by characterization and is not tested in production.

(5) Specification is ensured by design and is not tested in production.

(6) Jitter Frequency is specified in conjunction with DS90UH926 PLL bandwidth.

10

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ZHCSCL3 –JUNE 2014

7.7 Recommended Timing for the Serial Control Bus

Over 3.3 V supply and temperature ranges unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

100

UNIT

kHz

us

f_SCL

Standard Mode

Fast Mode

SCL Clock Frequency

0

400

t_LOW

Standard Mode

Fast Mode

4.7

1.3

4.0

0.6

4.0

SCL Low Period

SCL High Period

us

t_HIGH

Standard Mode

Fast Mode

us

t_HD;STA

Hold time for a start or a

repeated start condition

Figure 8

Standard Mode

us

Fast Mode

0.6

4.7

0.6

us

t_SU:STA

Set Up time for a start or a

repeated start condition

Figure 8

Standard Mode

Fast Mode

t_HD;DAT

t_SU;DAT

t_SU;STO

Standard Mode

Fast Mode

0

3.45

0.9

us

ns

us

Data Hold Time

Figure 8

0

Standard Mode

Fast Mode

250

100

4.0

0.6

4.7

Data Set Up Time

Figure 8

Standard Mode

Fast Mode

Set Up Time for STOP Condition,

Figure 8

Bus Free Time

Standard Mode

t_BUF

Between STOP and START,

Figure 8

Fast Mode

1.3

us

Standard Mode

Fast Mode

1000

300

ns

SCL & SDA Rise Time,

Figure 8

t_r

t_f

Standard Mode

Fast mode

SCL & SDA Fall Time,

Figure 8

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7.8 DC and AC Serial Control Bus Characteristics

Over 3.3 V supply and temperature ranges unless otherwise specified.⁽¹⁾

(2) (3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

0.7*

V_DD33

Input High Level

SDA and SCL

V_DD33

V

V_IL

0.3*

V_DD33

Input Low Level Voltage

Input Hysteresis

GND

V

V_HY

V_OL

I_in

>50

mV

V

SDA, IOL = 1.25 mA

0

0.36

+10

SDA or SCL, Vin = V_DD33or GND

-10

µA

ns

pF

t_R

SDA RiseTime – READ

SDA Fall Time – READ

Set Up Time – READ

Hold Up Time – READ

Input Filter

430

20

SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 8

t_F

t_SU;DAT

t_HD;DAT

t_SP

Figure 8

560

615

50

C_in

Input Capacitance

SDA or SCL

<5

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V_DD= 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD and ΔVOD, which are differential voltages.

7.9 AC Timing Diagrams and Test Circuits

DOUT+

DOUT-

100 nF

30

Differential probe

SCOPE

BW û 4GHz

Input Impedance û 100 k:

RGB[7:0],

HS,VS,DE,

I2S

100:

D

C

ú 0.5 pf

L

BW û 3.5 GHz

PCLK

D

OUT

-

V

OD-

Single Ended

V

OD

V

OD+

D

OUT

+

V

OS

|

V

OD+

(D

+) - (D -)

OUT OUT

0V

Differential

V

OD-

Figure 1. Serializer VOD DC Output

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AC Timing Diagrams and Test Circuits (continued)

V

DDIO

PCLK

GND

V

DDIO

RGB[n] (odd),

VS, HS

GND

V

DDIO

RGB[n] (even),

DE

GND

Figure 2. Checkboard Data Pattern

V

DDIO

80%

PCLK

20%

t

0V

t

CLKT

Figure 3. Serializer Input Clock Transition Time

C

DOUT+

DOUT-

L

80%

Differential

Signal

V

diff

= 0V

100:

20%

LHT

20%

t

HLT

C

L

Figure 4. Serializer CML Output Load and Transition Time

t

TCP

V

/2

DDIO

V

/2

V

/2

DDIO

PCLK

DDIO

t

DIH

DIS

V

DDIO

RGB[7:0],

HS,VS,DE

Setup

Hold

V

/2

DDIO

V

DDIO

/2

0V

Figure 5. Serializer Setup and Hold Times

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AC Timing Diagrams and Test Circuits (continued)

VDD

VDDIO

PDB

1/2 V

DDIO

PCLK

t

PLD

DOUT

(Diff.)

Driver On

Driver OFF, V

OD

= 0V

Figure 6. Serializer Lock Time

t

DJIT

VOD (+)

DOUT

(Diff.)

EYE OPENING

0V

VOD (-)

t

(1 UI)

BIT

Figure 7. Serializer CML Output Jitter

SDA

SCL

t

BUF

t

f

t

HD;STA

t

r

LOW

t

SP

t

f

r

t

HD;STA

SU;STA

t

SU;STO

t

HIGH

t

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

Figure 8. Serial Control Bus Timing Diagram

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7.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

SYMBOL

PARAMETER

TEST CONDITIONS

PIN/FREQ.

MIN

TYP

MAX

UNIT

t_LHT

CML Output Low-to-High

Transition Time

80

130

ps

DOUT+,

DOUT-

See Figure 4

t_HLT

t_DIS

CML Output High-to-Low

Transition Time

80

130

ps

ns

Data Input Setup to PCLK

Data Input Hold from PCLK

R[7:0],

G[7:0],

B[7:0], HS,

VS, DE,

PCLK,

I2S_CLK,

I2S_WC,

I2S_DA

2.0

See Figure 5

t_DIH

ns

(1)

t_PLD

t_SD

Figure 6

f = 15 -

45MHz

Serializer PLL Lock Time

Delay — Latency

131*T

145*T

ns

f = 15 -

45MHz

Output Total Jitter,

R_L= 100Ω

f = 45MHz

DOUT+,

DOUT-

t_TJIT

Bit Error Rate ≥10^-10

0.25

0.30

UI

(2) (3) (4)

Figure 7

(1) t_PLDis the time required by the device to obtain lock when exiting power-down state with an active PCLK.

(2) Specification is ensured by characterization and is not tested in production.

(3) Specification is ensured by design and is not tested in production.

(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1/35*PCLK). The UI scales with PCLK frequency.

7.11 Typical Characteristics

78 MHz TX

Pixel Clock

Input

(2 V/DIV)

78 MHz RX

Pixel Clock

Output

(2 V/DIV)

Time (1.25 ns/DIV)

Time (10 ns/DIV)

Note: On the rising edge of each clock period, the CML driver outputs

a low Stop bit, high Start bit, and 33 DC-scrambled data bits.

Figure 9. Serializer CML Driver Output at 2.73 Gbps

Figure 10. Comparison of Deserializer LVCMOS RX PCLK

Output locked to a 78 MHz TX PCLK

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8 Detailed Description

8.1 Overview

The DS90UH925AQ serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to

2.975 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced

video data and audio data which enhance signal quality to support AC coupling. The DS90UH925AQ serializes

video and audio data then applies encryption through a High-Bandwidth Digital Content Protection (HDCP)

Cipher and transmits out through the FPD-Link III interface. Audio encryption is supported. The serializer also

includes the HDCP cipher. On board non-volatile memory stores the HDCP keys. All key exchange is conducted

over the FPD-Link III bidirectional control interface. The serializer is intended for use with the DS90UH926Q

deserializer, but is also backward compatible with DS90UR906Q or DS90UR908Q FPD-Link II deserializer.

8.1.1 Functional Block Diagram

REGULATOR

CMF

24

RGB [7:0]

HS

VS

D

+

-

OUT

DE

D

PCLK

OUT

I2S_CLK

I2S_WC

I2S_DA

3

PDB

MODE_SEL

PLL

INTB

REM_INTB

SDA

Timing

and

Control

SCL

IDx

Figure 11. Block Diagram

8.1.2 Feature Description

8.1.2.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,

HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the serial stream per

PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,

balanced and scrambled.

C1

C0

Figure 12. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps

maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.

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Overview (continued)

8.1.2.2 Low Speed Back Channel Data Transfer

The Low-Speed Backward Channel (LS_BC) of the DS90UH925AQ provides bidirectional communication

between the display and host processor. The information is carried back from the Deserializer to the Serializer

per serial symbol. The back channel control data is transferred over the single serial link along with the high-

speed forward data, DC balance coding and embedded clock information. This architecture provides a backward

path across the serial link together with a high speed forward channel. The back channel contains the I2C,

HDCP, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

8.1.2.3 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin

for additional common-mode filtering of the differential pair. This can be useful in high noise environments for

additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

8.1.2.4 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following

restrictions:

•

Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, the transition pulse must be 3 PCLK or longer.

Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, no restriction on minimum transition pulse.

VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal

can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency

noise on the control signals. See Figure 13.

PCLK

IN

HS/VS/DE

IN

Latency

PCLK

OUT

Pulses 1 or 2

PCLKs wide

Filetered OUT

HS/VS/DE

OUT

Figure 13. Video Control Signal Filter Waveform

8.1.2.5 Backward Compatible Mode

The DS90UH925AQ is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II deserializers

at 5-65 MHz of PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at the line rate of

140 Mbps to 1.82 Gbps. The backward configuration mode can be set via MODE_SEL pin (Table 4) or the

configuration register (Table 6). Note: frequency range = 15 - 65 MHz when LFMODE = 0 and frequency range =

5 - <15 MHz when LFMODE = 1.

8.1.2.6 EMI Reduction Features

8.1.2.6.1 Input SSC Tolerance (SSCT)

The DS90UH925AQ serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up

to +/-2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.

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Overview (continued)

8.1.2.7 LVCMOS V_DDIOOption

1.8 V or 3.3 V Inputs and Outputs are powered from a separate V_DDIOsupply to offer compatibility with external

system interface signals. Note: When configuring theV_DDIOpower supplies, all the single-ended data and control

input pins for device need to scale together with the same operating V_DDIOlevels.

8.1.2.8 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the

host or through the V_DDIO, where V_DDIO= 3.0 V to 3.6 V or V_DD33. To save power disable the link when the

display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33and

V_DDIOhave reached final levels; no external components are required. In the case of driven by the V_DDIO= 3.0 V

to 3.6 V or V_DD33directly, a 10 kohm resistor to the V_DDIO= 3.0 V to 3.6 V or V_DD33, and a >10 uF capacitor to

the ground are required (See Figure 25 Typical Connection Diagram).

8.1.2.9 Remote Auto Power Down Mode

The Serializer features a remote auto power down mode. During the power down mode of the pairing

deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the

Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power

on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.

8.1.2.10 Input PCLK Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A

clock loss condition is detected when PCLK drops below approximately 1 MHz. When a PCLK is detected again,

the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers

values are still RETAINED.

8.1.2.11 Serial Link Fault Detect

The serial link fault detection is able to detect any of following seven (7) conditions

1) cable open

2) “+” to “-“ short

3) “+” short to GND

4) “-“ short to GND

5) “+” short to battery

6) “-“ short to battery

7) Cable is linked correctly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address

0x0C Table 6.

8.1.2.12 Pixel Clock Edge Select (RFB)

The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines

the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB

is LOW (‘0’), data is latched on the Falling edge of the PCLK.

8.1.2.13 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency

of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is

High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,

a PDB reset is required.

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Overview (continued)

8.1.2.14 Interrupt Pins – Funtional Description and Usage (INTB, REM_INTB)

The REM_INTB pin mirrors the status of INTB_IN from the remote DS90UH926Q. Any change in INTB_IN status

of the remote device will be reflected at the REM_INTB output of the serializer. REM_INTB will remain LOW until

lock is achieved with the downstream deserializer. Alternately, the INTB pin can be set to trigger on remote

interrupts by following the steps below.

1. On DS90UH925A, set register 0xC6[5] = 1 and 0xC6[0] = 1

2. DS90UH926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device.

3. DS90UH925AQ serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt

condition.

4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .

5. A read to HDCP_ISR will clear the interrupt at the DS90UH925A, releasing INTB.

6. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the

INTB_IN (pin 16) on the DS90UH926Q. The system is now ready to return to step (1) at next falling edge of

INTB_IN.

If using the REM_INTB pin instead of INTB for remote interrupts, the IS_RX_INT bit (0xC6[5]) of the serializer's

ICR register must be set low (default) masking remote interrupts to the INTB pin.

8.1.2.15 GPIO[3:0] and GPO_REG[7:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH925AQ can be used as the general

purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.

GPIO[3:0] Enable Sequence

See Table 1 for the GPIO enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925AQ only.

DS90UH926Q is automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925AQ, then write 0x05 to

address 0x1F on DS90UH926Q.

Table 1. GPIO Enable Sequencing Table

#

Description

Device

Forward Channel

0x12 = 0x04

Back Channel

0x12 = 0x04

1

Enable 18-bit

mode

DS90UH925AQ

DS90UH926Q

DS90UH925AQ

DS90UH926Q

DS90UH925AQ

DS90UH926Q

DS90UH925AQ

DS90UH926Q

DS90UH925AQ

DS90UH926Q

Auto Load from DS90UH925AQ

0x0F = 0x03

Auto Load from DS90UH925AQ

0x0F = 0x05

2

3

4

5

GPIO3

GPIO2

GPIO1

GPIO0

0x1F = 0x05

0x1F = 0x03

0x0E = 0x30

0x0E = 0x50

0x1E = 0x50

0x1E = 0x30

0x0E = 0x03

0x0E = 0x05

0x1E = 0x05

0x1E = 0x03

0x0D = 0x93

0x0D = 0x95

0x1D = 0x95

0x1D = 0x93

GPO_REG[7:4] Enable Sequence

GPO_REG[7:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2

for the GPO_REG enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925AQ only.

DS90UH926Q is automatically configured as in the 18-bit mode.

Step 2: To enable GPO_REG7 outputs an “1”, write 0x09 to address 0x11 on DS90UH925AQ.

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Table 2. GPO_REG Enable Sequencing Table

#

1

2

Description

Enable 18-bit mode

GPO_REG7

Device

Local Access

0x12 = 0x04

0x11 = 0x09

0x11 = 0x01

0x10 = 0x90

0x10 = 0x10

0x10 = 0x09

0x10 = 0x01

0x0F = 0x90

0x0F = 0x10

Local Output

DS90UH925AQ

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“0”

3

4

5

GPO_REG6

GPO_REG5

GPO_REG4

DS90UH925AQ

8.1.2.16 I2S Transmitting

In normal 24-bit RGB operation mode, the DS90UH925AQ supports 3 bits of I2S. They are I2S_CLK, I2S_WC

and I2S_DA. The optionally encrypted and packetized audio information can be transmitted during the video

blanking (data island transport) or during active video (forward channel frame transport). Note: The bit rates of

any I2S bits must maintain one fourth of the PCLK rate. The audio encryption capability is supported per HDCP

v1.3.

8.1.2.16.1 Secondary I2S Channel

In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in

addition to the 3–bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and

I2S_WC at the input to the serializer. This operation mode is enabled through either the MODE_SEL pin

(Table 4) or through the register bit 0x12[0] (Table 6). Table 3 below covers the range of I2S sample rates.

Table 3. Audio Interface Frequencies

Sample Rate (kHz)

I2S Data Word Size (bits)

I2S CLK (MHz)

1.024

32

44.1

48

16

24

32

1.411

1.536

96

3.072

192

32

6.144

1.536

44.1

48

2.117

2.304

96

4.608

192

32

9.216

2.048

44.1

48

2.822

3.072

96

6.144

192

12.288

8.1.2.16.2 HDCP

The Cipher function is implemented in the serializer per HDCP v1.3 specification. The DS90UH925AQ provides

HDCP encryption of audiovisual content when connected to an HDCP capable FPD-Link III deserializer such as

the DS90UH926Q. HDCP authentication and shared key generation is performed using the HDCP Control

Channel which is embedded in the forward and backward channels of the serial link. An on-chip Non-Volatile

Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the

manufacturing process and are not accessible external to the device.

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The DS90UH925AQ uses the Cipher engine to encrypt the data as per HDCP v1.3. The encrypted data is

transmitted through the FPD-Link III interface.

8.1.3 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the

low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for

system diagnostics. Note: BIST not available in backwards compatible mode.

8.1.3.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or

configuration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaults

to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can

select the desired OSC frequency (default 33 MHz or 25 MHz) through the register bit. When LFMODE = 1, the

pin based configuration defaults to external PCLK or 12.5 MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the

Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to

35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset

(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS

indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to

the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the

connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the

deserializer is locked or unlocked, the lock status can be read in the register. See Table 6.

Sample BIST Sequence

See Figure 14 for the BIST mode flow diagram.

Step 1:For the DS90UH925AQ and DS90UH926Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN

pin of DS90UH926Q FPD-Link III deserializer. The desired clock source is selected through BISTC pin.

Step 2:The DS90UH925AQ serializer is woken up through the back channel if it is not already on. The all zero

pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the

deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and

BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low

for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to

determine the payload error rate.

Step 3:To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there

was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST

is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4:The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 15 shows the

waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple

errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data

transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,

reducing signal condition enhancements (Rx Equalization).

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Normal

Step 1: DES in BIST

BIST

Wait

Step 2: Wait, SER in BIST

BIST

start

Step 3: DES in Normal

Mode - check PASS

BIST

stop

Step 4: DES/SER in Normal

Figure 14. BIST Mode Flow Diagram

8.1.3.2 Forward Channel and Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero

pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to

the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-

zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The

deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as

indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The

register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the

functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in

BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

BISTEN

(DES)

PCLK

(RFB = L)

RGB[7:0]

HS, VS, DE

DATA

(internal)

PASS

Prior Result

PASS

FAIL

X = bit error(s)

DATA

(internal)

X

PASS

BIST

Result

Held

Normal

SSO

Normal

BIST Test

BIST Duration

Figure 15. BIST Waveforms

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8.1.4 Internal Pattern Generation

The DS90UH925AQ serializer supports the internal pattern generation feature. It allows basic testing and

debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and

repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down

mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test

pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to SNLA132.

8.1.5 Change Summary from DS90UH925Q

The DS90UH925AQ is electrically similar to the DS90UH925Q. The changes between the devices are listed

below.

•

Pin 16, which is NC on the DS90UH925Q, becomes REM_INTB on the DS90UH925AQ. This pin mirrors the

status of INTB_IN from the remote deserializer. Any change in INTB_IN status of the remote device will be

reflected at the REM_INTB output of the serializer. No separate serializer register read will be required to

reset and change the status of this pin. Thus software complexity is reduced. Note: REM_INTB will remain

LOW until lock is achieved with the downstream deserializer.

•

Pin 13, which is I2S_CLK / GPO_REG8 on the DS90UH925Q, becomes solely I2S_CLK on the

DS90UH925AQ. Software must be updated to remove GPO_REG8, if used.

The number of allowable I2C addresses is reduced from 16 on the DS90UH925Q to 8 on the

DS90UH925AQ. The resistors in the divider network on the IDx pin may need to be updated, as well as the

I2C address in software.

•

The number of modes available through pin control is reduced from 10 on the DS90UH925Q to 8 on the

DS90UH925AQ. All modes are still available through register control. The modes removed from pin control in

the DS90UH925AQ are: (LFMODE = L, Repeater = L, Backward Compatible = L, I2S Channel B (18-bit

mode) = H) and (LFMODE = L, Repeater = L, Backward Compatible = H, I2S Channel B (18-bit mode) = L).

Backward compatibility and 18-bit mode can be configured through registers 0x04 and 0x12, respectively.

8.2 Device Functional Modes

8.2.1 Configuration Select (MODE_SEL)

Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-

up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL

input (V_R4) and V_DD33to select one of the other 10 possible selected modes. See Figure 16 and Table 4.

VDD33

R

3

4

MODE_SEL

VR4

SER

Figure 16. MODE_SEL Connection Diagram

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Device Functional Modes (continued)

Table 4. Configuration Select (MODE_SEL)

#

Ideal Ratio

V_R4/V_DD33

Ideal V_R4

(V)

Suggested

Resistor R3 kΩ Resistor R4 kΩ

Suggested

LFMODE

Repeater

Backward

Compatible

I2S Channel

B

(1% tol)

(18–bit

Mode)

1

2

3

4

5

6

7

8

0

Open

255

243

237

196

169

137

90.9

40.2 or Any

49.9

L

H

L

0.164

0.221

0.285

0.359

0.453

0.539

0.728

0.541

0.729

0.941

1.185

1.495

1.779

2.402

69.8

L

H

L

95.3

H

L

110

L

H

L

140

H

L

158

L

H^*

H

L

243

LFMODE:

L = frequency range is 15 – 85 MHz (Default)

H = frequency range is 5 – <15 MHz

Repeater:

L = Repeater OFF (Default)

H = Repeater ON

Backward Compatible:

L = Backward Compatible is OFF (Default)

H = Backward Compatible is ON; DES = DS90UR906Q or DS90UR916Q or DS90UR908Q

– frequency range = 15 - 65 MHz when LFMODE = 0

– frequency range = 5 - <15 MHz when LFMODE = 1

I2S Channel B:

L = I2S Channel B is OFF, Normal 24-bit RGB Mode (Default)

H = I2S Channel B is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by register.

8.2.2 HDCP Repeater

When DS90UH925AQ and DS90UH926Q are configured as the HDCP Repeater application, it provides a

mechanism to extend HDCP transmission over multiple links to multiple display devices. This repeater

application provides a mechanism to authenticate all HDCP Receivers in the system and distribute protected

content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.

8.2.2.1 Repeater Configuration

In HDCP repeater application, In this document, the DS90UH925AQ is referred to as the HDCP Transmitter or

transmit port (TX), and the DS90UH926Q is referred to as the HDCP Receiver (RX). Figure 17 shows the

maximum configuration supported for HDCP Repeater implementations using the DS90UH925AQ (TX) and

DS90UH926Q (RX). Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters

per HDCP Receiver.

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1:3 Repeater

Display

RX

TX

RX

TX

Source

TX

RX

Display

TX

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

1:3 Repeater

Display

RX

TX

RX

Display

RX

Figure 17. HDCP Maximum Repeater Application

To support HDCP Repeater operation, the DS90UH926Q Deserializer includes the ability to control the

downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV

list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q communicates with the I2C slave

within the DS90UH925AQ Serializer. The DS90UH925AQ Serializer handles authenticating with a downstream

HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q monitors the transmit

port status for each DS90UH925AQ and reads downstream KSV and KSV list values from the DS90UH925AQ.

In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation

includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB

format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel

LVCMOS interface communicates control information and packetized audio data during video blanking intervals.

A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and

HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and

video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.

Figure 18 provides more detailed block diagram of a 1:2 HDCP repeater configuration.

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HDCP Transmitter

DS90UH925A

downstream

Receiver

or

I2C

Slave

I2C

Master

Repeater

upstream

Transmitter

Parallel

LVCMOS

HDCP Transmitter

DS90UH925A

HDCP Receiver

DS90UH926

I2S Audio

downstream

Receiver

or

I2C

Slave

Repeater

FPD-Link III interfaces

Figure 18. HDCP 1:2 Repeater Configuration

8.2.2.2 Repeater Connections

The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP

Transmitter Figure 19.

1) Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).

2) I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33with 4.7 kΩ resistors.

3) Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.

4) IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.

5) MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.

6) Interrupt pin – Connect DS90UH926Q INTB_IN pin to DS90UH925AQ INTB pin. The signal must be pulled up

to V_DDIO

.

DS90UH926Q

DS90UH925AQ

R[7:0]

G[7:0]

B[7:0]

G[7:0]

B[7:0]

DE

VS

HS

DE

VS

HS

I2S_CLK

I2S_WC

I2S_DA

I2S_CLK

I2S_WC

I2S_DA

VDD33

Optional

VDDIO

MODE_SEL

INTB_IN

INTB

VDD33

ID[x]

SDA

SCL

SDA

SCL

Figure 19. HDCP Repeater Connection Diagram

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8.3 Programming

8.3.1 Serial Control Bus

The DS90UH925AQ is configured by the use of a serial control bus that is I2C protocol compatible. This bus is

also used by the Host source to control and monitor status of the HDCP function. Multiple serializer devices may

share the serial control bus since 16 device addresses are supported. Device address is set via R₁and R₂

values on IDx pin. See Figure 20 below.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /

Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external

pull-up resistor to V_DD33. For most applications a 4.7 k pull-up resistor to V_DD33may be used. The resistor value

may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven

Low.

V

DD33

R

1

2

V

DD33

IDx

VR2

4.7k

HOST

or

SER

or

Salve

DES

SCL

SDA

SCL

SDA

To other

Devices

Figure 20. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a

pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33to

select one of the other 16 possible addresses. Table 5 defines the required VR2 and VR2/VDD33 ratios, and

suggests standard resistor values to achieve these ratios. In systems where excessive noise may be present, we

recommend reducing the resistor values (by a factor of 10x or 100x) while maintaining the required ratio. This

provides tighter coupling to supply rails, and more stability of VR2 in the presence of coupled noise. Note that

reducing the resistor values will increase the current consumed by the resistor divider. See Table 5.

Table 5. Serial Control Bus Addresses for IDx

Ideal Ratio

V_R2/ V_DD33

Ideal V_R2

(V)

Suggested Resistor Suggested Resistor

Address 8'b

Appended

#

Address 7'b

R1 kΩ (1% tol)

R2 kΩ (1% tol)

1

2

3

4

5

6

7

8

0

Open

249

261

243

196

174

147

115

40.2 or Any

49.9

75

0x0C

0x0E

0x10

0x12

0x14

0x16

0x18

0x1A

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0.152

0.212

0.273

0.356

0.447

0.538

0.756

0.545

0.738

0.955

1.218

1.508

1.810

2.500

100

115

147

178

357

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The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See

Figure 21.

SDA

SCL

S

P

START condition, or

STOP condition

START repeat condition

Figure 21. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't

match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs

also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after

every data byte is successfully received. When the master is reading data, the master ACKs after every data

byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in Figure 22 and a WRITE is shown in Figure 23.

If the Serial Bus is not required, the three pins may be left open (NC).

Register Address

Slave Address

Data

a

c

k

a

c

k

a

c

k

a

c

k

A

2

A

1

A

0

A

2

A

1

A

0

S

1

P

Figure 22. Serial Control Bus — READ

Register Address

Slave Address

Data

a

c

a

c

k

a

c

k

A

2

A

1

A

0

S

P

k

Figure 23. Serial Control Bus — WRITE

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Table 6. Serial Control Bus Registers

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

0

0x00 I2C Device ID

7:1

0

RW

Device ID

ID Setting

7–bit address of Serializer

I2C ID Setting

1: Register I2C Device ID (Overrides IDx pin)

0: Device ID is from IDx pin

1

0x01 Reset

7

RW

0x00

Remote

Remote Auto Power Down

Auto Power 1: Power down when no Bidirectional Control

Down

Channel link is detected

0: Do not power down when no Bidirectional Control

Channel link is detected

6:2

1

Reserved.

RW

Digital

RESET1

Reset the entire digital block including registers

This bit is self-clearing.

1: Reset

0: Normal operation

0

7

Digital

RESET0

Reset the entire digital block except registers

This bit is self-clearing

1: Reset

0: Normal operation

3

0x03 Configuration

[0]

0xD2

Back

channel

CRC

Back Channel Check Enable

1: Enable

0: Disable

Checker

Enable

6

5

Reserved.

RW

I2C Remote Automatically Acknowledge I2C Remote Write

Write Auto When enabled, I2C writes to the Deserializer (or

Acknowledg any remote I2C Slave, if I2C PASS ALL is enabled)

e

are immediately acknowledged without waiting for

the Deserializer to acknowledge the write. This

allows higher throughput on the I2C bus

1: Enable

0: Disable

4

3

RW

Filter

Enable

HS, VS, DE two clock filter When enabled, pulses

less than two full PCLK cycles on the DE, HS, and

VS inputs will be rejected

1: Filtering enable

0: Filtering disable

I2C Pass-

through

I2C Pass-Through Mode

1: Pass-Through Enabled

0: Pass-Through Disabled

2

1

Reserved

RW

PCLK Auto Switch over to internal OSC in the absence of PCLK

1: Enable auto-switch

0: Disable auto-switch

0

TRFB

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the Rising

Clock Edge.

0: Parallel Interface Data is strobed on the Falling

Clock Edge.

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

4

0x04 Configuration

[1]

7

RW

0x80

Failsafe

State

Input Failsafe State

1: Failsafe to Low

0: Failsafe to High

6

5

Reserved

RW

CRC Error Clear back channel CRC Error Counters

Reset

This bit is NOT self-clearing

1: Clear Counters

0: Normal Operation

4

3

Reserved

RW

Backward

Backward Compatible (BC) mode set by

Compatible MODE_SEL pin or register

select by

pin or

1: BC is set by register bit. Use register bit

reg_0x04[2] to set BC Mode

register

control

0: BC is set by MODE_SEL pin.

2

1

0

RW

Backward

Backward compatible (BC) mode to DS90UR906Q

Compatible or DS90UR908Q, if reg_0x04[3] = 1

Mode

Select

1: Backward compatible with DS90UR906Q or

DS90UR908Q

0: Backward Compatible is OFF (default)

LFMODE

select by

pin or

register

control

Frequency range is set by MODE_SEL pin or

register

1: Frequency range is set by register. Use register

bit reg_0x04[0] to set LFMODE

0: Frequency range is set by MODE_SEL pin.

LFMODE

Frequency range select

1: PCLK range = 5 MHz - <15 MHz), if reg_0x04[1]

= 1

0: PCLK range = 15 MHz - 85 MHz (default)

5

0x05 I2C Control

7:5

4:3

0x00

Reserved

RW

SDA Output SDA output delay

Delay Configures output delay on the SDA output. Setting

this value will increase output delay in units of 40ns.

Nominal output delay values for SCL to SDA are

00: 240ns

01: 280ns

10: 320ns

11: 360ns

2

Local Write Disable remote writes to local registers

Disable

Setting the bit to a 1 prevents remote writes to local

device registers from across the control channel. It

prevents writes to the Serializer registers from an

I2C master attached to the Deserializer.

Setting this bit does not affect remote access to I2C

slaves at the Serializer

1

0

RW

I2C Bus

Timer

Speedup

Speed up I2C bus watchdog timer

1: Watchdog timer expires after ~50 ms.

0: Watchdog Timer expires after ~1 s

I2C Bus

timer

Disable

Disable I2C bus watchdog timer

When the I2C watchdog timer may be used to

detect when the I2C bus is free or hung up following

an invalid termination of a transaction.

If SDA is high and no signalling occurs for ~1 s, the

I2C bus assumes to be free. If SDA is low and no

signaling occurs, the device attempts to clear the

bus by driving 9 clocks on SCL

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

6

0x06 DES ID

7:1

RW

0x00

DES Device 7-bit Deserializer Device ID

ID

Configures the I2C Slave ID of the remote

Deserializer. A value of 0 in this field disables I2C

access to the remote Deserializer. This field is

automatically configured by the Bidirectional Control

Channel once RX Lock has been detected.

Software may overwrite this value, but should also

assert the FREEZE DEVICE ID bit to prevent

overwriting by the Bidirectional Control Channel.

0

RW

Device ID

Frozen

Freeze Deserializer Device ID

Prevents autoloading of the Deserializer Device ID

by the Bidirectional Control Channel. The ID will be

frozen at the value written.

7

0x07 Slave ID

7:1

0X00

Slave

7-bit Remote Slave Device ID

Device ID

Configures the physical I2C address of the remote

I2C Slave device attached to the remote

Deserializer. If an I2C transaction is addressed to

the Slave Device Alias ID, the transaction will be

remapped to this address before passing the

transaction across the Bidirectional Control Channel

to the Deserializer

0

Reserved

8

0x08 Slave Alias

7:1

RW

0x00

Slave

7-bit Remote Slave Device Alias ID

Device

Alias ID

Assigns an Alias ID to an I2C Slave device attached

to the remote Deserializer. The transaction will be

remapped to the address specified in the Slave ID

register. A value of 0 in this field disables access to

the remote I2C Slave.

0

Reserved

10

11

12

0x0A CRC Errors

0x0B

7:0

R

0x00

CRC Error Number of back channel CRC errors – 8 least

LSB significant bits

7:0

CRC Error Number of back channel CRC errors – 8 most

MSB

significant bits

0x0C General Status

7:4

3

Reserved

R

BIST CRC Back channel CRC error during BIST

Error

communication with Deserializer.

The bit is cleared upon loss of link, restart of BIST,

or assertion of CRC ERROR RESET in register

0x04.

2

1

R

PCLK

Detect

PCLK Status

1: Valid PCLK detected

0: Valid PCLK not detected

DES Error

Back channel CRC error during communication with

Deserializer.

The bit is cleared upon loss of link or assertion of

CRC ERROR RESET in register 0x04.

0

R

LINK Detect LINK Status

1: Cable link detected

0: Cable link not detected (Fault Condition)

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

13

0x0D Revision ID and

GPIO0

7:4

R

0xA0

Rev-ID

Revision ID: 1010

Production Device

Configuration

3

2

RW

GPIO0

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the

GPIO function is enabled, the local GPIO direction

is Output, and remote GPIO control is disabled.

RW

GPIO0

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

7

RW

GPIO0

Direction

Local GPIO Direction

1: Input

0: Output

GPIO0

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

14

0x0E GPIO2 and

GPIO1

0x0

GPIO2

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the

GPIO function is enabled, the local GPIO direction

is Output, and remote GPIO control is disabled.

Configurations

6

RW

GPIO2

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

5

4

3

RW

GPIO2

Direction

Local GPIO Direction

1: Input

0: Output

GPIO2

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

GPIO1

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the

GPIO function is enabled, the local GPIO direction

is Output, and remote GPIO control is disabled.

2

RW

GPIO1

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

RW

GPIO1

Direction

Local GPIO Direction

1: Input

0: Output

GPIO1

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

15

0x0F GPO_REG4

and GPIO3

7

RW

0x00

GPO_REG Local GPO_REG4 output value

4 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

Configurations

(The local GPO direction is Output, and remote

GPO control is disabled)

6:5

4

Reserved

RW

GPO_REG GPO_REG4 function enable

4 Enable

1: Enable GPO operation

0: Enable normal operation

3

2

GPIO3

Output

Value

Local GPIO output value

This value is output on the GPIO pin when the

GPIO function is enabled, the local GPIO direction

is Output, and remote GPIO control is disabled.

RW

GPIO3

Remote

Enable

Remote GPIO control

1: Enable GPIO control from remote Deserializer.

The GPIO pin will be an output, and the value is

received from the remote Deserializer.

0: Disable GPIO control from remote Deserializer.

1

0

7

RW

GPIO3

Direction

Local GPIO Direction

1: Input

0: Output

GPIO3

Enable

GPIO function enable

1: Enable GPIO operation

0: Enable normal operation

16

0x10 GPO_REG6

and

0x00

GPO_REG Local GPO_REG6 output value

6 Output

Value

This value is output on the GPO pin when the GPO

function is enabled.

(The local GPO direction is Output, and remote

GPO control is disabled)

GPO_REG5

Configurations

6:5

4

Reserved

RW

GPO_REG GPO_REG6 function enable

6 Enable

1: Enable GPO operation

0: Enable normal operation

3

GPO_REG Local GPO_REG5 output value

5 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.

2:1

0

Reserved

RW

GPO_REG GPO_REG5 function enable

5 Enable

1: Enable GPO operation

0: Enable normal operation

17

0x11 GPO_REG7

Configuration

7:4

3

0x00

Reserved

GPO_REG Local GPO_REG7 output value

7 Output

Value

This value is output on the GPO pin when the GPO

function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.

2:1

0

Reserved

RW

GPO_REG GPO_REG7 function enable

7 Enable

1: Enable GPO operation

0: Enable normal operation

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

18

0x12 Data Path

Control

7

6

0x00

Reserved

RW

Pass RGB Setting this bit causes RGB data to be sent

independent of DE.

It allows operation in systems which may not use

DE to frame video data or send other data when DE

is de-asserted.

Note that setting this bit prevents HDCP operation

and blocks packetized audio.

This bit does not need to be set in Backwards

Compatible mode

1: Pass RGB independent of DE

0: Normal operation

(DE gates RGB data transmission - RGB data is

transmitted only when DE is active)

5

4

3

2

RW

DE Polarity The bit indicates the polarity of the Data Enable

(DE) signal.

1: DE is inverted (active low, idle high)

0: DE is positive (active high, idle low)

I2S

I2S Repeater Regeneration

Repeater

1: Repeater regenerate I2S from I2S pins

Regenerati 0: Repeater pass through I2S from video pins

on

I2S

I2S Channel B Enable

Channel B 1: Set I2S Channel B Enable from reg_0x12[0]

Enable

0: Set I2S Channel B Enable from MODE_SEL pin

Override

18-bit Video 18–bit video select

Select

1: Select 18-bit video mode

Note: use of GPIO(s) on unused inputs must be

enabled by register.

0: Select 24-bit video mode

1

0

RW

I2S

Transport

Select

I2S Transport Mode Select

1: Enable I2S Data Forward Channel Frame

Transport

0: Enable I2S Data Island Transport

I2S

I2S Channel B Enable

Channel B 1: Enable I2S Channel B on B1 input

Enable

0: I2S Channel B disabled

19

0x13 Mode Status

7:5

4

0x10

Reserved

R

MODE_SE MODE_SEL Status

L

1: MODE_SEL decode circuit is completed

0: MODE_SEL decode circuit is not completed

3

2

1

0

Low

Low Frequency Mode Status

Frequency 1: Low frequency (5 - <15 MHz)

Mode

0: Normal frequency (15 - 85 MHz)

Repeater

Mode

Repeater Mode Status

1: Repeater mode ON

0: Repeater Mode OFF

Backward

Backward Compatible Mode Status

Compatible 1: Backward compatible ON

Mode

0: Backward compatible OFF

I2S

I2S Channel B Mode Status

Channel B 1: I2S Channel B ON, 18-bit RGB mode with

Mode

I2S_DB enabled

0: I2S Channel B OFF; normal 24-bit RGB mode

34

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ZHCSCL3 –JUNE 2014

Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

20

0x14 Oscillator Clock

Source and

7:3

2:1

0x00

Reserved

RW

OSC Clock OSC Clock Source

BIST Status

Source

(When LFMODE = 1, Oscillator = 12.5 MHz ONLY)

00: External Pixel Clock

01: 33 MHz Oscillator

10: Reserved

11: 25 MHz Oscillator

0

R

BIST

Enable

Status

BIST status

1: Enabled

0: Disabled

22

0x16 BCC Watchdog

Control

7:1

RW

0xFE

Timer Value The watchdog timer allows termination of a control

channel transaction if it fails to complete within a

programmed amount of time.

This field sets the Bidirectional Control Channel

Watchdog Timeout value in units of 2 ms.

This field should not be set to 0

0

7

RW

Timer

Control

Disable Bidirectional Control Channel Watchdog

Timer

1: Disables BCC Watchdog Timer operation

0: Enables BCC Watchdog Timer operation

23

0x17 I2C Control

0x5E

I2C Pass

All

I2C Control

1: Enable Forward Control Channel pass-through of

all I2C accesses to I2C Slave IDs that do not match

the Serializer I2C Slave ID.

0: Enable Forward Control Channel pass-through

only of I2C accesses to I2C Slave IDs matching

either the remote Deserializer Slave ID or the

remote Slave ID.

6

Reserved

5:4

RW

SDA Hold

Time

Internal SDA Hold Time

Configures the amount of internal hold time

provided for the SDA input relative to the SCL input.

Units are 40 ns

3:0

7:0

RW

I2C Filter

Depth

Configures the maximum width of glitch pulses on

the SCL and SDA inputs that will be rejected. Units

are 5 ns

24

25

0x18 SCL High Time

0xA1

0xA5

SCL HIGH I2C Master SCL High Time

Time

This field configures the high pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. Units are 40 ns for the nominal oscillator

clock frequency. The default value is set to provide

a minimum 5us SCL high time with the internal

oscillator clock running at 32.5 MHz rather than the

nominal 25MHz.

0x19 SCL Low Time

7:0

RW

SCL LOW

Time

I2C SCL Low Time

This field configures the low pulse width of the SCL

output when the Serializer is the Master on the local

I2C bus. This value is also used as the SDA setup

time by the I2C Slave for providing data prior to

releasing SCL during accesses over the

Bidirectional Control Channel. Units are 40 ns for

the nominal oscillator clock frequency. The default

value is set to provide a minimum 5us SCL low time

with the internal oscillator clock running at 32.5 MHz

rather than the nominal 25MHz.

27

0x1B BIST BC Error

7:0

R

0x00

BIST Back BIST Mode Back Channel CRC Error Counter

Channel This error counter is active only in the BIST mode. It

CRC Error clears itself at the start of the BIST run.

Counter

35

DS90UH925AQ-Q1

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

100

0x64 Pattern

Generator

Control

7:4

RW

0x10

Pattern

Generator

Select

Fixed Pattern Select

This field selects the pattern to output when in Fixed

Pattern Mode. Scaled patterns are evenly

distributed across the horizontal or vertical active

regions. This field is ignored when Auto-Scrolling

Mode is enabled. The following table shows the

color selections in non-inverted followed by inverted

color mode

0000: Reserved

0001: White/Black

0010: Black/White

0011: Red/Cyan

0100: Green/Magenta

0101: Blue/Yellow

0110: Horizontally Scaled Black to White/White to

Black

0111: Horizontally Scaled Black to Red/Cyan to

White

1000: Horizontally Scaled Black to Green/Magenta

to White

1001: Horizontally Scaled Black to Blue/Yellow to

White

1010: Vertically Scaled Black to White/White to

Black

1011: Vertically Scaled Black to Red/Cyan to White

1100: Vertically Scaled Black to Green/Magenta to

White

1101: Vertically Scaled Black to Blue/Yellow to

White

1110: Custom color (or its inversion) configured in

PGRS, PGGS, PGBS registers

1111: Reserved

3:1

0

Reserved

RW

Pattern

Generator

Enable

Pattern Generator Enable

1: Enable Pattern Generator

0: Disable Pattern Generator

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

101

0x65 Pattern

Generator

Configuration

7:5

4

0x00

Reserved

RW

Pattern

Generator

18 Bits

18-bit Mode Select

1: Enable 18-bit color pattern generation. Scaled

patterns will have 64 levels of brightness and the R,

G, and B outputs use the six most significant color

bits.

0: Enable 24-bit pattern generation. Scaled patterns

use 256 levels of brightness.

3

2

Pattern

Generator

External

Clock

Select External Clock Source

1: Selects the external pixel clock when using

internal timing.

0: Selects the internal divided clock when using

internal timing

This bit has no effect in external timing mode

(PATGEN_TSEL = 0).

Pattern

Generator

Timing

Timing Select Control

1: The Pattern Generator creates its own video

timing as configured in the Pattern Generator Total

Frame Size, Active Frame Size. Horizontal Sync

Width, Vertical Sync Width, Horizontal Back Porch,

Vertical Back Porch, and Sync Configuration

registers.

Select

0: the Pattern Generator uses external video timing

from the pixel clock, Data Enable, Horizontal Sync,

and Vertical Sync signals.

1

0

RW

Pattern

Generator

Enable Inverted Color Patterns

1: Invert the color output.

Color Invert 0: Do not invert the color output.

Pattern

Auto-Scroll Enable:

Generator

1: The Pattern Generator will automatically move to

Auto-Scroll the next enabled pattern after the number of frames

Enable

specified in the Pattern Generator Frame Time

(PGFT) register.

0: The Pattern Generator retains the current pattern.

102

103

0x66 Pattern

7:0

RW

0x00

Indirect

Address

This 8-bit field sets the indirect address for

accesses to indirectly-mapped registers. It should

be written prior to reading or writing the Pattern

Generator Indirect Data register.

Generator

Indirect Address

See AN-2198 (SNLA132)

0x67 Pattern

Indirect

Data

When writing to indirect registers, this register

contains the data to be written. When reading from

indirect registers, this register contains the read

back value.

Generator

Indirect Data

See AN-2198 ( SNLA132)

128

129

130

131

132

144

145

146

147

148

0x80 RX_BKSV0

0x81 RX_BKSV1

0x82 RX_BKSV2

0x83 RX_BKSV3

0x84 RX_BKSV4

0x90 TX_KSV0

0x91 TX_KSV1

0x92 TX_KSV2

0x93 TX_KSV3

0x94 TX_KSV4

7:0

R

0x00

RX BKSV0 BKSV0: Value of byte 0 of the Deserializer KSV

RX BKSV1 BKSV1: Value of byte 1 of the Deserializer KSV

RX BKSV2 BKSV2: Value of byte 2 of the Deserializer KSV

RX BKSV3 BKSV3: Value of byte 3of the Deserializer KSV

RX BKSV4 BKSV4: Value of byte 4of the Deserializer KSV

TX KSV0

TX KSV1

TX KSV2

TX KSV3

TX KSV4

KSV0: Value of byte 0 of the Serializer KSV

KSV1: Value of byte 1 of the Serializer KSV

KSV2: Value of byte 2 of the Serializer KSV

KSV3: Value of byte 3 of the Serializer KSV

KSV4: Value of byte 4 of the Serializer KSV

37

DS90UH925AQ-Q1

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

160

0xA0 RX BCAPS

7

6

0x13

Reserved

R

Repeater

Indicates if the attached Receiver supports

downstream connections. This bit is valid once the

Bksv is ready as indicated by the BKSV_RDY bit in

the HDCP

5

4

R

KSV FIFO

Fast I2C

KSV FIFO Ready

Indicates the receiver has built the list of attached

KSVs and computed the verification value

Fast I2C: The HDCP Receiver supports fast I2C.

Since the I2C is embedded in the serial data, this bit

is not relevant

3:2

1

Reserved

R

Features

HDCP v1.1_Features

The HDCP Receiver supports the Enhanced

Encryption Status Signaling (EESS), Advance

Cipher, and Enhanced Link Verification options.

0

7

R

Fast Re-

auth

The HDCP Receiver is capable of receiving

(unencrypted) video signal during the session re-

authentication.

161

0xA1 RX BSTATUS0

0x00

Max

Devices

Maximum Devices Exceeded: Indicates a topology

error was detected. Indicates the number of

downstream devices has exceeded the depth of the

Repeater's KSV FIFO

6:0

R

Device

Count

Total number of attached downstream device. For a

Repeater, this will indicate the number of

downstream devices, not including the Repeater.

For an HDCP Receiver that is not also a Repeater,

this field will be 0

162

0xA2 RX BSTATUS1

7:4

3

0x00

Reserved

R

Max

Cascade

Maximum Cascade Exceeded: Indicates a topology

error was detected. Indicates that more than seven

levels of repeaters have been cascad-ed together

2:0

7:0

R

Cascade

Depth

Indicates the number of attached levels of devices

for the Repeater

163

192

0xA3 KSV FIFO

0xC0 HDCP DBG

0x00

KSV FIFO

Each read of the KSV FIFO returns one byte of the

KSV FIFO list composed by the downstream

Receiver.

7:4

3

Reserved

RW

RGB

CHKSUM

Enable RGB video line checksum

Enables sending of ones-complement checksum for

each 8-bit RBG data channel following end of each

video data line

2

Fast LV

Fast Link Verification

HDCP periodically verifies that the HDCP Receiver

is correctly synchronized. Setting this bit will

increase the rate at which synchronization is

verified. When set to a 1, Pj is computed every 2

frames and Ri is computed every 16 frames. When

set to a 0, Pj is computed every 16 frames and Ri is

computed every 128 frames.

1

0

RW

TMR Speed Timer Speedup

Up

Speed up HDCP authentication timers.

HDCP I2C HDCP I2C Fast Mode Enable

Fast

Setting this bit to a 1 will enable the HDCP I2C

Master in the HDCP Receiver to operate with Fast

mode timing. If set to a 0, the I2C Master will

operate with Standard mode timing. This bit is

mirrored in the IND_STS register

38

DS90UH925AQ-Q1

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

194

0xC2 HDCP CFG

7

RW

0x80

ENH LV

Enable Enhanced Link Verification

Allows checking of the encryption Pj value on every

16th frame

1: Enhanced Link Verification enabled

0: Enhanced Link Verification disabled

6

5

HDCP

EESS

Enables Enhanced Encryption Status Signaling

(EESS) instead of the Original Encryption Status

Signaling (OESS)

1: EESS mode enabled

0: OESS mode enabled

TX RPTR

Transmit Repeater Enable

Enables the transmitter to act as a repeater. In this

mode, the HDCP Transmitter incorporates the

additional authentication steps required of an HDCP

Repeater.

1: Transmit Repeater mode enabled

0: Transmit Repeater mode disabled

4:3

RW

ENC Mode Encryption Control Mode

Determines mode for controlling whether encryption

is required for video frames

00: Enc_Authenticated

01: Enc_Reg_Control

10: Enc_Always

11: Enc_InBand_Control (per frame)

If the Repeater strap option is set at power-up,

Enc_InBand_Control (ENC_MODE == 11) will be

se-lected. Otherwise, the default will be

Enc_Authenticated mode (ENC_MODE == 00).

2

RW

Wait

Enable 100ms Wait

The HDCP 1.3 specification allows for a 100ms wait

to allow the HDCP Receiver to compute the initial

encryption values. The FPD-Link III implementation

ensures that the Receiver will complete the

computations before the HDCP Transmitter. Thus

the timer is unnecessary. To enable the 100ms

timer, set this bit to a 1.

1

0

RW

RX DET

SEL

RX Detect Select

Controls assertion of the Receiver Detect Interrupt.

If set to 0, the Receiver Detect Interrupt will be

asserted on detection of an FPD-Link III Receiver. If

set to 1, the Receiver Detect Interrupt will also

require a receive lock indication from the receiver.

HDCP AV

MUTE

Enable AVMUTE

Setting this bit to a 1 will initiate AVMUTE operation.

The transmitter will ignore encryption status controls

while in this state. If this bit is set to a 0, normal

operation resumes. This bit may only be set if the

HDCP_EESS bit is also set.

39

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

195

0xC3 HDCP CTL

7

RW

0x00

HDCP RST HDCP Reset

Setting this bit will reset the HDCP transmitter and

disable HDCP authentication. This bit is self-

clearing.

6

5

Reserved

RW

KSV List

Valid

The controller sets this bit after validating the

Repeater’s KSV List against the Key revocation list.

This allows completion of the Authentication

process. This bit is self-clearing

4

KSV Valid

The controller sets this bit after validating the

Receiver’s KSV against the Key revocation list. This

allows continuation of the Authentication process.

This bit will be cleared upon assertion of the

KSV_RDY flag in the HDCP_STS register. Setting

this bit to a 0 will have no effect

3

2

RW

HDCP ENC HDCP Encrypt Disable

DIS Disables HDCP encryption. Setting this bit to a 1 will

cause video data to be sent without encryption.

Authentication status will be maintained. This bit is

self-clearing

HDCP ENC HDCP Encrypt Enable

EN Enables HDCP encryption. When set, if the device

is authenticated, encrypted data will be sent. If

device is not authenticated, a blue screen will be

sent. Encryption should always be enabled when

video data requiring content protection is being

supplied to the transmitter. When this bit is not set,

video data will be sent without encryption. Note that

when CFG_ENC_MODE is set to Enc_Always, this

bit will be read only with a value of 1

1

0

RW

HDCP DIS HDCP Disable

Disables HDCP authentication. Setting this bit to a 1

will disable the HDCP authentication.

This bit is self-clearing

HDCP EN

HDCP Enable/Restart

Enables HDCP authentication. If HDCP is already

enabled, setting this bit to a 1 will restart

authentication. Setting this bit to a 0 will have no

effect. A register read will return the current HDCP

enabled status

40

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ZHCSCL3 –JUNE 2014

Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

196

0xC4 HDCP STS

7

R

0x00

I2C ERR

DET

HDCP I2C Error Detected

This bit indicates an error was detected on the

embedded communications channel with the HDCP

Receiver. Setting of this bit might indicate that a

problem exists on the link between the HDCP

Transmitter and HDCP Receiver. This bit will be

cleared on read

6

R

RX INT

RX Interrupt

Status of the RX Interrupt signal.

The signal is received from the attached HDCP

Receiver and is the status on the INTB_IN pin of the

HDCP Receiver. The signal is active low, a 0

indicates an interrupt condition

5

4

R

RX Lock

DET

Receiver Lock Detect

This bit indicates that the downstream Receiver has

indicated Receive Lock to incoming serial data

DOWN

HPD

Hot Plug Detect

This bit indicates the local device or a downstream

repeater has reported a Hot Plug event, indicating

addition of a new receiver. This bit will be cleared

on read

3

2

R

RX DET

Receiver Detect

This bit indicates that a downstream Receiver has

been detected

KSV LIST

RDY

HDCP Repeater KSV List Ready

This bit indicates that the Receiver KSV list has

been read and is available in the KSV_FIFO

registers. The device will wait for the controller to

set the KSV_LIST_VALID bit in the HDCP_CTL

register before continuing. This bit will be cleared

once the controller sets the KSV_LIST_VALID bit.

1

R

KSV RDY

HDCP Receiver KSV Ready

This bit indicates that the Receiver KSV has been

read and is available in the HDCP_ BKSV registers.

If the device is not a Repeater, it will wait for the

controller to set the KSV_VALID bit in the

HDCP_CTL register before continuing.

This bit will be cleared once the controller sets the

KSV_VALID bit.. The bit will also be cleared if

authentication fails.

0

R

AUTHED

HDCP Authenticated

Indicates the HDCP authentication has completed

successfully. The controller may now send video

data requiring content protection. This bit will be

cleared if authentication is lost or if the controller

restarts authentication

41

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Table 6. Serial Control Bus Registers (continued)

ADD

(dec)

ADD

(hex)

Register

Type

Default

(hex)

Register Name

Bit(s)

Function

Description

198

0xC6 HDCP ICR

7

RW

0x00

IE IND ACC Interrupt on Indirect Access Complete

Enables interrupt on completion of Indirect Register

Access

6

5

RW

IE RXDET

INT

Interrupt on Receiver Detect

Enables interrupt on detection of a downstream

Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1,

the interrupt will wait for Receiver Lock Detect.

RW

IS_RX_INT Interrupt on Receiver interrupt

Enables interrupt on indication from the HDCP

Receiver. Allows propagation of interrupts from

downstream devices

4

3

2

RW

IE LIST

RDY

Interrupt on KSV List Ready

Enables interrupt on KSV List Ready

IE KSV

RDY

Interrupt on KSV Ready

Enables interrupt on KSV Ready

IE AUTH

FAIL

Interrupt on Authentication Failure

Enables interrupt on authentication failure or loss of

authentication

1

0

RW

IE AUTH

PASS

Interrupt on Authentication Pass

Enables interrupt on successful completion of

authentication

INT Enable Global Interrupt Enable

Enables interrupt on the interrupt signal to the

controller.

199

0xC7 HDCP ISR

7

6

5

R

0x00

IS IND ACC Interrupt on Indirect Access Complete

Indirect Register Access has completed

INT Detect Interrupt on Receiver Detect interrupt

A downstream receiver has been detected

IS RX INT

Interrupt on Receiver interrupt

Receiver has indicated an interrupt request from

down-stream device

4

3

R

IS LIST

RDY

Interrupt on KSV List Ready

The KSV list is ready for reading by the controller

IS KSV

RDY

Interrupt on KSV Ready

The Receiver KSV is ready for reading by the

controller

2

R

IS AUTH

FAIL

Interrupt on Authentication Failure

Authentication failure or loss of authentication has

occurred

1

0

R

IS AUTH

PASS

Interrupt on Authentication Pass

Authentication has completed successfully

INT

Global Interrupt

Set if any enabled interrupt is indicated

240

241

242

0xF0 HDCP TX ID

7:0

R

0x5F

0x55

0x48

ID0

ID1

ID2

First byte ID code, ‘_’

0xF1

0xF2

Second byte of ID code, ‘U’

Third byte of ID code. Value will be either ‘B’ or ‘H’.

‘H’ indicates an HDCP capable device

243

244

245

0xF3

0xF4

0xF5

7:0

R

0x39

0x32

0x35

ID3

ID4

ID5

Forth byte of ID code: ‘9’

Fifth byte of ID code: '2'

Sixth byte of ID code: '5'

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DS90UH925AQ-Q1

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ZHCSCL3 –JUNE 2014

9 Application and Implementation

9.1 Application Information

The DS90UH925AQ, in conjunction with the DS90UH926Q, is intended for interface between a HDCP compliant

host (graphics processor) and a Display. It supports a 24-bit color depth (RGB888) and high definition (720p)

digital video format. It can receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three

control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz. The

included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q, which decrypts both

video and audio contents. The keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum security.

9.2 Typical Application

V

DD33

V

DDIO

V

DDIO

V

DD33

(1.8Vor3.3V) (3.3V)

(3.3V) (1.8Vor3.3V)

R[7:0]

G[7:0]

R[7:0]

G[7:0]

FPD-Link III

1 Pair /AC Coupled

B[7:0]

HS

VS

DE

PCLK

0.1 PF

HOST

Graphics

Processor

RGB Display

720p

24-bit color depth

HS

DOUT+

DOUT-

RIN+

RIN-

VS

DE

PCLK

100 ohm STP Cable

DS90UH925AQ

Serializer

DS90UH926Q

Deserializer

LOCK

PASS

PDB

OSS_SEL

OEN

PDB

3

/

I2S AUDIO

(STEREO)

3

/

I2S AUDIO

(STEREO)

MCLK

MODE_SEL

INTB

REM_INTB

INTB_IN

SCL

SDA

IDx

SCL

SDA

IDx

DAP

Figure 24. Typical Display System Diagram

9.2.1 Design Requirements

For the typical design application, use the following as input parameters.

Table 7. Design Parameters

Design Parameter

VDDIO

Example Value

1.8 V or 3.3 V

3.3 V

VDD33

AC Coupling Capacitor for DOUT±

PCLK Frequency

100 nF

85 MHz

9.2.2 Detailed Design Procedure

9.2.2.1 Typical Application Connection

Figure 25 shows a typical application of the DS90UH925AQ serializer for an 85 MHz 24-bit Color Display

Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines.

The serializer has an internal termination. Bypass capacitors are placed near the power supply pins. At a

minimum, six (6) 4.7μF capacitors (and two (2) additional 1μF capacitors should be used for local device

bypassing. Ferrite beads are placed on the two (2) VDDs (V_DD33and V_DDIO) for effective noise suppression. The

interface to the graphics source is with 3.3 V LVCMOS levels, thus the V_DDIOpin is connected to the 3.3 V rail. A

RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.

43

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VDDIO

DS90UH925AQ

3.3V/1.8V

VDD33

3.3V

VDDIO

VDD33

CAPP12

CAPL12

FB1

C5

FB2

C4

R7

R6

R5

R4

R3

R2

R1

R0

C6

C7

C9

C8

CAPHS12

G7

G6

G5

G4

G3

G2

G1

G0

C1

Serial

DOUT+

DOUT-

CMF

LVCMOS

Parallel

Video

FPD-Link III

Interface

C2

Interface

C3

B7

B6

B5

B4

B3

B2

B1

B0

VDD33

R

3

MODE_SEL

PCLK

R

4

HS

VS

DE

VDD33

VDDIO VDD33*

NOTE:

FB1-FB2: Impedance = 1 k: @ 100MHz,

Low DC resistance (<1:)

C1-C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)

C4-C9 = 4.7 PF

R

1

R

6

5

REM_INTB

INTB

ID[X]

SCL

SDA

LVCMOS

Control

Interface

R

2

PDB

C10 =>10 PF

C10

R

1

R

3

R

5

R

6

and R (see IDx Resistor Values Table 5)

2

NC

and R (see MODE_SEL Resistor Values Table 1)

4

I2S_CLK

I2S_WC

I2S_DA

RES

DAP (GND)

= 10 k:

= 4.7 k:

* or VDDIO = 3.3V+0.3V

Figure 25. Typical Connection Diagram

9.2.2.2 Power Up Requirements and PDB Pin

When power is applied, the V_DDIOsupply needs to reach the expected operating voltage (1.8V or 3.3V) before

the other supply (V_DD33) begins to ramp. It is acceptable if both supplies ramp at the same time. The VDDs

(V_DD33and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB

pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage.

When PDB pin is pulled to V_DDIO= 3.0 V to 3.6 V or V_DD33, it is recommended to use a 10 kΩ pull-up and a >10

uF cap to GND to delay the PDB input signal.

All inputs must not be driven until V_DD33and V_DDIOhas reached its steady state value.

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ZHCSCL3 –JUNE 2014

9.2.2.3 CML Interconnect Guidelines

See AN-1108 ( SNLA008) and AN-1187(SNLA035) for full details.

•

Use 100 Ω coupled differential pairs

Use the S/2S/3S rule in spacings

–

S = space between the pair

2S = space between pairs

3S = space to LVCMOS signal

•

Minimize the number of Vias

Use differential connectors when operating above 500 Mbps line speed

Maintain balance of the traces

Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI

web site at: www.ti.com/lvds

9.2.2.4 Application Curves

Time (100 ps/DIV)

Time (2.5 ns/DIV)

Figure 26. Serializer Eye Diagram at 2.73 Gbps Serial Data

Rate

Figure 27. Serializer CML Output with 78MHz TX Pixel

Clock

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DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

10 Power Supply Recommendations

This device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separate

power and ground Terminals for different portions of the circuit. This is done to isolate switching noise effects

between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal

Description tables typically provide guidance on which circuit blocks are connected to which power Terminal

pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

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11 Layout

11.1 Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power

feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to

minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly

improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane

capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at

high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01µF to 0.1µF. Tantalum capacitors may be in the 2.2µF to 10µF range. Voltage rating of the tantalum

capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50µF to 100µF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body

size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of

these external bypass capacitors, usually in the range of 20-30MHz. To provide effective bypassing, multiple

capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At

high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing

the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as

PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML

lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100Ω are

typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will

appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

Information on the WQFN-style package is provided in TI SNOA401.

11.2 Layout Example

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste

deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve

board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow

unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

47

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

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Layout Example (continued)

Figure 28. No Pullback WQFN, Single Row Reference Diagram

Table 8. No Pullback WQFN Stencil Aperture Summary for DS90UH925AQ-Q1

Gap

Between

DAP

Aperture

(Dim A

mm)

Stencil

DAP

Aperture

(mm)

Number of

DAP

Aperture

Openings

PCB I/O

Pad Size

(mm)

Stencil I/O

Aperture

(mm)

Count

PCB Pitch

(mm)

PCB DAP

size(mm)

Device

MKT Dwg

DS90UH925A

Q-Q1

48

SNA48A

0.25 x 0.6

0.5

5.1 x 5.1

0.25 x 0.7

1.1 x 1.1

16

0.2

Figure 29. 48-Pin WQFN Stencil Example of Via and Opening Placement

The following PCB layout example is derived from the EVM layout of the DS90UH925AQ. This graphics and

additional layout description are used to demonstrate both proper routing and proper solder techniques when

designing in the Seralizer.

48

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Figure 30. DS90UH925AQ-Q1 Serializer Example Layout

49

DS90UH925AQ-Q1

ZHCSCL3 –JUNE 2014

www.ti.com.cn

12 器件和文档支持

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

50

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	DS90UR124IVS
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	NATIONAL SEMICONDUCTOR CORP
包装说明：	10 X 10 MM, 1 MM HEIGHT, 0.50 PITCH, TQFP-64
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.26
Is Samacsys：	N
差分输出：	YES
驱动器位数：	1
输入特性：	STANDARD
接口集成电路类型：	LINE RECEIVER
接口标准：	GENERAL PURPOSE
JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0
长度：	10 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	64
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP
封装等效代码：	TQFP64,.47SQ
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
最大接收延迟：
接收器位数：	1
座面最大高度：	1.2 mm
子类别：	Line Driver or Receivers
最大压摆率：	95 mA
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	40
宽度：	10 mm
Base Number Matches：	1

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