EL7534
has adverse effect on overall circuit if close to 100% duty
ratio is expected.
(V - V ) × V
O
IN
O
∆I = --------------------------------------------
IL
L × V × f
IN
S
RSI/POR Function
• L is the inductance
When powering up, the open-collector Power-On-Reset
• f the switching frequency (nominally 1.5MHz)
S
output holds low for about 100ms after V reaches the
O
The inductor must be able to handle I for the RMS load
O
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to the timing
diagram). When the function is not used, connect RSI to
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
Current Limit and Short-Circuit Protection
ground and leave open the pull-up resister R at POR pin.
4
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resister R is installed. The
4
RSI pin needs to be directly (or indirectly through a resister
R ) connected to Ground for this to function properly.
6
Thermal Shut-Down
V
O
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
MIN
25ns
RSI
100ms
100ms
POR
FIGURE 14. RSI & POR TIMING DIAGRAM
Thermal Performance
The EL7534 is in a fused-lead MSOP10 package. Compared
with regular MSOP10 package, the fused-lead package
Output Voltage Selection
Users can set the output voltage of the converter with a
resister divider, which can be chosen based on the following
formula:
provides lower thermal resistance. The θ is 100°C/W on a
JA
4-layer board and 125°C/W on 2-layer board. Maximizing the
copper area around the pins will further improve the thermal
performance.
R
R
2
V
= 0.8 × 1 + ------
O
1
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. We recommend 10µF to 22µF
multi-layer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and 1.5µH to 2.2µH
inductance for the inductor.
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to V and PGND pins
IN
The RMS current present at the input capacitor is decided by
the following formula:
as possible
• Make the following PC traces as small as possible:
V
× (V - V
)
O
IN
O
- from L pin to L
-----------------------------------------------
I
=
× I
X
INRMS
O
V
IN
- from C to PGND
O
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
This is about half of the output current I for all the V . This
O
O
input capacitor must be able to handle this current.
• Maximize the copper area around the PGND pin
The inductor peak-to-peak ripple current is given as:
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7534 Application Brief.
FN7431.5
7
August 16, 2005