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EL7535

®

Data Sheet

August 16, 2005

FN7003.2

Monolithic 350mA Step-Down Regulator

Features

• Extremely small 350mA DC/DC converter

The EL7535 is a synchronous, integrated FET 350mA step-

down regulator in a MSOP10 package. The regulator is

internally compensated, which makes it possible to use just

five tiny external components to form a complete DC/DC

converter. The regulator operates with an input voltage

range from 2.5V to 6V, which accommodates supplies of

3.3V, 5V, or a Li-Ion battery source. The output can be

• Max height 1.1mm MSOP10 package

• Possibly uses only five tiny external components with fixed

output

• Power-On-Reset output (POR)

• Internally-compensated voltage mode controller

• Up to 94% efficiency

externally set from 0.8V to V with a resistive divider.

IN

The EL7535 features PWM mode control. The operating

frequency is typically 1.4MHz. Additional features include

<1µA shut-down current, short-circuit protection, and over-

temperature protection.

• <1µA shut-down current

• Overcurrent and over-temperature protection

• Pb-Free plus anneal available (RoHS compliant)

The EL7535 is available in the 10-pin MSOP package and is

specified for operation over the full -40°C to +85°C

temperature range.

Applications

• PDA and pocket PC computers

Ordering Information

• Bar code readers

PART NUMBER

TAPE &

REEL

PKG.

• Cellular phones

(BRAND)

PACKAGE

DWG. #

• Portable test equipment

• Li-Ion battery powered devices

• Small form factor (SFP) modules

EL7535IY

10-Pin MSOP

-

MDP0043

(a)

EL7535IY-T7

(a)

10-Pin MSOP

7”

Pinout and Typical Application Diagram

EL7535IY-T13

(a)

13”

-

EL7535

(10-PIN MSOP)

TOP VIEW

EL7535IYZ

(BAACA) (Note)

10-Pin MSOP

(Pb-free)

EL7535IYZ-T7

(BAACA) (Note)

10-Pin MSOP

(Pb-free)

7”

EL7535IYZ-T13

(BAACA) (Note)

10-Pin MSOP

(Pb-free)

13”

R *

1

100kΩ

1 SGND

2 PGND

3 LX

FB 10

R *

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

2

124kΩ

VO

POR

EN

9

8

7

6

C

10µF

C

2

10µF

1.8µH

1

L

1

POR

EN

V

(1.8V@350mA)

O

4 VIN

V

(2.5V-6V)

IN

5 VDD

RSI

R

6

100kΩ

R

100kΩ

4

5

* FOR VARIABLE OUTPUT VOLTAGE: V = 0.8V * (1 + R / R )

O

2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL7535

Absolute Maximum Ratings (T = 25°C)

A

V

, V , POR to SGND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +145°C

IN DD

LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

IN

RSI, EN, V , FB to SGND. . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

IN

O

PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

Electrical Specifications

V

= V = V

IN

= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V, unless otherwise specified.

EN O

DD

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

DC CHARACTERISTICS

V

Feedback Input Voltage

790

800

810

250

6

mV

nA

V

FB

I

Feedback Input Current

Input Voltage

FB

V

, V

2.5

2

IN DD

IN,OFF

IN,ON

Minimum Voltage for Shutdown

Maximum Voltage for Startup

Supply Current

V

falling

rising

2.2

2.4

500

1

V

IN

2.2

V

I

PWM, V = V

IN DD

= 5V

400

0.1

70

µA

mΩ

A

DD

EN = 0, V = V

IN

DD

R

PMOS FET Resistance

NMOS FET Resistance

Current Limit

V

= 5V, wafer test only

100

75

DS(ON)-PMOS

DS(ON)-NMOS

LMAX

DD

V

45

I

1.5

145

130

T

Over-temperature Threshold

Over-temperature Hysteresis

EN, RSI Current

T rising

T falling

°C

µA

V

OT,OFF

OT,ON

T

I

, I

EN RSI

V

, V

EN RSI

= 0V and 3.3V

-1

0.8

86

1

V

, V

EN1 RSI1

EN, RSI Rising Threshold

EN, RSI Falling Threshold

= 3.3V

rising

2.4

DD

, V

V

EN2 RSI2

Minimum V for POR, WRT Targeted

FB

95

70

%

POR

FB

V

Value

FB

falling

%

FB

V

POR Voltage Drop

I

= 5mA

35

mV

OLPOR

SINK

AC CHARACTERISTICS

F

PWM Switching Frequency

Minimum RSI Pulse Width

Soft-start Time

1.25

80

1.4

25

1.55

50

MHz

ns

PWM

t

Guaranteed by design

RSI

650

100

µs

SS

Power On Reset Delay Time

120

ms

POR

FN7003.2

2

August 16, 2005

EL7535

Pin Descriptions

PIN NUMBER

PIN NAME

PIN FUNCTION

1

2

SGND

PGND

LX

Negative supply for the controller stage

Negative supply for the power stage

3

Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage

4

VIN

Positive supply for the power stage

Power supply for the controller stage

Resets POR timer

5

VDD

RSI

6

7

EN

Enable

8

POR

VO

Power on reset open drain output

Output voltage sense

9

10

FB

Voltage feedback input; connected to an external resistor divider between V and SGND for variable

O

output

Timing Diagram

V

O

MIN

25ns

RSI

100ms

POR

FN7003.2

3

August 16, 2005

EL7535

Block Diagram

V

DD

O

+

-

10pF

V

IN

124K

100K

CURRENT

LIMIT

FB

5M

-

+

PWM

COMPEN-

SATION

+

-

PWM

COMPARATOR

P-DRIVER

LX

1.8µ

CONTROL

LOGIC

RAMP

GENERATOR

CLOCK

1.4MHz

1.8V

350mA

EN

SOFT-

START

10µF

N-DRIVER

UNDER-

VOLTAGE

LOCKOUT

+

–

PGND

POR

BANDGAP

REFERENCE

100K

PG

5V

TEMPERATURE

SENSE

SGND

RSI

POR

FN7003.2

4

August 16, 2005

EL7535

Typical Performance Curves

100

95

90

85

80

75

70

65

60

V

=5V

IN

V

=3.3V

IN

V

=2.5V

V

=3.3V

O

95

90

85

80

75

70

65

60

V

=2.5V

V

=1.8V

V =1.2V

O

V

=1.8V

O

V

=1V

O

V

=1.2V

O

300

0

100

200

(mA)

400

0

100

200

(mA)

400

I

O

FIGURE 1. EFFICIENCY

FIGURE 2. EFFICIENCY

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

1

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.087W

607mW

0.8

0.6

0.4

0.2

0

25

50

75 85 100

125

150

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Waveforms

All waveforms are taken at V =3.3V, V =1.8V, I =350mA with component values shown on page 1, unless otherwise noted

IN

O

V

IN

(2V/DIV)

V

IN

(1V/DIV)

V

O

I

IN

(0.2A/DIV)

(2V/DIV)

POR

(2V/DIV)

V

O

(1V/DIV)

50ms/DIV

0.5ms/DIV

FIGURE 6. START-UP 2

FIGURE 5. START-UP 1

FN7003.2

August 16, 2005

5

EL7535

Waveforms (Continued)

All waveforms are taken at V =3.3V, V =1.8V, I =350mA with component values shown on page 1, unless otherwise noted

IN

O

V

IN

(2V/DIV)

V

O

(2V/DIV)

350mA

100mA

I

O

RSI

(2V/DIV)

∆V

O

20mV/DIV

POR

(2V/DIV)

0.2ms/DIV

50ms/DIV

FIGURE 8. TRANSIENT RESPONSE

FIGURE 7. POR FUNCTION

∆V

100mV/DIV

0.5A/DIV

IN

i

L

V

2V/DIV

LX

∆V

10mV/DIV

O

1µs/DIV

FIGURE 9. STEADY-STATE

current decreases linearly, and energy is transferred from

the inductor to the output. Hence, the average current

through the inductor is the output current. Since the inductor

and the output capacitor act as a low pass filter, the duty

Applications Information

Product Description

The EL7535 is a synchronous, integrated FET 350mA step-

down regulator which operates from an input of 2.5V to 6V.

The output voltage is user-adjustable with a pair of external

resistors.

cycle ratio is approximately equal to V divided by V

.

O

IN

The output LC filter has a second order effect. To maintain

the stability of the converter, the overall controller must be

compensated. This is done with the fixed internally

compensated error amplifier and the PWM compensator.

Because the compensations are fixed, the values of input

and output capacitors are 10µF to 22µF ceramic. The

inductor is nominally 1.8µH, though 1.5µA to 2.2µH can be

used.

The internally-compensated controller makes it possible to

use only two ceramic capacitors and one inductor to form a

complete, very small footprint 350mA DC/DC converter.

PWM Operation

In the PWM mode, the P channel MOSFET and N channel

MOSFET always operate complementary. When the

PMOSFET is on and the NMOSFET off, the inductor current

increases linearly. The input energy is transferred to the

output and also stored in the inductor. When the P channel

MOSFET is off and the N channel MOSFET on, the inductor

Start-Up and Shut-Down

When the EN pin is tied to V , and V reaches

IN

approximately 2.4V, the regulator begins to switch. The

FN7003.2

August 16, 2005

6

EL7535

output voltage is gradually increased to ensure proper soft-

start operation.

The inductor must be able to handle I for the RMS load

O

current, and to assure that the inductor is reliable, it must

handle the 1.5A surge current that can occur during a

current limit condition.

When the EN pin is connected to a logic low, the EL7535 is

in the shut-down mode. All the control circuitry and both

MOSFETs are off, and V

falls to zero. In this mode, the

Current Limit and Short-Circuit Protection

OUT

total input current is less than 1µA.

The current limit is set at about 1.5A for the PMOS. When a

short-circuit occurs in the load, the preset current limit

restricts the amount of current available to the output, which

causes the output voltage to drop below the preset voltage.

In the meantime, the excessive current heats up the

regulator until it reaches the thermal shut-down point.

When the EN reaches logic HI, the regulator repeats the

start-up procedure, including the soft-start function.

RSI/POR Function

When powering up, the open-collector Power-On-Reset

output holds low for about 100ms after V reaches the

O

Thermal Shut-Down

preset voltage. When the active-HI reset signal RSI is

issued, POR goes to low immediately and holds for the

same period of time after RSI comes back to LOW. The

output voltage is unaffected. (Please refer to the timing

diagram). When the function is not used, connect RSI to

Once the junction reaches about 145°C, the regulator shuts

down. Both the P channel and the N channel MOSFETs turn

off. The output voltage will drop to zero. With the output

MOSFETs turned off, the regulator will soon cool down.

Once the junction temperature drops to about 130°C, the

regulator will restart again in the same manner as EN pin

connects to logic HI.

ground and leave open the pull-up resister R at POR pin.

4

The POR output also serves as a 100ms delayed Power

Good signal when the pull-up resister R is installed. The

4

Thermal Performance

RSI pin needs to be directly (or indirectly through a resister

R ) connected to Ground for this to function properly.

The EL7535 is in a fused-lead MSOP10 package. Compared

with regular MSOP10 package, the fused-lead package

6

Output Voltage Selection

Users can set the output voltage of the converter with a

resister divider, which can be chosen based on the following

formula:

provides lower thermal resistance. The θ is 100°C/W on a

JA

4-layer board and 125°C/W on 2-layer board. Maximizing the

copper area around the pins will further improve the thermal

performance.

R









2

V

= 0.8 × 1 + ------



Layout Considerations

The layout is very important for the converter to function

properly. The following PC layout guidelines should be

followed:

O



1

Component Selection

Because of the fixed internal compensation, the component

choice is relatively narrow. For a regulator with fixed output

voltage, only two capacitors and one inductor are required.

We recommend 10µF to 22µF multi-layer ceramic capacitors

with X5R or X7R rating for both the input and output

• Separate the Power Ground ( ) and Signal Ground ( );

connect them only at one point right at the pins

• Place the input capacitor as close to V and PGND pins

IN

as possible

capacitors, and 1.5µH to 2.2µH inductance for the inductor.

• Make the following PC traces as small as possible:

The RMS current present at the input capacitor is decided by

the following formula:

- from L pin to L

X

- from C to PGND

O

V

× (V - V

)

IN

O

• If used, connect the trace from the FB pin to R1 and R2 as

close as possible

-------------------------------------------------

I

=

× I

INRMS

O

V

IN

• Maximize the copper area around the PGND pin

This is about half of the output current I for all the V . This

O

input capacitor must be able to handle this current.

• Place several via holes under the chip to additional ground

plane to improve heat dissipation

The inductor peak-to-peak ripple current is given as:

The demo board is a good example of layout based on this

outline. Please refer to the EL7535 Application Brief.

(V - V ) × V

O

IN

O

∆I = --------------------------------------------

IL

L × V × f

IN

S

• L is the inductance

• f the switching frequency (nominally 1.4MHz)

S

FN7003.2

7

August 16, 2005

EL7535

Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil

website at <http://www.intersil.com/design/packages/index.asp>

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7003.2

8

August 16, 2005

型号:	EL7535IY-T7
Brand Name：	Intersil
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTERSIL CORP
零件包装代码：	MSOP
包装说明：	TSSOP, TSSOP10,.19,20
针数：	10
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.2
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	6 V
最小输入电压：	2.5 V
标称输入电压：	3.3 V
JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e0
长度：	3 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	10
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	0.5 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	1550 kHz
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
Base Number Matches：	1

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