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产品型号EPM9320的Datasheet PDF文件预览

MAX 9000  
Programmable Logic  
Device Family  
Includes  
MAX 9000A  
®
June 2003, ver. 6.5  
Data Sheet  
High-performance CMOS EEPROM-based programmable logic  
devices (PLDs) built on third-generation Multiple Array MatriX  
(MAX®) architecture  
Features...  
5.0-V in-system programmability (ISP) through built-in IEEE Std.  
1149.1 Joint Test Action Group (JTAG) interface  
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE  
Std. 1149.1-1990  
High-density erasable programmable logic device (EPLD) family  
ranging from 6,000 to 12,000 usable gates (see Table 1)  
10-ns pin-to-pin logic delays with counter frequencies of up to  
144 MHz  
Fully compliant with the peripheral component interconnect Special  
Interest Groups (PCI SIG) PCI Local Bus Specification, Revision 2.2  
Dual-output macrocell for independent use of combinatorial and  
registered logic  
FastTrack® Interconnect for fast, predictable interconnect delays  
Input/ output registers with clear and clock enable on all I/ O pins  
Programmable output slew-rate control to reduce switching noise  
MultiVoltI/ O interface operation, allowing devices to interface with  
3.3-V and 5.0-V devices  
Configurable expander product-term distribution allowing up to 32  
product terms per macrocell  
Programmable power-saving mode for more than 50% power  
reduction in each macrocell  
Table 1. MAX 9000 Device Features  
Feature EPM9320  
EPM9400  
EPM9480  
EPM9560  
EPM9320A  
EPM9560A  
Usable gates  
6,000  
484  
320  
20  
8,000  
580  
400  
25  
10,000  
676  
480  
30  
12,000  
772  
560  
35  
Flipflops  
Macrocells  
Logic array blocks (LABs)  
Maximum user I/O pins  
tPD1 (ns)  
168  
10  
159  
15  
175  
10  
216  
10  
tFSU (ns)  
3.0  
5
3.0  
3.0  
t
FCO (ns)  
4.5  
7
4.8  
4.8  
fCNT (MHz)  
144  
118  
144  
144  
Altera Corporation  
1
DS-M9000-6.5  
MAX 9000 Programmable Logic Device Family Data Sheet  
Programmable macrocell flipflops with individual clear, preset,  
clock, and clock enable controls  
...and More  
Features  
Programmable security bit for protection of proprietary designs  
Software design support and automatic place-and-route provided by  
Alteras MAX+PLUS® II development system on Windows-based  
PCs as well as Sun SPARCstation, HP 9000 Series 700/ 800, and IBM  
RISC System/ 6000 workstations  
Additional design entry and simulation support provided by EDIF  
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),  
Verilog HDL, VHDL, and other interfaces to popular EDA tools from  
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,  
OrCAD, Synopsys, Synplicity, and VeriBest  
Programming support with Alteras Master Programming Unit  
(MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel  
port download cable, and ByteBlasterMVTM parallel port download  
cable, as well as programming hardware from third-party  
manufacturers  
Offered in a variety of package options with 84 to 356 pins (see  
Table 2)  
Table 2. MAX 9000 Package Options & I/O Counts  
Note (1)  
Device  
84-Pin  
PLCC  
208-Pin 240-Pin 280-Pin 304-Pin 356-Pin  
RQFP  
RQFP  
PGA  
RQFP  
BGA  
EPM9320  
EPM9320A  
EPM9400  
EPM9480  
EPM9560  
EPM9560A  
60 (2)  
132  
132  
139  
146  
153  
153  
168  
168  
168  
60 (2)  
59 (2)  
159  
175  
191  
191  
216  
216  
216  
216  
Notes:  
(1) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power  
quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA)  
packages.  
(2) Perform a complete thermal analysis before committing a design to this device  
package. See Application Note 74 (Evaluating Power for Altera Devices).  
2
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
The MAX 9000 family of in-system-programmable, high-density, high-  
performance EPLDs is based on Alteras third-generation MAX  
architecture. Fabricated on an advanced CMOS technology, the EEPROM-  
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin  
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed  
grade of the MAX 9000 family is compliant with the PCI Local Bus  
Specification, Revision 2.2. Table 3 shows the speed grades available for  
MAX 9000 devices.  
General  
Description  
Table 3. MAX 9000 Speed Grade Availability  
Device  
Speed Grade  
-10  
-15  
-20  
EPM9320  
EPM9320A  
EPM9400  
EPM9480  
EPM9560  
EPM9560A  
v
v
v
v
v
v
v
v
v
v
Table 4 shows the performance of MAX 9000 devices for typical functions.  
Table 4. MAX 9000 Performance  
Note (1)  
Application  
Macrocells Used  
Speed Grade  
-15  
Units  
-10  
-20  
16-bit loadable counter  
16-bit up/down counter  
16-bit prescaled counter  
16-bit address decode  
16-to-1 multiplexer  
16  
16  
16  
1
144  
144  
118  
118  
100  
100  
MHz  
MHz  
MHz  
ns  
144  
118  
100  
5.6 (10)  
7.7 (12.1)  
7.9 (15)  
10.9 (18)  
10 (20)  
16 (26)  
1
ns  
Note:  
(1) Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row  
input pin to row I/ O pin.  
The MAX 9000 architecture supports high-density integration of system-  
level logic functions. It easily integrates multiple programmable logic  
devices ranging from PALs, GALs, and 22V10s to field-programmable  
gate array (FPGA) devices and EPLDs.  
Altera Corporation  
3
MAX 9000 Programmable Logic Device Family Data Sheet  
All MAX 9000 device packages provide four dedicated inputs for global  
control signals with large fan-outs. Each I/ O pin has an associated I/ O  
cell register with a clock enable control on the periphery of the device. As  
outputs, these registers provide fast clock-to-output times; as inputs, they  
offer quick setup times.  
MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This  
feature allows the devices to be programmed and reprogrammed on the  
printed circuit board (PCB) for quick and efficient iterations during design  
development and debug cycles. MAX 9000 devices are guaranteed for 100  
program and erase cycles.  
MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into  
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell  
has a programmable-AND/ fixed-ORarray and a configurable register with  
independently programmable clock, clock enable, clear, and preset  
functions. For increased flexibility, each macrocell offers a dual-output  
structure that allows the register and the product terms to be used  
independently. This feature allows register-rich and combinatorial-  
intensive designs to be implemented efficiently. The dual-output  
structure of the MAX 9000 macrocell also improves logic utilization, thus  
increasing the effective capacity of the devices. To build complex logic  
functions, each macrocell can be supplemented with both shareable  
expander product terms and high-speed parallel expander product terms  
to provide up to 32 product terms per macrocell.  
The MAX 9000 family provides programmable speed/ power  
optimization. Speed-critical portions of a design can run at high  
speed/ full power, while the remaining portions run at reduced  
speed/ low power. This speed/ power optimization feature enables the  
user to configure one or more macrocells to operate at 50% or less power  
while adding only a nominal timing delay. MAX 9000 devices also  
provide an option that reduces the slew rate of the output buffers,  
minimizing noise transients when non-speed-critical signals are  
switching. MAX 9000 devices offer the MultiVolt feature, which allows  
output drivers to be set for either 3.3-V or 5.0-V operation in mixed-  
voltage systems.  
4
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
The MAX 9000 family is supported by Alteras MAX+PLUS II  
development system, a single, integrated software package that offers  
schematic, text—including VHDL, Verilog HDL, and the Altera  
Hardware Description Language (AHDL)—and waveform design entry,  
compilation and logic synthesis, simulation and timing analysis, and  
device programming. The MAX+PLUS II software provides EDIF 2 0 0  
and 3 0 0, LPM, and other interfaces for additional design entry and  
simulation support from other industry-standard PC- and UNIX-  
workstation-based EDA tools. The MAX+PLUS II software runs on  
Windows-based PCs as well as Sun SPARCstation, HP 9000 Series  
700/ 800, and IBM RISC System/ 6000 workstations.  
For more information on development tools, see the MAX+PLUS II  
Programmable Logic Development System & Software Data Sheet.  
f
MAX 9000 devices use a third-generation MAX architecture that yields  
both high performance and a high degree of utilization for most  
applications. The MAX 9000 architecture includes the following elements:  
Functional  
Description  
Logic array blocks  
Macrocells  
Expander product terms (shareable and parallel)  
FastTrack Interconnect  
Dedicated inputs  
I/ O cells  
Figure 1 shows a block diagram of the MAX 9000 architecture.  
Altera Corporation  
5
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 1. MAX 9000 Device Block Diagram  
I/O Cell  
(IOC)  
IOC  
IOC  
IOC  
IOC  
IOC  
IOC  
IOC  
IOC  
FastTrack  
Interconnect  
Logic Array  
Block (LAB)  
IOC  
IOC  
IOC  
IOC  
Macrocell  
LAB Local Array  
IOC  
IOC  
IOC  
IOC  
Logic Array Blocks  
The MAX 9000 architecture is based on linking high-performance, flexible  
logic array modules called logic array blocks (LABs). LABs consist of  
16-macrocell arrays that are fed by the LAB local array, as shown in  
Figure 2 on page 7. Multiple LABs are linked together via the FastTrack  
Interconnect, a series of fast, continuous channels that run the entire  
length and width of the device. The I/ O pins are supported by I/ O cells  
(IOCs) located at the end of each row (horizontal) and column (vertical)  
path of the FastTrack Interconnect.  
Each LAB is fed by 33 inputs from the row interconnect and 16 feedback  
signals from the macrocells within the LAB. All of these signals are  
available within the LAB in their true and inverted form. In addition,  
16 shared expander product terms (“expanders”) are available in their  
inverted form, for a total of 114 signals that feed each product term in the  
LAB. Each LAB is also fed by two low-skew global clocks and one global  
clear that can be used for register control signals in all 16 macrocells.  
6
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
LABs drive the row and column interconnect directly. Each macrocell can  
drive out of the LAB onto one or both routing resources. Once on the row  
or column interconnect, signals can traverse to other LABs or to the IOCs.  
Figure 2. MAX 9000 Logic Array Block  
Global Control Select  
DIN1  
GCLK1  
GCLK2  
GCLR  
GOE  
To Peripheral Bus and  
Other LABs in the Device  
DIN2  
DIN3  
To Peripheral Bus  
DIN4  
Row FastTrack  
Interconnect  
33  
16  
16  
See Figure 7  
for details.  
LAB Local Array  
(114 Channels)  
Macrocell 1  
Macrocell 2  
Macrocell 3  
Macrocell 4  
Macrocell 5  
Macrocell 6  
Macrocell 7  
Macrocell 8  
Macrocell 9  
Macrocell 10  
Macrocell 11  
Macrocell 12  
Macrocell 13  
Macrocell 14  
Macrocell 15  
Macrocell 16  
16  
48  
48  
16  
Column FastTrack  
Interconnect  
Shared Expander  
Signals  
16  
Local Feedback  
16  
Altera Corporation  
7
MAX 9000 Programmable Logic Device Family Data Sheet  
Macrocells  
The MAX 9000 macrocell consists of three functional blocks: the product  
terms, the product-term select matrix, and the programmable register.  
The macrocell can be individually configured for both sequential and  
combinatorial logic operation. See Figure 3.  
Figure 3. MAX 9000 Macrocell & Local Array  
LAB Local  
Array  
Global Global  
Clear Clocks  
33 Row  
FastTrack  
Interconnect  
Inputs  
Parallel  
2
Expanders  
(from Other  
Macrocells)  
Macrocell  
Input Select  
Programmable  
Register  
Register  
Bypass  
To Row or  
Column  
FastTrack  
Interconnect  
PRN  
D/T  
Q
Clock/  
Enable  
Select  
Product-  
Term  
Select  
Matrix  
ENA  
CLRN  
VCC  
Clear  
Select  
Local Array  
Feedback  
16 Local  
Feedbacks  
16 Shareable  
Expander Product  
Combinatorial logic is implemented in the local array, which provides five  
product terms per macrocell. The product-term select matrix allocates  
these product terms for use as either primary logic inputs (to the ORand  
XORgates) to implement combinatorial functions, or as secondary inputs  
to the macrocells register clear, preset, clock, and clock enable control  
functions. Two kinds of expander product terms (“expanders”) are  
available to supplement macrocell logic resources:  
Shareable expanders, which are inverted product terms that are fed  
back into the logic array  
Parallel expanders, which are product terms borrowed from adjacent  
macrocells  
The MAX+PLUS II software automatically optimizes product-term  
allocation according to the logic requirements of the design.  
8
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
For registered functions, each macrocell register can be individually  
programmed for D, T, JK, or SR operation with programmable clock  
control. The flipflop can also be bypassed for combinatorial operation.  
During design entry, the user specifies the desired register type; the  
MAX+PLUS II software then selects the most efficient register operation  
for each registered function to optimize resource utilization.  
Each programmable register can be clocked in three different modes:  
By either global clock signal. This mode achieves the fastest clock-to-  
output performance.  
By a global clock signal and enabled by an active-high clock enable.  
This mode provides an enable on each flipflop while still achieving  
the fast clock-to-output performance of the global clock.  
By an array clock implemented with a product term. In this mode, the  
flipflop can be clocked by signals from buried macrocells or I/ O pins.  
Two global clock signals are available. As shown in Figure 2, these global  
clock signals can be the true or the complement of either of the global clock  
pins (DIN1and DIN2).  
Each register also supports asynchronous preset and clear functions. As  
shown in Figure 3, the product-term select matrix allocates product terms  
to control these operations. Although the product-term-driven preset and  
clear inputs to registers are active high, active-low control can be obtained  
by inverting the signal within the logic array. In addition, each register  
clear function can be individually driven by the dedicated global clear pin  
(DIN3). The global clear can be programmed for active-high or active-low  
operation.  
All MAX 9000 macrocells offer a dual-output structure that provides  
independent register and combinatorial logic output within the same  
macrocell. This function is implemented by a process called register  
packing. When register packing is used, the product-term select matrix  
allocates one product term to the D input of the register, while the  
remaining product terms can be used to implement unrelated  
combinatorial logic. Both the registered and the combinatorial output of  
the macrocell can feed either the FastTrack Interconnect or the LAB local  
array.  
Altera Corporation  
9
MAX 9000 Programmable Logic Device Family Data Sheet  
Expander Product Terms  
Although most logic functions can be implemented with the five product  
terms available in each macrocell, some logic functions are more complex  
and require additional product terms. Although another macrocell can  
supply the required logic resources, the MAX 9000 architecture also offers  
both shareable and parallel expander product terms that provide  
additional product terms directly to any macrocell in the same LAB. These  
expanders help ensure that logic is synthesized with the fewest possible  
logic resources to obtain the fastest possible speed.  
Shareable Expanders  
Each LAB has 16 shareable expanders that can be viewed as a pool of  
uncommitted single product terms (one from each macrocell) with  
inverted outputs that feed back into the LAB local array. Each shareable  
expander can be used and shared by any or all macrocells in the LAB to  
build complex logic functions. A small delay (tLOCAL + tSEXP) is incurred  
when shareable expanders are used. Figure 4 shows how shareable  
expanders can feed multiple macrocells.  
Figure 4. MAX 9000 Shareable Expanders  
Shareable expanders can be shared by any or all macrocells in the LAB.  
LAB Local Array  
33 Row  
FastTrack  
Interconnect  
Signals  
Macrocell  
Product-Term  
Logic  
Product-Term Select Matrix  
Macrocell  
Product-Term  
Logic  
16 Local  
Feedbacks  
16 Shared  
Expanders  
10  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Parallel Expanders  
Parallel expanders are unused product terms that can be allocated to a  
neighboring macrocell to implement fast, complex logic functions.  
Parallel expanders allow up to 20 product terms to directly feed the  
macrocell ORlogic, with five product terms provided by the macrocell and  
15 parallel expanders provided by neighboring macrocells in the LAB.  
Figure 5 shows how parallel expanders can feed the neighboring  
macrocell.  
Figure 5. MAX 9000 Parallel Expanders  
Unused product terms in a macrocell can be allocated to a neighboring macrocell.  
33 Row  
FastTrack  
Interconnect  
Signals  
LAB Local  
Array  
From  
Previous  
Macrocell  
Preset  
Product-  
Term  
Select  
Matrix  
Macrocell  
Product-  
Term Logic  
Clock  
Clear  
Preset  
Product-  
Term  
Select  
Matrix  
Macrocell  
Product-  
Term Logic  
Clock  
Clear  
To Next  
Macrocell  
16 Local  
16 Shared  
Feedbacks Expanders  
Altera Corporation  
11  
MAX 9000 Programmable Logic Device Family Data Sheet  
The MAX+PLUS II Compiler automatically allocates as many as three sets  
of up to five parallel expanders to macrocells that require additional  
product terms. Each set of expanders incurs a small, incremental timing  
delay (tPEXP). For example, if a macrocell requires 14 product terms, the  
Compiler uses the five dedicated product terms within the macrocell and  
allocates two sets of parallel expanders; the first set includes five product  
terms and the second set includes four product terms, increasing the total  
delay by 2 × tPEXP  
.
Two groups of eight macrocells within each LAB (e.g., macrocells 1  
through 8 and 9 through 16) form two chains to lend or borrow parallel  
expanders. A macrocell borrows parallel expanders from lower-  
numbered macrocells. For example, macrocell 8 can borrow parallel  
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells  
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can  
only lend parallel expanders and the highest-numbered macrocell can  
only borrow them.  
FastTrack Interconnect  
In the MAX 9000 architecture, connections between macrocells and device  
I/ O pins are provided by the FastTrack Interconnect, a series of  
continuous horizontal and vertical routing channels that traverse the  
entire device. This device-wide routing structure provides predictable  
performance even in complex designs. In contrast, the segmented routing  
in FPGAs requires switch matrices to connect a variable number of  
routing paths, increasing the delays between logic resources and reducing  
performance. Figure 6 shows the interconnection of four adjacent LABs  
with row and column interconnects.  
12  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 6. MAX 9000 Device Interconnect Resources  
Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.  
See Figure 9  
for details.  
IOC1  
IOC1  
IOC10  
IOC10  
Column  
FastTrack  
Interconnect  
See Figure 8  
for details.  
Row FastTrack  
Interconnect  
IOC1  
IOC8  
IOC1  
IOC8  
See Figure 7  
for details.  
LAB  
A1  
LAB  
A2  
IOC1  
IOC1  
IOC8  
IOC8  
LAB  
B1  
LAB  
B2  
IOC1  
IOC1  
IOC10  
IOC10  
The LABs within MAX 9000 devices are arranged into a matrix of columns  
and rows. Table 5 shows the number of columns and rows in each  
MAX 9000 device.  
Table 5. MAX 9000 Rows & Columns  
Devices  
Rows  
Columns  
EPM9320, EPM9320A  
EPM9400  
4
5
6
7
5
5
5
5
EPM9480  
EPM9560, EPM9560A  
Altera Corporation  
13  
MAX 9000 Programmable Logic Device Family Data Sheet  
Each row of LABs has a dedicated row interconnect that routes signals  
both into and out of the LABs in the row. The row interconnect can then  
drive I/ O pins or feed other LABs in the device. Each row interconnect has  
a total of 96 channels. Figure 7 shows how a macrocell drives the row and  
column interconnect.  
Figure 7. MAX 9000 LAB Connections to Row & Column Interconnect  
48 Column  
Channels  
96 Row Channels  
Each macrocell drives  
one row channel.  
LAB  
Macrocell 1  
Dual-output  
macrocell feeds  
both FastTrack  
Interconnect and  
LAB local array.  
Macrocell 2  
To LAB  
Local Array  
Each macrocell drives one  
of three column channels.  
Additional multiplexer provides  
column-to-row path if  
macrocell drives row channel.  
Each macrocell in the LAB can drive one of three separate column  
interconnect channels. The column channels run vertically across the  
entire device, and are shared by the macrocells in the same column. The  
MAX+PLUS II Compiler optimizes connections to a column channel  
automatically.  
14  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
A row interconnect channel can be fed by the output of the macrocell  
through a 4-to-1 multiplexer that the macrocell shares with three column  
channels. If the multiplexer is used for a macrocell-to-row connection, the  
three column signals can access another row channel via an additional  
3-to-1 multiplexer. Within any LAB, the multiplexers provide all  
48 column channels with access to 32 row channels.  
Row-to-I/O Cell Connections  
Figure 8 illustrates the connections between row interconnect channels  
and IOCs. An input signal from an IOC can drive two separate row  
channels. When an IOC is used as an output, the signal is driven by a  
10-to-1 multiplexer that selects the row channels. Each end of the row  
channel feeds up to eight IOCs on the periphery of the device.  
Figure 8. MAX 9000 Row-to-IOC Connections  
IOC1  
10  
Row FastTrack  
Interconnect  
96  
96  
96  
IOC8  
10  
Each IOC is driven by  
a 10-to-1 multiplexer.  
Each IOC can drive up to  
two row channels.  
Column-to-I/O Cell Connections  
Each end of a column channel has up to 10 IOCs (see Figure 9). An input  
signal from an IOC can drive two separate column channels. When an IOC  
is used as an output, the signal is driven by a 17-to-1 multiplexer that  
selects the column channels.  
Altera Corporation  
15  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 9. MAX 9000 Column-to-IOC Connections  
IOC10  
IOC1  
Each IOC is driven by  
a 17-to-1 multiplexer.  
Each IOC can drive up  
to two column  
channels.  
17  
17  
48  
48  
48  
Column FastTrack  
Interconnect  
Dedicated Inputs  
In addition to the general-purpose I/ O pins, MAX 9000 devices have four  
dedicated input pins. These dedicated inputs provide low-skew, device-  
wide signal distribution to the LABs and IOCs in the device, and are  
typically used for global clock, clear, and output enable control signals.  
The global control signals can feed the macrocell or IOC clock and clear  
inputs, as well as the IOC output enable. The dedicated inputs can also be  
used as general-purpose data inputs because they can feed the row  
FastTrack Interconnect (see Figure 2 on page 7).  
I/O Cells  
Figure 10 shows the IOC block diagram. Signals enter the MAX 9000  
device from either the I/ O pins that provide general-purpose input  
capability or from the four dedicated inputs. The IOCs are located at the  
ends of the row and column interconnect channels.  
16  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 10. MAX 9000 IOC  
Peripheral Control  
Bus [12..0]  
VCC  
OE [7..0]  
8
To Row or  
Column FastTrack  
Interconnect  
13  
From Row or  
Column FastTrack  
Interconnect  
D
Q
CLK [3..0]  
4
Slew-Rate  
Control  
ENA  
CLRN  
VCC  
ENA [5..0]  
6
VCC  
CLR [1..0]  
2
I/ O pins can be used as input, output, or bidirectional pins. Each IOC has  
an IOC register with a clock enable input. This register can be used either  
as an input register for external data that requires fast setup times, or as an  
output register for data that requires fast clock-to-output performance.  
The IOC register clock enable allows the global clock to be used for fast  
clock-to-output performance, while maintaining the flexibility required  
for selective clocking.  
The clock, clock enable, clear, and output enable controls for the IOCs are  
provided by a network of I/ O control signals. These signals can be  
supplied by either the dedicated input pins or internal logic. The IOC  
control-signal paths are designed to minimize the skew across the device.  
All control-signal sources are buffered onto high-speed drivers that drive  
the signals around the periphery of the device. This “peripheral bus” can  
be configured to provide up to eight output enable signals, up to four  
clock signals, up to six clock enable signals, and up to two clear signals.  
Table 6 on page 18 shows the sources that drive the peripheral bus and  
how the IOC control signals share the peripheral bus.  
Altera Corporation  
17  
MAX 9000 Programmable Logic Device Family Data Sheet  
The output buffer in each IOC has an adjustable output slew rate that can  
be configured for low-noise or high-speed performance. A slower slew  
rate reduces board-level noise and adds a nominal timing delay to the  
output buffer delay (tOD) parameter. The fast slew rate should be used for  
speed-critical outputs in systems that are adequately protected against  
noise. Designers can specify the slew rate on a pin-by-pin basis during  
design entry or assign a default slew rate to all pins on a global basis. The  
slew rate control affects both rising and falling edges of the output signals.  
Table 6. Peripheral Bus Sources  
Peripheral Control  
Signal  
Source  
EPM9400 EPM9480  
EPM9320  
EPM9560  
EPM9320A  
EPM9560A  
OE0/ENA0  
OE1/ENA1  
OE2/ENA2  
OE3/ENA3  
OE4/ENA4  
OE5  
Row C  
Row B  
Row A  
Row B  
Row A  
Row D  
Row C  
Row B/GOE  
Row E  
Row F  
Row G  
Row F  
Row E  
Row F  
Row E  
Row E  
Row E  
Row B  
Row A  
Row D  
Row C  
Row B/GOE  
Row B  
Row B  
Row A  
Row A  
Row D  
Row C  
Row B/GOE  
Row D  
Row C  
Row B/GOE  
OE6  
OE7/CLR1  
CLR0/ENA5  
CLK0  
Row A/GCLR Row A/GCLR Row A/GCLR Row A/GCLR  
GCLK1  
GCLK2  
Row D  
Row C  
GCLK1  
GCLK2  
Row D  
Row C  
GCLK1  
GCLK2  
Row D  
Row C  
GCLK1  
GCLK2  
Row D  
Row C  
CLK1  
CLK2  
CLK3  
The MAX 9000 device architecture supports the MultiVolt I/ O interface  
feature, which allows MAX 9000 devices to interface with systems of  
differing supply voltages. The 5.0-V devices in all packages can be set for  
3.3-V or 5.0-V I/ O pin operation. These devices have one set of VCC pins  
for internal operation and input buffers (VCCINT), and another set for I/ O  
output drivers (VCCIO).  
Output  
Configuration  
The VCCINTpins must always be connected to a 5.0-V power supply.  
With a 5.0-V VCCINT level, input voltages are at TTL levels and are  
therefore compatible with 3.3-V and 5.0-V inputs.  
18  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
The VCCIOpins can be connected to either a 3.3-V or 5.0-V power supply,  
depending on the output requirements. When the VCCIOpins are  
connected to a 5.0-V power supply, the output levels are compatible with  
5.0-V systems. When the VCCIOpins are connected to a 3.3-V power  
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V  
or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V  
incur a nominally greater timing delay of tOD2 instead of tOD1  
.
MAX 9000 devices can be programmed in-system through a 4-pin JTAG  
interface. ISP offers quick and efficient iterations during design  
development and debug cycles. The MAX 9000 architecture internally  
generates the 12.0-V programming voltage required to program EEPROM  
cells, eliminating the need for an external 12.0-V power supply to program  
the devices on the board. During ISP, the I/ O pins are tri-stated to  
eliminate board conflicts.  
In-System  
Programma-  
bility (ISP)  
ISP simplifies the manufacturing flow by allowing the devices to be  
mounted on a printed circuit board with standard pick-and-place  
equipment before they are programmed. MAX 9000 devices can be  
programmed by downloading the information via in-circuit testers,  
embedded processors, or the Altera BitBlaster, ByteBlaster, or  
ByteBlasterMV download cable. (The ByteBlaster cable is obsolete and has  
been replaced by the ByteBlasterMV cable, which can interface with 2.5-V,  
3.3-V, and 5.0-V devices.) Programming the devices after they are placed  
on the board eliminates lead damage on high pin-count packages (e.g.,  
QFP packages) due to device handling. MAX 9000 devices can also be  
reprogrammed in the field (i.e., product upgrades can be performed in the  
field via software or modem).  
In-system programming can be accomplished with either an adaptive or  
constant algorithm. An adaptive algorithm reads information from the  
unit and adapts subsequent programming steps to achieve the fastest  
possible programming time for that unit. Because some in-circuit testers  
platforms have difficulties supporting an adaptive algorithm, Altera  
offers devices tested with a constant algorithm. Devices tested to the  
constant algorithm have an “F” suffix in the ordering code.  
Altera Corporation  
19  
MAX 9000 Programmable Logic Device Family Data Sheet  
Programming Sequence  
During in-system programming, instructions, addresses, and data are  
shifted into the MAX 9000 device through the TDIinput pin. Data is  
shifted out through the TDOoutput pin and compared against the  
expected data.  
Programming a pattern into the device requires the following six ISP  
stages. A stand-alone verification of a programmed pattern involves only  
stages 1, 2, 5, and 6.  
1. Enter ISP. The enter ISP stage ensures that the I/ O pins transition  
smoothly from user mode to ISP mode. The enter ISP stage requires  
1 ms.  
2. Check ID. Before any program or verify process, the silicon ID is  
checked. The time required to read this silicon ID is relatively small  
compared to the overall programming time.  
3. Bulk Erase. Erasing the device in-system involves shifting in the  
instructions to erase the device and applying one erase pulse of  
100 ms.  
4. Program. Programming the device in-system involves shifting in the  
address and data and then applying the programming pulse to  
program the EEPROM cells. This process is repeated for each  
EEPROM address.  
5. Verify. Verifying an Altera device in-system involves shifting in  
addresses, applying the read pulse to verify the EEPROM cells, and  
shifting out the data for comparison. This process is repeated for  
each EEPROM address.  
6. Exit ISP. An exit ISP stage ensures that the I/ O pins transition  
smoothly from ISP mode to user mode. The exit ISP stage requires  
1 ms.  
Programming Times  
The time required to implement each of the six programming stages can  
be broken into the following two elements:  
A pulse time to erase, program, or read the EEPROM cells.  
A shifting time based on the test clock (TCK) frequency and the  
number of TCKcycles to shift instructions, address, and data into the  
device.  
20  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
By combining the pulse and shift times for each of the programming  
stages, the program or verify time can be derived as a function of the TCK  
frequency, the number of devices, and specific target device(s). Because  
different ISP-capable devices have a different number of EEPROM cells,  
both the total fixed and total variable times are unique for a single device.  
Programming a Single MAX 9000 Device  
The time required to program a single MAX 9000 device in-system can be  
calculated from the following formula:  
Cycle  
PTCK  
t
= t  
+ -------------------------------  
PROG  
PP ULSE  
f
TCK  
where: tPROG  
= Programming time  
tPPULSE  
= Sum of the fixed times to erase, program, and  
verify the EEPROM cells  
CyclePTCK = Number of TCKcycles to program a device  
fTCK = TCKfrequency  
The ISP times for a stand-alone verification of a single MAX 9000 device  
can be calculated from the following formula:  
Cycle  
VTCK  
t
= t  
+ --------------------------------  
VER  
VPULSE  
f
TCK  
where: tVER  
tVPULSE  
CycleVTCK = Number of TCKcycles to verify a device  
= Verify time  
= Sum of the fixed times to verify the EEPROM cells  
Altera Corporation  
21  
MAX 9000 Programmable Logic Device Family Data Sheet  
The programming times described in Tables 7 through 9 are associated  
with the worst-case method using the ISP algorithm.  
Table 7. MAX 9000 tPULSE & CycleTCK Values  
Device  
Programming  
Stand-Alone Verification  
tVPULSE (s) CycleVTCK  
tPPULSE (s)  
CyclePTCK  
EPM9320  
11.79  
2,966,000  
0.15  
1,806,000  
EPM9320A  
EPM9400  
EPM9480  
12.00  
12.21  
12.42  
3,365,000  
3,764,000  
4,164,000  
0.15  
0.15  
0.15  
2,090,000  
2,374,000  
2,658,000  
EPM9560  
EPM9560A  
Tables 8 and 9 show the in-system programming and stand alone  
verification times for several common test clock frequencies.  
Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies  
Device  
fTCK  
Units  
10 MHz 5 MHz 2 MHz  
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz  
EPM9320  
12.09  
12.38  
13.27  
14.76  
17.72  
26.62  
41.45  
71.11  
s
EPM9320A  
EPM9400  
EPM9480  
12.34  
12.59  
12.84  
12.67  
12.96  
13.26  
13.68  
14.09  
14.50  
15.37  
15.98  
16.59  
18.73  
19.74  
20.75  
28.83  
31.03  
33.24  
45.65  
49.85  
54.06  
79.30  
87.49  
95.70  
s
s
s
EPM9560  
EPM9560A  
Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies  
Device  
fTCK  
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz  
Units  
10 MHz 5 MHz 2 MHz  
EPM9320  
0.33  
0.52  
1.06  
1.96  
3.77  
9.18  
18.21  
36.27  
s
EPM9320A  
EPM9400  
EPM9480  
0.36  
0.39  
0.42  
0.57  
0.63  
0.69  
1.20  
1.34  
1.48  
2.24  
2.53  
2.81  
4.33  
4.90  
5.47  
10.60  
12.02  
13.44  
21.05  
23.89  
26.73  
41.95  
47.63  
53.31  
s
s
s
EPM9560  
EPM9560A  
22  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
MAX 9000 devices can be programmed on Windows-based PCs with an  
Altera Logic Programmer card, the Master Programming Unit (MPU),  
and the appropriate device adapter. The MPU performs continuity  
checking to ensure adequate electrical contact between the adapter and  
the device.  
Programming  
with External  
Hardware  
For more information, see the Altera Programming Hardware Data Sheet.  
f
The MAX+PLUS II software can use text- or waveform-format test vectors  
created with the MAX+PLUS II Text Editor or Waveform Editor to test a  
programmed device. For added design verification, designers can  
perform functional testing to compare the functional behavior of a  
MAX 9000 device with the results of simulation.  
Data I/ O, BP Microsystems, and other programming hardware  
manufacturers also provide programming support for Altera devices.  
For more information, see Programming Hardware Manufacturers.  
f
MAX 9000 devices support JTAG BST circuitry as specified by IEEE Std.  
1149.1-1990. Table 10 describes the JTAG instructions supported by the  
MAX 9000 family. The pin-out tables starting on page 38 show the  
location of the JTAG control pins for each device. If the JTAG interface is  
not required, the JTAG pins are available as user I/ O pins.  
IEEE Std.  
1149.1 (JTAG)  
Boundary-Scan  
Support  
Table 10. MAX 9000 JTAG Instructions  
JTAG Instruction  
Description  
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during  
normal device operation, and permits an initial data pattern output at the device pins.  
EXTEST  
Allows the external circuitry and board-level interconnections to be tested by forcing a test  
pattern at the output pins and capturing test results at the input pins.  
BYPASS  
Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST  
data to pass synchronously through a selected device to adjacent devices during normal  
device operation.  
IDCODE  
Selects the IDCODE register and places it between TDIand TDO, allowing the IDCODE  
to be shifted out of TDO. Supported by the EPM9320A, EPM9400, EPM9480, and  
EPM9560A devices only.  
UESCODE  
Selects the user electronic signature (UESCODE) register and allows the UESCODE to  
be shifted out of TDOserially. This instruction is supported by MAX 9000A devices only.  
ISP Instructions  
These instructions are used when programming MAX 9000 devices via the JTAG ports  
with the BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam  
Byte-Code File (.jbc), or Serial Vector Format (.svf) File via an embedded processor or  
test equipment.  
Altera Corporation  
23  
MAX 9000 Programmable Logic Device Family Data Sheet  
The instruction register length for MAX 9000 devices is 10 bits. EPM9320A  
and EPM9560A devices support a 16-bit UESCODE register. Tables 11  
and 12 show the boundary-scan register length and device IDCODE  
information for MAX 9000 devices.  
Table 11. MAX 9000 Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EPM9320, EPM9320A  
EPM9400  
504  
552  
600  
648  
EPM9480  
EPM9560, EPM9560A  
Table 12. 32-Bit MAX 9000 Device IDCODE  
Note (1)  
Device  
IDCODE (32 Bits)  
Version  
(4 Bits)  
Part Number  
(16 Bits) (2)  
Manufacturer’s  
Identity (11 Bits) (1 Bit)  
1
EPM9320A (3)  
EPM9400  
0000 1001 0011 0010 0000 00001101110  
0000 1001 0100 0000 0000 00001101110  
0000 1001 0100 1000 0000 00001101110  
0000 1001 0101 0110 0000 00001101110  
1
1
1
1
EPM9480  
EPM9560A (3)  
Notes:  
(1) The IDCODE’s least significant bit (LSB) is always 1.  
(2) The most significant bit (MSB) is on the left.  
(3) Although the EPM9320A and EPM9560A devices support the IDCODE instruction,  
the EPM9320 and EPM9560 devices do not.  
Figure 11 shows the timing requirements for the JTAG signals.  
24  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 11. MAX 9000 JTAG Waveforms  
TMS  
TDI  
tJCP  
tJCH  
tJCL  
tJPH  
tJPSU  
TCK  
TDO  
t
tJPXZ  
tJPCO  
JPZX  
tJSSU  
tJSH  
Signal  
to Be  
Captured  
tJSCO  
tJSXZ  
tJSZX  
Signal  
to Be  
Driven  
Table 13 shows the JTAG timing parameters and values for MAX 9000  
devices.  
Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices  
Symbol  
Parameter  
Min Max Unit  
tJCP  
TCKclock period  
TCKclock high time  
TCKclock low time  
100  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tJCH  
tJCL  
50  
tJPSU  
tJPH  
JTAG port setup time  
20  
JTAG port hold time  
45  
tJPCO  
tJPZX  
tJPXZ  
tJSSU  
tJSH  
JTAG port clock to output  
25  
25  
25  
JTAG port high impedance to valid output  
JTAG port valid output to high impedance  
Capture register setup time  
20  
45  
Capture register hold time  
tJSCO  
tJSZX  
tJSXZ  
Update register clock to output  
Update register high impedance to valid output  
Update register valid output to high impedance  
25  
25  
25  
For detailed information on JTAG operation in MAX 9000 devices, refer to  
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera  
Devices).  
f
Altera Corporation  
25  
MAX 9000 Programmable Logic Device Family Data Sheet  
MAX 9000 devices offer a power-saving mode that supports low-power  
Programmable  
Speed/Power  
Control  
operation across user-defined signal paths or the entire device. Because  
most logic applications require only a small fraction of all gates to operate  
at maximum frequency, this feature allows total power dissipation to be  
reduced by 50% or more.  
The designer can program each individual macrocell in a MAX 9000  
device for either high-speed (i.e., with the Turbo Bitoption turned on) or  
low-power (i.e., with the Turbo Bit option turned off) operation. As a  
result, speed-critical paths in the design can run at high speed, while  
remaining paths operate at reduced power. Macrocells that run at low  
power incur a nominal timing delay adder (tLPA) for the LAB local array  
delay (tLOCAL).  
All MAX 9000 EPLDs contain a programmable security bit that controls  
access to the data programmed into the device. When this bit is  
programmed, a proprietary design implemented in the device cannot be  
copied or retrieved. This feature provides a high level of design security,  
because programmed data within EEPROM cells is invisible. The security  
bit that controls this function, as well as all other programmed data, is  
reset only when the device is erased.  
Design Security  
Generic Testing  
MAX 9000 EPLDs are fully functionally tested. Complete testing of each  
programmable EEPROM bit and all logic functionality ensures 100%  
programming yield. AC test measurements are taken under conditions  
equivalent to those shown in Figure 12. Test patterns can be used and then  
erased during the early stages of the production flow.  
Figure 12. MAX 9000 AC Test Conditions  
VCC  
Power supply transients can affect AC  
measurements. Simultaneous transitions of  
multiple outputs should be avoided for  
accurate measurement. Threshold tests  
must not be performed under AC  
conditions. Large-amplitude, fast ground-  
current transients normally occur as the  
device outputs discharge the load  
464 Ω  
(703 )  
Device  
Output  
To Test  
System  
250 Ω  
capacitances. When these transients flow  
through the parasitic inductance between  
the device ground pin and the test system  
ground, significant reductions in  
observable noise immunity can result.  
Numbers in parentheses are for 3.3-V  
outputs. Numbers without parentheses are  
for 5.0-V devices or outputs.  
C1 (includes  
JIG capacitance)  
(8.06 K)  
Device input  
rise and fall  
times < 3 ns  
26  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Tables 14 through 20 provide information on absolute maximum ratings,  
recommended operating conditions, operating conditions, and  
capacitance for MAX 9000 devices.  
Operating  
Conditions  
Table 14. MAX 9000 Device Absolute Maximum Ratings  
Note (1)  
Conditions  
Symbol  
Parameter  
Min  
Max  
Unit  
VCC  
VI  
Supply voltage  
With respect to ground (2)  
–2.0  
–2.0  
–2.0  
7.0  
7.0  
7.0  
V
V
V
DC input voltage  
VCCISP  
Supply voltage during in-system  
programming  
IOUT  
TSTG  
TAMB  
TJ  
DC output current, per pin  
Storage temperature  
Ambient temperature  
Junction temperature  
–25  
–65  
–65  
25  
mA  
° C  
° C  
° C  
° C  
No bias  
150  
135  
150  
135  
Under bias  
Ceramic packages, under bias  
PQFP and RQFP packages, under bias  
Table 15. MAX 9000 Device Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCCINT  
Supply voltage for internal logic and  
input buffers  
(3), (4)  
(3), (4)  
(3), (4)  
4.75  
(4.50)  
4.75  
5.25  
(5.50)  
5.25  
V
VCCIO  
Supply voltage for output drivers,  
5.0-V operation  
V
V
(4.50)  
3.00  
(5.50)  
3.60  
Supply voltage for output drivers,  
3.3-V operation  
(3.00)  
4.75  
(3.60)  
5.25  
VCCISP  
VI  
Supply voltage during in-system  
programming  
V
V
Input voltage  
–0.5  
VCCINT  
0.5  
+
VO  
TA  
Output voltage  
0
0
VCCIO  
70  
V
Ambient temperature  
For commercial use  
For industrial use  
For commercial use  
For industrial use  
° C  
° C  
° C  
° C  
ns  
–40  
0
85  
TJ  
Junction temperature  
90  
–40  
105  
40  
tR  
tF  
Input rise time  
Input fall time  
40  
ns  
Altera Corporation  
27  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 16. MAX 9000 Device DC Operating Conditions  
Notes (5), (6)  
Conditions  
Symbol  
Parameter  
Min  
Max  
Unit  
VIH  
High-level input voltage  
(7)  
2.0  
VCCINT  
0.5  
+
V
VIL  
Low-level input voltage  
–0.5  
2.4  
0.8  
V
V
V
V
VOH  
5.0-V high-level TTL output voltage  
3.3-V high-level TTL output voltage  
3.3-V high-level CMOS output voltage  
IOH = –4 mA DC, VCCIO = 4.75 V (8)  
OH = –4 mA DC, VCCIO = 3.00 V (8)  
I
2.4  
IOH = –0.1 mA DC, VCCIO = 3.00 V (8)  
VCCIO  
0.2  
VOL  
5.0-V low level TTL output voltage  
3.3-V low-level TTL output voltage  
3.3-V low-level CMOS output voltage  
IOL = 12 mA DC, VCCIO = 4.75 V (8)  
0.45  
0.45  
0.2  
V
V
I
I
OL = 12 mA DC, VCCIO = 3.00 V (8)  
OL = 0.1 mA DC, VCCIO = 3.00 V (8)  
V
II  
I/O pin leakage current of dedicated input VI = –0.5 to 5.5 V (9)  
pins  
–10  
–40  
10  
µA  
IOZ  
Tri-state output off-state current  
VI = –0.5 to 5.5 V  
40  
µA  
Table 17. MAX 9000 Device Capacitance: EPM9320, EPM9400, EPM9480 & EPM9560 Devices  
Note (10)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
C DIN1  
C DIN2  
C DIN3  
C DIN4  
C I/O  
Dedicated input capacitance  
Dedicated input capacitance  
Dedicated input capacitance  
Dedicated input capacitance  
I/O pin capacitance  
VIN = 0 V, f = 1.0 MHz  
18  
18  
17  
20  
12  
pF  
pF  
pF  
pF  
pF  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
Table 18. MAX 9000A Device Capacitance: EPM9320A & EPM9560A Devices  
Note (10)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
C DIN1  
C DIN2  
C DIN3  
C DIN4  
C I/O  
Dedicated input capacitance  
Dedicated input capacitance  
Dedicated input capacitance  
Dedicated input capacitance  
I/O pin capacitance  
VIN = 0 V, f = 1.0 MHz  
16  
10  
10  
12  
8
pF  
pF  
pF  
pF  
pF  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
VIN = 0 V, f = 1.0 MHz  
Table 19. MAX 9000 Device Typical ICC Supply Current Values  
Symbol  
Parameter  
Conditions  
EPM9320 EPM9400 EPM9480 EPM9560 Unit  
ICC1  
ICC supply current(low-power mode, VI = ground,  
standby, typical) no load (11)  
106  
132  
140  
146  
mA  
28  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 20. MAX 9000A Device Typical ICC Supply Current Values  
Symbol  
Parameter  
Conditions  
EPM9320A EPM9560A Unit  
ICC1  
ICC supply current (low-power mode, VI = ground, no load (11)  
99  
174  
mA  
standby, typical)  
Notes to tables:  
(1) See the Operating Requirements for Altera Devices Data Sheet.  
(2) Minimum DC input on I/ O pins is –0.5 V and on the four dedicated input pins is –0.3 V. During transitions, the  
inputs may undershoot to –2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.  
(3)  
(4) Numbers in parentheses are for industrial-temperature-range devices.  
(5) Typical values are for T = 25° C and V = 5.0 V.  
V
must rise monotonically.  
CC  
A
CC  
(6) These values are specified under the MAX 9000 recommended operating conditions, shown in Table 15 on page 27.  
(7) During in-system programming, the minimum V of the JTAG TCKpin is 3.6 V. The minimum V of this pin  
IH  
IH  
during JTAG testing remains at 2.0 V. To attain this 3.6-V V during programming, the ByteBlaster and  
IH  
ByteBlasterMV download cables must have a 5.0-V V  
.
CC  
(8) This parameter is measured with 50% of the outputs each sinking 12 mA. The I  
parameter refers to high-level  
OH  
TTL or CMOS output current; the I parameter refers to the low-level TTL or CMOS output current.  
OL  
(9) JTAG pin input leakage is typically –60 µΑ.  
(10) Capacitance is sample-tested only and is measured at 25° C.  
(11) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB. I is measured at 0° C.  
CC  
Figure 13 shows typical output drive characteristics for MAX 9000 devices  
with 5.0-V and 3.3-V VCCIO  
.
Figure 13. Output Drive Characteristics of MAX 9000 Devices  
Note (1)  
5.0-V  
3.3-V  
150  
120  
90  
150  
120  
90  
IOL  
IOL  
Typical I  
VCCIO = 3.3 V  
Room Temperature  
VCCIO = 5.0 V  
Room Temperature  
Typical I  
Output  
Current (mA)  
O
O
Output  
Current (mA)  
60  
30  
60  
30  
IOH  
IOH  
3.3  
1
2
3
4
5
1
2
3
4
5
Output Voltage (V)  
Output Voltage (V)  
Note:  
(1) Output drive characteristics include the JTAG TDOpin.  
Altera Corporation  
29  
MAX 9000 Programmable Logic Device Family Data Sheet  
The continuous, high-performance FastTrack Interconnect ensures  
Timing Model  
predictable performance and accurate simulation and timing analysis.  
This predictable performance contrasts with that of FPGAs, which use a  
segmented connection scheme and hence have unpredictable  
performance. Timing simulation and delay prediction are available with  
the MAX+PLUS II Simulator and Timing Analyzer, or with industry-  
standard EDA tools. The Simulator offers both pre-synthesis functional  
simulation to evaluate logic design accuracy and post-synthesis timing  
simulation with 0.1-ns resolution. The Timing Analyzer provides point-  
to-point timing delay information, setup and hold time prediction, and  
device-wide performance analysis.  
The MAX 9000 timing model in Figure 14 shows the delays that  
correspond to various paths and functions in the circuit. This model  
contains three distinct parts: the macrocell, IOC, and interconnect,  
including the row and column FastTrack Interconnect and LAB local array  
paths. Each parameter shown in Figure 14 is expressed as a worst-case  
value in the internal timing characteristics tables in this data sheet. Hand-  
calculations that use the MAX 9000 timing model and these timing  
parameters can be used to estimate MAX 9000 device performance.  
For more information on calculating MAX 9000 timing delays, see  
Application Note 77 (Understanding MAX 9000 Timing).  
f
30  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 14. MAX 9000 Timing Model  
Altera Corporation  
31  
MAX 9000 Programmable Logic Device Family Data Sheet  
Tables 21 through 24 show timing for MAX 9000 devices.  
Table 21. MAX 9000 External Timing Characteristics  
Note (1)  
Symbol  
Parameter  
Conditions  
Speed Grade  
-15  
Unit  
-10  
-20  
Min Max Min Max Min Max  
tPD1  
tPD2  
Row I/O pin input to row I/O  
pin output  
C1 = 35 pF (2)  
10.0  
15.0  
20.0  
ns  
Column I/O pin input to  
column I/O pin output  
C1 = 35 pF EPM9320A  
10.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(2)  
EPM9320  
16.0  
16.2  
16.4  
23.0  
23.2  
23.4  
EPM9400  
EPM9480  
EPM9560A  
EPM9560  
11.4  
16.6  
23.6  
tFSU  
tFH  
Global clock setup time for I/O  
cell  
3.0  
0.0  
5.0  
0.0  
6.0  
0.0  
Global clock hold time for I/O  
cell  
ns  
ns  
tFCO  
tCNT  
fCNT  
Global clock to I/O cell output C1 = 35 pF  
delay  
1.0 (3)  
4.8  
6.9  
1.0 (3)  
7.0  
8.5  
1.0 (3)  
8.5  
Minimum internal global clock (4)  
period  
10.0  
ns  
Maximum internal global clock (4)  
144.9  
117.6  
100.0  
MHz  
frequency  
32  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 22. MAX 9000 Internal Timing Characteristics  
Note (1)  
Symbol  
Parameter  
Conditions  
Speed Grade  
-15  
Unit  
-10  
-20  
Min Max Min Max Min Max  
tLAD  
tLAC  
tI C  
Logic array delay  
3.5  
3.5  
3.5  
3.5  
3.5  
0.5  
0.5  
0.4  
4.0  
4.0  
4.0  
4.0  
5.0  
1.0  
1.0  
1.0  
4.5  
4.5  
4.5  
4.5  
7.5  
2.0  
1.0  
1.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Logic control array delay  
Array clock delay  
tEN  
Register enable time  
Shared expander delay  
Parallel expander delay  
Register delay  
tSEXP  
tPEXP  
tRD  
tCOMB  
tSU  
Combinatorial delay  
Register setup time  
Register hold time  
Register preset time  
Register clear time  
FastTrack drive delay  
Low-power adder  
2.4  
2.0  
3.0  
3.5  
4.0  
4.5  
tH  
tPRE  
tCLR  
tFTD  
tLPA  
3.5  
3.7  
4.0  
4.0  
4.5  
4.5  
0.5  
1.0  
2.0  
(5)  
10.0  
15.0  
20.0  
Altera Corporation  
33  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 23. IOC Delays  
Symbol  
Parameter  
Conditions  
Speed Grade  
-15  
Unit  
-10  
-20  
Min Max Min Max Min Max  
tIODR  
tIODC  
I/O row output data delay  
I/O column output data delay  
I/O control delay  
0.2  
0.4  
0.2  
0.2  
1.5  
1.5  
ns  
ns  
tIOC  
(6)  
0.5  
0.6  
1.0  
1.0  
2.0  
1.5  
ns  
ns  
tIORD  
I/O register clock-to-output  
delay  
tIOCOMB  
tIOSU  
I/O combinatorial delay  
0.2  
1.0  
1.5  
ns  
ns  
I/O register setup time before  
clock  
2.0  
1.0  
4.0  
1.0  
5.0  
1.0  
tIOH  
I/O register hold time after  
clock  
ns  
tIOCLR  
tIOFD  
I/O register clear delay  
1.5  
0.0  
3.5  
3.0  
0.0  
4.5  
3.0  
0.5  
5.5  
ns  
ns  
ns  
I/O register feedback delay  
tINREG  
I/O input pad and buffer to I/O  
register delay  
tINCOMB  
tOD1  
I/O input pad and buffer to row  
and column delay  
1.5  
1.8  
2.0  
2.5  
2.5  
2.5  
ns  
ns  
Output buffer and pad delay, C1 = 35 pF  
Slow slew rate = off,  
VCCIO = 5.0 V  
tOD2  
Output buffer and pad delay, C1 = 35 pF  
Slow slew rate = off,  
2.3  
8.3  
3.5  
3.5  
ns  
ns  
V
CCIO = 3.3 V  
tOD3  
Output buffer and pad delay, C1 = 35 pF  
Slow slew rate = on,  
10.0  
10.5  
V
CCIO = 5.0 V or 3.3 V  
tXZ  
Output buffer disable delay  
C1 = 5 pF  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
ns  
ns  
tZX1  
Output buffer enable delay,  
Slow slew rate = off,  
VCCIO = 5.0 V  
C1 = 35 pF  
tZX2  
Output buffer enable delay,  
Slow slew rate = off,  
VCCIO = 3.3 V  
C1 = 35 pF  
C1 = 35 pF  
3.0  
9.0  
3.5  
3.5  
ns  
ns  
tZX3  
Output buffer enable delay,  
Slow slew rate = on,  
10.0  
10.5  
VCCIO = 3.3 V or 5.0 V  
34  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 24. Interconnect Delays  
Symbol  
Parameter  
Conditions  
Speed Grade  
-15  
Unit  
-10  
-20  
Min Max Min Max Min Max  
tLOCAL  
tROW  
LAB local array delay  
0.5  
0.9  
0.9  
4.0  
2.7  
4.5  
2.5  
0.5  
1.4  
1.7  
4.5  
3.5  
5.0  
3.5  
0.5  
2.0  
3.0  
5.0  
4.0  
5.5  
4.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
FastTrack row delay  
(6)  
(6)  
tCOL  
FastTrack column delay  
Dedicated input data delay  
Dedicated input clock delay  
Dedicated input clear delay  
tDIN_D  
tDIN_CLK  
tDIN_CLR  
tDIN_IOC  
Dedicated input I/O register  
clock delay  
tDIN_IO  
Dedicated input I/O register  
control delay  
5.5  
6.0  
6.5  
ns  
Notes to tables:  
(1) These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 15 on  
page 27.  
(2) See Application Note 77 (Understanding MAX 9000 Timing) for more information on test conditions for t  
and t  
PD1  
PD2  
delays.  
(3) This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This  
parameter applies for both global and array clocking as well as both macrocell and I/ O cell registers.  
(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed in each LAB.  
(5) The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode.  
(6) The t and t delays are worst-case values for typical applications. Post-compilation timing simulation  
t
ROW , COL,  
IOC  
or timing analysis is required to determine actual worst-case performance.  
The supply power (P) versus frequency (fMAX) for MAX 9000 devices can  
be calculated with the following equation:  
Power  
Consumption  
P = PINT + PIO = ICCINT × VCC + PIO  
The PIO value, which depends on the device output load characteristics  
and switching frequency, can be calculated using the guidelines given in  
Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value  
depends on the switching frequency and the application logic.  
The ICCINT value is calculated with the following equation:  
ICCINT  
= (A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED  
× fMAX × togLC  
)
Altera Corporation  
35  
MAX 9000 Programmable Logic Device Family Data Sheet  
The parameters in this equation are shown below:  
MCTON  
=
Number of macrocells with the Turbo Bit option turned on,  
as reported in the MAX+PLUS II Report File (.rpt)  
Number of macrocells in the device  
Number of macrocells used in the design, as reported in the  
MAX+PLUS II Report File  
MCDEV  
MCUSED  
=
=
fMAX  
togLC  
=
Highest clock frequency to the device  
= Average percentage of logic cells toggling at each clock  
(typically 12.5%)  
A, B, C = Constants, shown in Table 25  
Table 25. MAX 9000 ICC Equation Constants  
Device  
Constant A  
Constant B  
Constant C  
EPM9320  
EPM9320A  
EPM9400  
EPM9480  
EPM9560  
EPM9560A  
0.81  
0.56  
0.60  
0.68  
0.68  
0.56  
0.33  
0.31  
0.33  
0.29  
0.26  
0.31  
0.056  
0.024  
0.053  
0.064  
0.052  
0.024  
This calculation provides an ICC estimate based on typical conditions with  
no output load, using a typical pattern of a 16-bit, loadable, enabled  
up/ down counter in each LAB. Actual ICC values should be verified  
during operation, because the measurement is sensitive to the actual  
pattern in the device and the environmental operating conditions.  
Figure 15 shows typical supply current versus frequency for MAX 9000  
devices.  
36  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 1 of 2)  
EPM9320A  
EPM9320  
1000  
800  
600  
400  
200  
1000  
800  
Typical  
ICC Active  
(mA)  
Typical  
ICC Active  
(mA)  
600  
400  
118 MHz  
144 MHz  
Turbo  
42 MHz  
200  
Turbo  
59 MHz  
Non-Turbo  
Non-Turbo  
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
125  
Frequency (MHz)  
Frequency (MHz)  
EPM9480  
EPM9400  
1000  
1000  
800  
800  
600  
400  
200  
118 MHz  
600  
400  
200  
Typical  
ICC Active  
(mA)  
Typical  
ICC Active  
(mA)  
118 MHz  
Turbo  
Turbo  
42 MHz  
42 MHz  
Non-Turbo  
Non-Turbo  
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
125  
Frequency (MHz)  
Frequency (MHz)  
Altera Corporation  
37  
MAX 9000 Programmable Logic Device Family Data Sheet  
Figure 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2)  
EPM9560A  
EPM9560  
1000  
1000  
118 MHz  
800  
600  
400  
200  
800  
600  
400  
200  
Typical  
ICC Active  
(mA)  
Typical  
ICC Active  
(mA)  
144 MHz  
Turbo  
Turbo  
42 MHz  
59 MHz  
Non-Turbo  
Non-Turbo  
0
25  
50  
75  
100  
125  
0
25  
50  
75  
100  
125  
Frequency (MHz)  
Frequency (MHz)  
Tables 26 through 29 show the dedicated pin names and numbers for each  
EPM9320, EPM9320A, EPM9400, EPM9480, EPM9560, and EPM9560A  
device package.  
Device  
Pin-Outs  
Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 1 of 2)  
Note (1)  
Pin Name 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3)  
356-Pin BGA  
DIN1  
(GCLK1)  
1
182  
V10  
U10  
AD13  
AF14  
DIN2  
84  
183  
(GCLK2)  
DIN3(GCLR) 13  
DIN4(GOE) 72  
153  
4
V17  
W2  
A9  
AD1  
AC24  
A18  
E23  
A13  
D3  
TCK  
TMS  
TDI  
TDO  
43  
55  
42  
30  
78  
49  
79  
108  
D6  
C11  
A18  
38  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of 2)  
Note (1)  
Pin Name 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3)  
356-Pin BGA  
GND  
6, 18, 24, 25, 48, 14, 20, 24, 31, 35, D4, D5, D16, E4, E5, E6,  
A9, A22, A25, A26, B25,  
B26, D2, E1, E26, F2, G1,  
61, 67, 70  
41, 42, 43, 44, 46, E15, E16, F5, F15, G5,  
47, 66, 85, 102,  
G15, H5, H15, J5, J15, K5, G25, G26, H2, J1, J25, J26,  
110, 113, 114, 115, K15, L5, L15, M5, M15, N5, K2, L26, M26, N1, N25,  
116, 118, 121, 122, N15, P4, P5, P15, P16, R4, P26, R2, T1, U2, U26, V1,  
132, 133, 143, 152, R5, R15, R16, T4, T5, T16 V25, W25, Y26, AA2, AB1,  
170, 189, 206  
AB26, AC26, AE1, AF1,  
AF2, AF4, AF7, AF20  
VCCINT  
(5.0 V only) 64, 71  
14, 21, 28, 57,  
10, 19, 30, 45, 112, D15, E8, E10, E12, E14,  
D26, F1, H1, K26, N26, P1,  
U1, W26, AE26, AF25,  
AF26  
128, 139, 148  
R7, R9, R11, R13, R14,  
T14  
VCCIO  
15, 37, 60, 79  
5, 25, 36, 55, 72,  
D14, E7, E9, E11, E13, R6, A1, A2, A21, B1, B10, B24,  
(3.3 or 5.0 V)  
91, 111, 127, 138, R8, R10, R12, T13, T15  
159, 176, 195  
D1, H26, K1, M25, R1, V26,  
AA1, AC25, AF5, AF8,  
AF19  
No Connect 29  
(N.C.)  
6, 7, 8, 9, 11, 12,  
B6, K19, L2, L4, L18, L19, B4, B5, B6, B7, B8, B9,  
13, 15, 16, 17, 18, M1, M2, M3, M4, M16, M17, B11, B12, B13, B14, B15,  
109, 140, 141, 142, M18, M19, N1, N2, N3, N4, B16, B18, B19, B20, B21,  
144, 145, 146, 147, N16, N17, N18, N19, P1,  
B22, B23, C4, C23, D4,  
149, 150, 151  
P2, P3, P17, P18, P19, R1, D23, E4, E22, F4, F23, G4,  
R2, R3, R17, R18, R19, T1, H4, H23, J23, K4, L4, L23,  
T2, T3, T17, T18, T19, U1, N4, P4, P23, R3, R26, T2,  
U2, U3, U17, U18, U19, V1, T3, T4, T5, T22, T23, T24,  
V2, V19, W1  
T25, T26, U3, U4, U5, U22,  
U23, U24, U25, V2, V3, V4,  
V5, V22, V23, V24, W1,  
W2, W3, W4, W5, W22,  
W23, W24, Y1, Y2, Y3, Y4,  
Y5, Y22, Y23, Y24, Y25,  
AA3, AA4, AA5, AA22,  
AA23, AA24, AA25, AA26,  
AB2, AB3, AB4, AB5,  
AB23, AB24, AB25, AC1,  
AC2, AC23, AD4, AD23,  
AE4, AE5, AE6, AE7, AE9,  
AE11, AE12, AE14, AE15,  
AE16, AE18, AE19, AE20,  
AE21, AE22, AE23  
VPP(4)  
56  
60  
48  
C4  
E25  
168  
Total User  
132  
168  
I/O Pins (5)  
Altera Corporation  
39  
MAX 9000 Programmable Logic Device Family Data Sheet  
Notes:  
(1) All pins not listed are user I/ O pins.  
(2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74  
(Evaluating Power for Altera Devices).  
(3) EPM9320A devices are not offered in this package.  
(4) During in-system programming, each devices VPPpin must be connected to the 5.0-V power supply. During  
normal device operation, the VPPpin is pulled up internally and can be connected to the 5.0-V supply or left  
unconnected.  
(5) The user I/ O pin count includes dedicated input pins and all I/ O pins.  
Table 27. EPM9400 Dedicated Pin-Outs  
Note (1)  
Pin Name 84-Pin PLCC (2)  
208-Pin RQFP  
240-Pin RQFP  
DIN1(GCLK1)  
2
182  
183  
153  
4
210  
211  
187  
234  
91  
DIN2(GCLK2)  
DIN3(GCLR)  
DIN4(GOE)  
TCK  
1
12  
74  
43  
54  
42  
31  
78  
TMS  
49  
68  
TDI  
79  
92  
TDO  
108  
114  
GND  
6, 13, 20, 26, 27, 47, 60, 14, 20, 24, 31, 35, 41, 42, 5, 14, 25, 34, 45, 54, 65,  
66, 69, 73  
43, 44, 46, 47, 66, 85, 102, 66, 81, 96, 110, 115, 126,  
110, 113, 114, 115, 116,  
118, 121, 122, 132, 133,  
143, 152, 170, 189, 206  
127, 146, 147, 166, 167,  
186, 200, 216, 229  
VCCINT(5.0 V only)  
VCCIO(3.3 or 5.0 V)  
16, 23, 30, 56, 63, 70  
17, 37, 59, 80  
10, 19, 30, 45, 112, 128,  
139, 148  
4, 24, 44, 64, 117, 137,  
157, 177  
5, 25, 36, 55, 72, 91, 111, 15, 35, 55, 73, 86, 101,  
127, 138, 159, 176, 195  
116, 136, 156, 176, 192,  
205, 220, 235  
No Connect (N.C.)  
6, 7, 8, 9, 11, 12, 13, 109, 1, 2, 3, 6, 7, 8, 9, 10, 11,  
144, 145, 146, 147, 149,  
150, 151  
12, 13, 168, 169, 170,  
171, 172, 173, 174, 175,  
178, 179, 180, 181, 182,  
183, 184, 185, 236, 237,  
238, 239, 240  
VPP(3)  
55  
59  
48  
67  
Total User I/O Pins (4)  
139  
159  
Notes:  
(1) All pins not listed are user I/ O pins.  
(2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74  
(Evaluating Power for Altera Devices) for more information.  
(3) During in-system programming, each devices VPPpin must be connected to the 5.0-V power supply. During  
normal device operation, the VPPpin is pulled up internally and can be connected to the 5.0-V supply or left  
unconnected.  
(4) The user I/ O pin count includes dedicated input pins and all I/ O pins.  
40  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 28. EPM9480 Dedicated Pin-Outs  
Note (1)  
Pin Name 208-Pin RQFP  
240-Pin RQFP  
DIN1(GCLK1)  
182  
183  
153  
4
210  
211  
187  
234  
91  
DIN2(GCLK2)  
DIN3(GCLR)  
DIN4(GOE)  
TCK  
78  
TMS  
49  
68  
TDI  
79  
92  
TDO  
108  
114  
GND  
14, 20, 24, 31, 35, 41, 42, 5, 14, 25, 34, 45, 54, 65,  
43, 44, 46, 47, 66, 85, 66, 81, 96, 110, 115, 126,  
102, 110, 113, 114, 115, 127, 146, 147, 166, 167,  
116, 118, 121, 122, 132, 186, 200, 216, 229  
133, 143, 152, 170, 189,  
206  
VCCINT(5.0 V only)  
VCCIO(3.3 or 5.0 V)  
10, 19, 30, 45, 112, 128, 4, 24, 44, 64, 117, 137,  
139, 148  
157, 177  
5, 25, 36, 55, 72, 91, 111, 15, 35, 55, 73, 86, 101,  
127, 138, 159, 176, 195 116, 136, 156, 176, 192,  
205, 220, 235  
No Connect (N.C.)  
6, 7, 8, 9, 109, 149, 150, 1, 2, 3, 178, 179, 180,  
151  
181, 182, 183, 184, 185,  
236, 237, 238, 239, 240  
VPP(2)  
48  
67  
Total User I/O Pins (3)  
146  
175  
Notes:  
(1) All pins not listed are user I/ O pins.  
(2) During in-system programming, each devices VPPpin must be connected to the  
5.0-V power supply. During normal device operation, the VPPpin is pulled up  
internally and can be connected to the 5.0-V supply or left unconnected.  
(3) The user I/ O pin count includes dedicated input pins and all I/ O pins.  
Altera Corporation  
41  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2)  
Note (1)  
Pin Name  
208-Pin RQFP  
240-Pin RQFP  
280-Pin PGA (2) 304-Pin RQFP (2)  
356-Pin BGA  
DIN1  
182  
210  
V10  
266  
AD13  
(GCLK1)  
DIN2  
183  
211  
U10  
267  
AF14  
(GCLK2)  
DIN3(GCLR) 153  
187  
234  
91  
V17  
W2  
A9  
237  
296  
114  
85  
AD1  
AC24  
A18  
E23  
A13  
D3  
DIN4(GOE)  
TCK  
4
78  
49  
79  
108  
TMS  
68  
D6  
TDI  
92  
C11  
A18  
115  
144  
TDO  
114  
GND  
14, 20, 24, 31, 35, 5, 14, 25, 34, 45, D4, D5, D16, E4, 13, 22, 33, 42, 53, A9, A22, A25,  
41, 42, 43, 44, 46, 54, 65, 66, 81, 96, E5, E6, E15, E16, 62, 73, 74, 102,  
A26, B25, B26,  
D2, E1, E26, F2,  
G1, G25, G26,  
H2, J1, J25, J26,  
K2, L26, M26, N1,  
N25, P26, R2, T1,  
U2, U26, V1, V25,  
W25, Y26, AA2,  
AB1, AB26,  
47, 66, 85, 102,  
110, 113, 114,  
115, 116, 118,  
121, 122, 132,  
133, 143, 152,  
170, 189, 206  
110, 115, 126,  
127, 146, 147,  
166, 167, 186,  
200, 216, 229  
F5, F15, G5, G15, 121, 138, 155,  
H5, H15, J5, J15, 166, 167, 186,  
K5, K15, L5, L15, 187, 206, 207,  
M5, M15, N5,  
226, 254, 273,  
N15, P4, P5, P15, 290  
P16, R4, R5, R15,  
R16, T4, T5, T16  
AC26, AE1, AF1,  
AF2, AF4, AF7,  
AF20  
VCCINT  
10, 19, 30, 45,  
112, 128, 139,  
148  
4, 24, 44, 64, 117, D15, E8, E10,  
12, 32, 52, 72,  
D26, F1, H1, K26,  
N26, P1, U1,  
W26, AE26,  
(5.0 V only)  
137, 157, 177 E12, E14, R7, R9, 157, 177, 197,  
R11, R13, R14,  
T14  
217  
AF25, AF26  
VCCIO  
5, 25, 36, 55, 72, 15, 35, 55, 73, 86, D14, E7, E9, E11, 3, 23, 43, 63, 91, A1, A2, A21, B1,  
(3.3 or 5.0 V) 91, 111, 127, 138, 101, 116, 136,  
E13, R6, R8, R10, 108, 127, 156,  
B10, B24, D1,  
H26, K1, M25,  
R1, V26, AA1,  
AC25, AF5, AF8,  
AF19  
159, 176, 195  
156, 176, 192,  
205, 220, 235  
R12, T13, T15  
176, 196, 216,  
243, 260, 279  
42  
Altera Corporation  
MAX 9000 Programmable Logic Device Family Data Sheet  
Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 2 of 2)  
Note (1)  
Pin Name  
208-Pin RQFP  
240-Pin RQFP  
280-Pin PGA (2) 304-Pin RQFP (2)  
356-Pin BGA  
No Connect 109  
(N.C.)  
B6, W1  
1, 2, 76, 77, 78,  
B4, B5, B6, B7,  
79, 80, 81, 82, 83, B8, B9, B11, B12,  
84, 145, 146, 147, B13, B14, B15,  
148, 149, 150,  
151, 152, 153,  
154, 227, 228,  
229, 230, 231,  
232, 233, 234,  
235, 236, 297,  
298, 299, 300,  
301, 302, 303,  
304  
B16, B18, B19,  
B20, B21, B22,  
B23, C4, C23, D4,  
D23, E4, E22, F4,  
F23, G4, H4, H23,  
J23, K4, L4, L23,  
N4, P4, P23, T4,  
T23, U4, V4, V23,  
W4, Y4, AA4,  
AA23, AB4,  
AB23, AC23,  
AD4, AD23, AE4,  
AE5, AE6, AE7,  
AE9, AE11,  
AE12, AE14,  
AE15, AE16,  
AE18, AE19,  
AE20, AE21,  
AE22, AE23  
VPP(3)  
48  
67  
C4  
75  
E25  
216  
Total User  
153  
191  
216  
216  
I/O Pins (4)  
Notes:  
(1) All pins not listed are user I/ O pins.  
(2) EPM9560A devices are not offered in this package.  
(3) During in-system programming, each devices VPPpin must be connected to the 5.0-V power supply. During  
normal device operation, the VPPpin is pulled up internally and can be connected to the 5.0-V supply or left  
unconnected.  
(4) The user I/ O pin count includes dedicated input pins and all I/ O pins.  
Altera Corporation  
43  
MAX 9000 Programmable Logic Device Family Data Sheet  
Information contained in the MAX 9000 Programmable Logic Device Family  
Data Sheet version 6.5 supersedes information published in previous  
versions.  
Revision  
History  
Version 6.5  
Version 6.6 of the MAX 9000 Programmable Logic Device Family Data Sheet  
contains the following change:  
Added Tables 7 through 9.  
Added “Programming Sequence” on page 20 and “Programming  
Times” on page 20  
Version 6.4  
Version 6.4 of the MAX 9000 Programmable Logic Device Family Data Sheet  
contains the following change: Updated text on page 23.  
Version 6.3  
Version 6.3 of the MAX 9000 Programmable Logic Device Family Data Sheet  
contains the following change: added Note (7) to Table 16.  
®
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the  
stylized Altera logo, specific device designations, and all other words and logos that are identified as  
trademarks and/ or service marks are, unless noted otherwise, the trademarks and service marks of Altera  
Corporation in the U.S. and other countries. All other product or service names are the property of their  
respective holders. Altera products are protected under numerous U.S. and foreign patents and pending  
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to  
current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes  
to any products and services at any time without notice. Altera assumes no responsibility  
101 Innovation Drive  
San Jose, CA 95134  
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http://www.altera.com  
Applications Hotline:  
(800) 800-EPLD  
or liability arising out of the application or use of any information, product, or service  
described herein except as expressly agreed to in writing by Altera Corporation. Altera  
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Literature Services:  
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Altera Corporation  
Printed on Recycled Paper.  
MAX 9000 Programmable Logic Device Family Data Sheet  
Altera Corporation  
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MAX 9000 Programmable Logic Device Family Data Sheet  
46  
Altera Corporation  
配单直通车
EPM9320ABC356-10产品参数
型号:EPM9320ABC356-10
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Active
零件包装代码:BGA
包装说明:LBGA,
针数:356
Reach Compliance Code:unknown
风险等级:5.77
其他特性:320 MACROCELLS; 20 LABS; 484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
最大时钟频率:144.9 MHz
JESD-30 代码:S-PBGA-B356
JESD-609代码:e0
长度:35 mm
湿度敏感等级:NOT SPECIFIED
专用输入次数:
I/O 线路数量:168
端子数量:356
最高工作温度:70 °C
最低工作温度:
组织:0 DEDICATED INPUTS, 168 I/O
输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY
封装代码:LBGA
封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):220
可编程逻辑类型:EE PLD
传播延迟:10.8 ns
认证状态:COMMERCIAL
座面最大高度:1.63 mm
最大供电电压:5.25 V
最小供电电压:4.75 V
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:TIN LEAD
端子形式:BALL
端子节距:1.27 mm
端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:35 mm
Base Number Matches:1
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