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产品型号FDS6672A的概述

芯片 FDS6672A 的概述 FDS6672A 是一款由 Fairchild Semiconductor（现为 ON Semiconductor 的一部分）设计的 N 沟道和 P 沟道增强型场效应晶体管 (MOSFET)。该芯片主要用于电源管理应用，具备高效率、低开关损耗的特点，因此在多个领域中得到广泛应用，包括电源转换、直流-直流转换器、负载开关以及电机驱动器等。由于其低导通电阻和较高的电流承受能力，FDS6672A 在各类电子设备中表现出色，尤其是在需要高性能和高可靠性的场合。芯片 FDS6672A 的详细参数 FDS6672A 的重要参数包括： - 最大漏极-源极电压 (V_DS): 30V - 最大栅极-源极电压 (V_GS): ±20V - 导通电阻 (R_DS(on)): - N 沟道：典型值 7.5mΩ（在 V_GS = 10V 时） - P 沟道：典型值 ...

产品型号FDS6672A的Datasheet PDF文件预览

February 2000

PRELIMINARY

FDS6672A

30V N-Channel PowerTrench MOSFET

General Description

Features

This N-Channel MOSFET has been designed

specifically to improve the overall efficiency of DC/DC

converters using either synchronous or conventional

switching PWM controllers. It has been optimized for

low gate charge, low R_DS(ON)and fast switching speed.

• 12.5 A, 30 V. R_DS(ON)= 8 mΩ @ V_GS= 10 V

R_DS(ON)= 9.5 mΩ @ V_GS= 4.5 V

• High performance trench technology for extremely

low R_DS(ON)

Applications

• Low gate charge (33 nC typical)

• DC/DC converter

• High power and current handling capability

SO-8

Absolute Maximum Ratings T_A=25^oC unless otherwise noted

Symbol

V_DSS

Parameter

Drain-Source Voltage

Ratings

Units

V_GSS

Gate-Source Voltage

±12

12.5

I_D

Drain Current – Continuous

– Pulsed

(Note 1a)

Power Dissipation for Single Operation

(Note 1a)

(Note 1b)

(Note 1c)

2.5

P_D

1.2

1.0

T_J, T_STG

Operating and Storage Junction Temperature Range

-55 to +150

°C

Thermal Characteristics

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

(Note 1a)

(Note 1)

R_θJA

°C/W

R_θJC

Package Marking and Ordering Information

Device Marking

Device

Reel Size

Tape width

Quantity

FDS6672A

13’’

12mm

2500 units

FDS6672A Rev B(W)

2000 Fairchild Semiconductor Corporation

Electrical Characteristics

T_A= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min Typ Max Units

Off Characteristics

BV_DSS

Drain–Source Breakdown Voltage

_GS= 0 V, I_D= 250 µA

∆BV^DSS

∆T_J

Breakdown Voltage Temperature

Coefficient

I_D= 250 µA, Referenced to 25°C

mV/°C

I_DSS

Zero Gate Voltage Drain Current

Gate–Body Leakage, Forward

Gate–Body Leakage, Reverse

V_DS= 24 V, V_GS= 0 V

V_GS= 12 V, V_DS= 0 V

V_GS= –12 V V_DS= 0 V

µA

I_GSSF

I_GSSR

100

–100

On Characteristics

(Note 2)

V_GS(th)

Gate Threshold Voltage

0.8

1.2

-4

2.0

_DS= V_GS, I_D= 250 µA

∆V^GS(th)

∆T_J

R_DS(on)

Gate Threshold Voltage

Temperature Coefficient

Static Drain–Source

On–Resistance

I_D= 250 µA, Referenced to 25°C

mV/°C

mΩ

V_GS= 10 V, I_D= 14 A

V_GS= 4.5 V, I_D= 12.5 A

V_GS= 4.5 V, I_D= 12.5 A,

T_J=125°C

6.8

8.2

11.5

9.5

I_D(on)

g_FS

On–State Drain Current

V_GS= 10 V, V_DS= 5 V

Forward Transconductance

V_DS= 10 V,

I_D= 15 A

Dynamic Characteristics

C_iss

C_oss

C_rss

Input Capacitance

5070

550

V_DS= 15 V, V _GS= 0 V,

f = 1.0 MHz

Output Capacitance

Reverse Transfer Capacitance

230

Switching Characteristics ^{(Note 2)}

_DD= 10 V, I_D= 1 A,

t_d(on)

t_r

t_d(off)

t_f

Turn–On Delay Time

Turn–On Rise Time

Turn–Off Delay Time

Turn–Off Fall Time

Total Gate Charge

Gate–Source Charge

Gate–Drain Charge

7.5

6.8

V_GS= 4.5 V, R_GEN= 6 Ω

100

_DS= 15 V, I_D= 15 A,

Q_g

Q_gs

Q_gd

V_GS= 4.5 V

Drain–Source Diode Characteristics and Maximum Ratings

I_S

Maximum Continuous Drain–Source Diode Forward Current

2.1

1.2

Drain–Source Diode Forward

V_SD

_GS= 0 V, I_S= 2.1 A

(Note 2)

0.7

Voltage

Notes:

1. R_θJAis the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

the drain pins. R_θJCis guaranteed by design while R_θCAis determined by the user's board design.

a) 50°/W when

b) 105°/W when

c) 125°/W when mounted on a

minimum pad.

mounted on a 1in²

pad of 2 oz copper

mounted on a .04 in²

pad of 2 oz copper

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

FDS6672A Rev B(W)

Typical Characteristics

1.5

1.3

1.1

0.9

V_GS= 4.5V

3.5V

3.0V

V_GS= 2.5V

2.5V

2.0V

3.0V

3.5V

4.0V

4.5V

0.5

1.5

150

I_D, DRAIN CURRENT (A)

V_DS, DRAIN-SOURCE VOLTAGE (V)

Figure 1. On-Region Characteristics.

Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

0.025

1.8

I_D= 6 A

I_D= 15A

_GS= 10V

1.6

1.4

1.2

0.02

0.015

0.01

0.005

T_A= 125^oC

T_A= 25^oC

0.8

0.6

-50

-25

100

125

T_J, JUNCTION TEMPERATURE (^oC)

V_GS, GATE TO SOURCE VOLTAGE (V)

Figure 3. On-Resistance Variation with

Temperature.

Figure 4. On-Resistance Variation with

Gate-to-Source Voltage.

100

V_GS= 0V

V_DS= 5V

T_A= 125^oC

25^oC

-55^oC

0.1

T_A= 125^oC

25^oC

-55^oC

0.01

0.001

0.2

0.4

0.6

0.8

1.2

1.4

0.5

1.5

2.5

V_SD, BODY DIODE FORWARD VOLTAGE (V)

V_GS, GATE TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics.

Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

FDS6672A Rev B(W)

Typical Characteristics

8000

6000

4000

2000

I_D= 12.5A

f = 1MHz

V_GS= 0 V

10V

V_DS= 5V

C_ISS

15V

C_OSS

C_RSS

Q_g, GATE CHARGE (nC)

V_DS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Gate Charge Characteristics.

Figure 8. Capacitance Characteristics.

100

100µs

SINGLE PULSE

R_θJA= 125°C/W

T_A= 25°C

R_DS(ON)LIMIT

1ms

10ms

100ms

10s

V_GS= 10V

SINGLE PULSE

0.1

_θJA= 125^oC/W

T_A= 25^oC

0.01

0.1

100

0.001

0.01

0.1

100

V_DS, DRAIN-SOURCE VOLTAGE (V)

t₁, TIME (sec)

Figure 9. Maximum Safe Operating Area.

Figure 10. Single Pulse Maximum

Power Dissipation.

D = 0.5

0.2

_θJA(t) = r(t) + R_θJA

_θJA= 125°C/W

0.1

0.05

0.02

P(pk)

t₁

0.01

t₂

0.01

SINGLE PULSE

T_J- T_A= P * R_θJA(t)

Duty Cycle, D = t₁/ t₂

0.001

0.0001

0.001

0.01

0.1

100

1000

t₁, TIME (sec)

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.

Transient thermal response will change depending on the circuit board design.

FDS6672A Rev B(W)

SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging

Configuration: Figure 1.0

Packaging Description:

SOIC-8 parts are shipped in tape. The carrier tape is

ELECTROSTATIC

SENSITIVE DEVICES

DO NO

RO NG

CTROS

ATIC

made from dissipative (carbon filled) polycarbonate

CTRO

AGN

AG NE

R R ADIO ACTIVE FI ELD S

TNR DATE

PT NUMB E

resin. The cover tape is a multilayer film (Heat Activated

Adhesive in nature) primarily composed of polyester film,

adhesive layer, sealant, and anti-static sprayed agent.

These reeled parts in standard option are shipped with

2,500 units per 13" or 330cm diameter reel. The reels are

dark blue in color and is made of polystyrene plastic (anti-

static coated). Other option comes in 500 units per 7" or

177cm diameter reel. This and some other options are

further described in the Packaging Information table.

PEEL STRENGTH MIN ______________gms

MAX _____________gms

Antistatic Cover Tape

ESD Label

These full reels are individually barcode labeled and

placed inside

a standard intermediate box (illustrated in

figure 1.0) made of recyclable corrugated brown paper.

One box contains two reels maximum. And these boxes

are placed inside

comes in different sizes depending on the number of parts

shipped.

a barcode labeled shipping box which

Static Dissipative

Embossed Carrier Tape

F63TNR

Label

NDS

9959

852

Customized

Label

Pin 1

SOIC (8lds) Packaging Information

Standard

L86Z

F011

D84Z

Packaging Option

(no flow code)

SOIC-8 Unit Orientation

Packaging type

TNR

2,500

Rail/Tube

TNR

4,000

TNR

500

Qty per Reel/Tube/Bag

Reel Size

13" Dia

7" Dia

Box Dimension (mm)

Max qty per Box

343x64x343 530x130x83 343x64x343 184x187x47

5,000

0.0774

0.6060

30,000

0.0774

8,000

0.0774

0.9696

1,000

0.0774

0.1182

Weight per unit (gm)

Weight per Reel (kg)

Note/Comments

343mm x 342mm x 64mm

Standard Intermediate box

ESD Label

F63TNR Label sample

F63TNLabel

ESD Label

F63TN Label

LOT: CBVK741B019

FSID: FDS9953A

QTY: 2500

SPEC:

D/C1: D9842

D/C2:

QTY1:

QTY2:

SPEC REV:

CPN:

N/F: F

(F63TNR)3

SOIC(8lds) Tape Leader and Trailer

Configuration: Figure 2.0

Carrier Tape

Cover Tape

Components

Trailer Tape

Leader Tape

640mm minimum or

80 empty pockets

1680mm minimum or

210 empty pockets

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape

Configuration: Figure 3.0

User Direction of Feed

Dimensions are in millimeter

Pkg type

0.450

+/-

0.150

(8lds)

SOIC

(12mm)

6.50

+/-0.10

5.30

+/-0.10

12.0

+/-0.3

1.55

+/-0.05

1.60

+/-0.10

1.75

+/-0.10

10.25

min

5.50

+/-0.05

8.0

+/-0.1

4.0

+/-0.1

2.1

+/-0.10

9.2

+/-0.3

0.06

+/-0.02

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

rotational and lateral movement requirements (see sketches A, B, and C).

0.5mm

maximum

20 deg maximum

Typical

component

cavity

center line

0.5mm

maximum

20 deg maximum component rotation

Typical

component

center line

Sketch A (Side or Front Sectional View)

Component Rotation

Sketch C (Top View)

Component lateral movement

Sketch B (Top View)

Component Rotation

SOIC(8lds) Reel Configuration: Figure 4.0

W1 Measured at Hub

Dim A

Max

Dim A

max

See detail AA

Dim N

7"Diameter Option

B Min

Dim C

See detail AA

Dim D

min

13" Diameter Option

W2 max Measured at Hub

DETAIL AA

Dim W2

Dimensions are in inches and millimeters

Reel

Option

Tape Size

12mm

Dim A

Dim B

Dim C

Dim D

Dim N

Dim W1

Dim W3 (LSL-USL)

7.00

177.8

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

2.165

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.469 – 0.606

11.9 – 15.4

7" Dia

13.00

330

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

7.00

178

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.469 – 0.606

11.9 – 15.4

12mm

13" Dia

1998 Fairchild Semiconductor Corporation

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0774

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

CoolFET™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench

QFET™

SyncFET™

TinyLogic™

UHC™

CROSSVOLT™

E²CMOS^TM

VCX™

FACT™

FACT Quiet Series™

QS™

FAST^®

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

FASTr™

GTO™

HiSeC™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or

In Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. D

FDS6672A相关文章

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FDS6672A产品参数

型号:	FDS6672A
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOT
包装说明：	SO-8
针数：	8
Reach Compliance Code：	unknown
风险等级：	5.36
Is Samacsys：	N
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	30 V
最大漏极电流 (ID)：	12.5 A
最大漏源导通电阻：	0.008 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
湿度敏感等级：	1
元件数量：	1
端子数量：	8
工作模式：	ENHANCEMENT MODE
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
极性/信道类型：	N-CHANNEL
最大脉冲漏极电流 (IDM)：	50 A
认证状态：	COMMERCIAL
表面贴装：	YES
端子面层：	MATTE TIN
端子形式：	GULL WING
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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