GAL16V8D-15LPN全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

GAL16V8

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

I/CLK

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 3.5 ns Maximum Propagation Delay

— Fmax = 250 MHz

CLK

I/O/Q

8

OLMC

— 3.0 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

I

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

OLMC

• ACTIVE PULL-UPS ON ALL PINS

8

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 20-pin PAL^®Devices with Full

Function/Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

I/O/Q

I/OE

OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

Pin Configuration

PLCC

Description

I

I/CLK Vcc I/O/Q

2

20

DIP

18

16

I/O/Q

4

6

I

The GAL16V8, at 3.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide the highest speed

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

I/O/Q

I

1

20

Vcc

I/CLK

GAL16V8

Top View

I

I/O/Q

I/OE

I

I/O/Q

I

GAL

14

I

8

9

I

11

13

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL16V8 are the PAL architectures listed

in the table of the macrocell description section. GAL16V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

16V8

GND I/OE I/O/Q I/O/Q

5

I

SOIC

15

I/CLK

I

1

20

Vcc

I

I/O/Q

I/OE

I

GAL

16V8

Top

5

I

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

15

11

10

11

GND

I

View

I

10

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

1

16v8_11

Specifications GAL16V8

GAL16V8 Ordering Information

Conventional Packaging

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

3.5

5

2.5

3

3.0

4

115

GAL16V8D-3LJ¹

20-Lead PLCC

GAL16V8C-5LP¹

GAL16V8D-5LJ

GAL16V8D-7LP

GAL16V8C-7LP¹

GAL16V8D-7LJ

GAL16V8D-7LS¹

GAL16V8D-10QP

GAL16V8D-10QJ

20-Pin Plastic DIP

20-Lead PLCC

115

7.5

7

5

20-Pin Plastic DIP

20-Lead PLCC

115

55

20-Pin SOIC

10

7

20-Pin Plastic DIP

20-Lead PLCC

20-Pin Plastic DIP

20-Lead PLCC

55

115

55

GAL16V8D-10LP

GAL16V8D-10LJ

GAL16V8D-10LS¹

GAL16V8D-15QP

GAL16V8D-15QJ

GAL16V8D-15LP

20-Pin SOIC

15

25

12

15

10

12

20-Pin Plastic DIP

20-Lead PLCC

20-Pin Plastic DIP

55

90

GAL16V8D-15LJ

GAL16V8D-15LS¹

GAL16V8D-25QP

GAL16V8D-25QJ

GAL16V8D-25LP

20-Lead PLCC

20-Pin SOIC

90

55

20-Pin Plastic DIP

20-Lead PLCC

20-Pin Plastic DIP

20-Lead PLCC

55

90

GAL16V8D-25LJ

GAL16V8D-25LS¹

90

20-Pin SOIC

1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

Package

7.5

10

15

20

25

7

5

130

65

20-Pin Plastic DIP

GAL16V8D-7LPI

20-Lead PLCC

GAL16V8D-7LJI

GAL16V8D-10LPI

GAL16V8D-10LJI

GAL16V8D-15LPI

GAL16V8D-15LJI

GAL16V8D-20QPI

GAL16V8D-20QJI

GAL16V8D-25QPI

GAL16V8D-25QJI

GAL16V8D-25LPI

GAL16V8D-25LJI

10

12

13

15

7

20-Pin Plastic DIP

20-Lead PLCC

10

11

12

20-Pin Plastic DIP

20-Lead PLCC

20-Pin Plastic DIP

20-Lead PLCC

65

20-Pin Plastic DIP

20-Lead PLCC

65

130

20-Pin Plastic DIP

20-Lead PLCC

2

Specifications GAL16V8

Lead-Free Packaging

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

GAL16V8D-3LJN¹

Package

3.5

2.5

3.0

115

Lead-Free 20-Lead PLCC

5

3

7

4

5

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

GAL16V8D-5LJN

GAL16V8D-7LPN

GAL16V8D-7LJN

GAL16V8D-10QPN

GAL16V8D-10QJN

7.5

115

55

10

15

25

10

12

15

7

55

115

55

GAL16V8D-10LPN

GAL16V8D-10LJN

GAL16V8D-15QPN

GAL16V8D-15QJN

GAL16V8D-15LPN

10

12

55

90

GAL16V8D-15LJN

GAL16V8D-25QPN

GAL16V8D-25QJN

GAL16V8D-25LPN

55

90

GAL16V8D-25LJN

1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.

Industrial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)

Ordering #

GAL16V8D-7LJNI

Package

7.5

7

5

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

Lead-Free 20-Lead PLCC

Lead-Free 20-Pin Plastic DIP

130

65

GAL16V8D-7LPNI

GAL16V8D-10LJNI

GAL16V8D-10LPNI

10

7

15

20

25

12

13

15

10

11

12

GAL16V8D-15LJNI

GAL16V8D-15LPNI

GAL16V8D-20QJNI

GAL16V8D-20QPNI

GAL16V8D-25QJNI

GAL16V8D-25QPNI

GAL16V8D-25LJNI

GAL16V8D-25LPNI

65

130

Part Number Description

_

XXXXXXXX XX X XX X

GAL16V8D Device Name

Grade

Blank = Commercial

I = Industrial

Speed (ns)

L = Low Power

Q = Quarter Power

Power

Package P = Plastic DIP

PN = Lead-free Plastic DIP

J = PLCC

JN = Lead-free PLCC

S = SOIC

3

Specifications GAL16V8

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the output logic

macrocell. It should be noted that actual implementation is accom-

plished by development software/hardware and is completely trans-

parent to the user.

PAL Architectures

Emulated by GAL16V8

GAL16V8

Global OLMC Mode

16R8

16R6

16R4

16RP8

16RP6

16RP4

Registered

There are three global OLMC configuration modes possible:

simple, complex, and registered. Details of each of these modes

are illustrated in the following pages. Two global bits, SYN and

AC0, control the mode configuration for all macrocells. The XOR

bit of each macrocell controls the polarity of the output in any of the

three modes, while the AC1 bit of each of the macrocells controls

the input/output configuration. These two global and 16 individ-

ual architecture bits define all possible configurations in a GAL16V8

. The information given on these architecture bits is only to give

a better understanding of the device. Compiler software will trans-

parently set these architecture bits from the pin definitions, so the

user should not need to directly manipulate these architecture bits.

16L8

16H8

16P8

Complex

10L8

12L6

14L4

16L2

10H8

12H6

14H4

16H2

10P8

12P6

14P4

16P2

Simple

The following is a list of the PAL architectures that the GAL16V8

can emulate. It also shows the OLMC mode under which the

GAL16V8 emulates the PAL architecture.

Compiler Support for OLMC

Software compilers support the three different global OLMC modes as clock and output enable, respectively. These pins cannot be con-

as different device types. These device types are listed in the table figured as dedicated inputs in the registered mode.

below. Most compilers have the ability to automatically select the

device type, generally based on the register usage and output In complex mode pin 1 and pin 11 become dedicated inputs and

enable (OE) usage. Register usage on the device forces the soft- use the feedback paths of pin 19 and pin 12 respectively. Because

ware to choose the registered mode. All combinatorial outputs with of this feedback path usage, pin 19 and pin 12 do not have the

OE controlled by the product term will force the software to choose feedback option in this mode.

the complex mode. The software will choose the simple mode only

when all outputs are dedicated combinatorial without OE control. In simple mode all feedback paths of the output pins are routed

The different device types listed in the table can be used to override via the adjacent pins. In doing so, the two inner most pins ( pins

the automatic device selection by the software. For further details, 15 and 16) will not have the feedback option as these pins are

refer to the compiler software manuals.

always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user

must pay special attention to the following restrictions in each mode.

In registered mode pin 1 and pin 11 are permanently configured

Registered

Complex

Simple

Auto Mode Select

ABEL

P16V8R

G16V8MS

GAL16V8_R

"Registered"¹

P16V8R²

P16V8C

G16V8MA

GAL16V8_C7

"Complex"¹

P16V8C²

P16V8AS

G16V8AS

GAL16V8_C8

"Simple"¹

P16V8C²

G16V8AS³

P16V8

G16V8

CUPL

LOG/iC

GAL16V8

GAL16V8A

P16V8A

G16V8

OrCAD-PLD

PLDesigner

TANGO-PLD

G16V8R

G16V8C

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

4

Specifications GAL16V8

Registered Mode

In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-

registered outputs or as I/O functions. sets of the I/O function.

Architecture configurations available in this mode are similar to the Registered outputs have eight product terms per output. I/O's have

common 16R8 and 16RP4 devices with various permutations of seven product terms per output.

polarity, I/O and register placement.

The JEDEC fuse numbers, including the User Electronic Signature

All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown

control pins. Any macrocell can be configured as registered or I/ on the logic diagram on the following page.

O. Up to eight registers or up to eight I/O's are possible in this mode.

CLK

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

D

Q

- Pin 1 controls common CLK for the registered outputs.

XOR

- Pin 11 controls common OE for the registered outputs.

- Pin 1 & Pin 11 are permanently configured as CLK &

OE for registered output configuration.

OE

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

- Pin 1 & Pin 11 are permanently configured as CLK &

XOR

OE for registered output configuration.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

5

Specifications GAL16V8

Registered Mode Logic Diagram

DIP & PLCC Package Pinouts

1

2128

28

PTD

0

4

8

12

16

20

24

0000

0224

OLMC

19

18

17

16

15

14

13

XOR-2048

AC1-2120

2

3

4

5

6

7

8

9

0256

0480

OLMC

XOR-2049

AC1-2121

0512

0736

OLMC

XOR-2050

AC1-2122

0768

0992

OLMC

XOR-2051

AC1-2123

1024

1248

OLMC

XOR-2052

AC1-2124

1280

1504

OLMC

XOR-2053

AC1-2125

1536

1760

OLMC

XOR-2054

AC1-2126

1792

2016

OLMC

12

11

XOR-2055

AC1-2127

OE

2191

SYN-2192

AC0-2193

6

Specifications GAL16V8

Complex Mode

In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the

I/O functions. Registered mode.

Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product

common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and

each macrocell.

11 are always available as data inputs into the AND array.

Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses

outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.

two outer most macrocells (pins 12 & 19) do not have input capa-

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

XOR

- Pin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

XOR

- Pin 12 and Pin 19 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

7

Specifications GAL16V8

Complex Mode Logic Diagram

DIP & PLCC Package Pinouts

1

2128

PTD

0

4

8

12

16

20

24

28

0000

0224

OLMC

19

XOR-2048

AC1-2120

2

3

4

0256

0480

OLMC

18

XOR-2049

AC1-2121

0512

0736

OLMC

17

XOR-2050

AC1-2122

0768

0992

OLMC

16

XOR-2051

AC1-2123

5

6

7

8

1024

1248

OLMC

15

XOR-2052

AC1-2124

1280

1504

OLMC

14

XOR-2053

AC1-2125

1536

1760

OLMC

13

XOR-2054

AC1-2126

1792

2016

OLMC

12

XOR-2055

AC1-2127

9

11

2191

SYN-2192

AC0-2193

8

Specifications GAL16V8

Simple Mode

Pins 1 and 11 are always available as data inputs into the AND

array. The center two macrocells (pins 15 & 16) cannot be used

as input or I/O pins, and are only available as dedicated outputs.

In the Simple mode, macrocells are configured as dedicated inputs

or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the

common 10L8 and 12P6 devices with many permutations of ge-

neric output polarity or input choices.

The JEDEC fuse numbers including the UES fuses and PTD fuses

are shown on the logic diagram.

All outputs in the simple mode have a maximum of eight product

terms that can control the logic. In addition, each output has pro-

grammable polarity.

Combinatorial Output with Feedback Configuration

for Simple Mode

Vcc

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to

this function.

XOR

Combinatorial Output Configuration for Simple Mode

Vcc

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 15 & 16 are permanently configured to this

function.

XOR

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to

this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

9

Specifications GAL16V8

Simple Mode Logic Diagram

DIP & PLCC Package Pinouts

1

2128

0

4

8

12

16

20

24

28

PTD

0000

OLMC

19

18

17

16

15

14

13

XOR-2048

AC1-2120

0224

2

0256

OLMC

XOR-2049

AC1-2121

0480

3

0512

OLMC

XOR-2050

AC1-2122

0736

4

0768

OLMC

XOR-2051

AC1-2123

0992

5

1024

OLMC

XOR-2052

AC1-2124

1248

6

1280

OLMC

XOR-2053

AC1-2125

1504

7

1536

OLMC

XOR-2054

AC1-2126

1760

8

1792

OLMC

12

11

XOR-2055

AC1-2127

2016

9

2191

SYN-2192

AC0-2193

10

Specifications GAL16V8D

(1)

Absolute Maximum Ratings

Recommended Operating Conditions

Supply voltage V_CC...................................... –0.5 to +7V

Input voltage applied .......................... –2.5 to V_CC+1.0V

Off-state output voltage applied ......... –2.5 to V_CC+1.0V

Storage Temperature ................................ –65 to 150°C

Ambient Temperature with

Commercial Devices:

Ambient Temperature (T_A) ............................... 0 to 75°C

Supply voltage (V_CC)

with Respect to Ground ..................... +4.75 to +5.25V

Power Applied ........................................ –55 to 125°C

Industrial Devices:

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress only ratings and functional operation of the device at

these or at any other conditions above those indicated in the

operational sections of this specification is not implied (while

programming, follow the programming specifications).

Ambient Temperature (T_A) ........................... –40 to 85°C

Supply voltage (V_CC)

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.³

MAX. UNITS

VIL

VIH

IIL¹

Input Low Voltage

Vss – 0.5

2.0

—

0.8

Vcc+1

–100

10

V

Input High Voltage

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

Output Low Voltage

0V ≤ VIN ≤ VIL (MAX.)

3.5V ≤ VIN ≤ VCC

μA

V

IIH

—

VOL

VOH

IOL

IOL = MAX. Vin = VIL or VIH

IOH = MAX. Vin = VIL or VIH

L-3/-5 & -7 (Ind. PLCC)

—

0.5

Output High Voltage

2.4

—

V

Low Level Output Current

16

mA

L-7 (Except Ind. PLCC)/-10/-15/-25

Q-10/-15/-20/-25

—

24

IOH

IOS²

High Level Output Current

Output Short Circuit Current

—

–3.2

mA

VCC = 5V VOUT = 0.5V T_A= 25°C

–30

–150

COMMERCIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V

L -3/-5/-7/-10

L-15/-25

—

75

115

90

mA

f^toggle= 15MHz Outputs Open

Q-10/-15/-25

—

45

55

mA

INDUSTRIAL

ICC

Operating Power

Supply Current

VIL = 0.5V VIH = 3.0V

L -7/-10/-15/-25

Q -20/-25

—

75

45

130

65

mA

f^toggle= 15MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C

11

Specifications GAL16V8D

AC Switching Characteristics

Over Recommended Operating Conditions

COM

-5

COM / IND

-7

COM

-3

TEST

COND¹.

DESCRIPTION

PARAMETER

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

tpd

tco

tcf²

A

Input or I/O to Comb. Output

Clock to Output Delay

1

3.5

3

1

5

4

3

1

7.5

5

ns

—

Clock to Feedback Delay

—

2.5

—

3

tsu

th

—

A

Setup Time, Input or Feedback before Clock↑

Hold Time, Input or Feedback after Clock↑

2.5

0

—

3

0

—

5

0

—

ns

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

182

142.8 — 100

MHz

A

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

200

250

—

166

—

125

—

MHz

fmax³

Maximum Clock Frequency with

No Feedback

twh

twl

—

Clock Pulse Duration, High

Clock Pulse Duration, Low

2⁴

—

3⁴

—

4

—

ns

ten

B

Input or I/O to Output Enabled

—

4.5

1

6

1

9

6

ns

OE to Output Enabled

tdis

C

Input or I/O to Output Disabled

—

4.5

1

5

1

9

6

ns

OE to Output Disabled

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

3) Refer to fmax Descriptions section. Characterized but not 100% tested.

4) Characterized but not 100% tested.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

pF

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

8

C_I/O

pF

*Characterized but not 100% tested.

12

SpSepceifcicifaictaiotinosnGs GALA1L61V68VD8

AC Switching Characteristics

Over Recommended Operating Conditions

COM / IND COM / IND

IND

-20

COM / IND

-25

-10

-15

TEST

COND¹.

DESCRIPTION

PARAM.

UNITS

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

tpd

tco

tcf²

tsu

th

A

Input or I/O to Comb. Output

Clock to Output Delay

3

2

10

7

3

2

15

10

8

3

2

20

11

9

3

2

25

12

10

—

ns

—

Clock to Feedback Delay

—

7.5

6

—

12

—

13

—

15

Setup Time, Input or Fdbk before Clk↑

Hold Time, Input or Fdbk after Clk↑

—

A

0

—

0

—

0

—

0

—

ns

Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

66.7

45.5

41.6

37

MHz

fmax³

A

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

71.4

83.3

—

50

—

45.4

50

—

40

—

MHz

Maximum Clock Frequency with

No Feedback

62.5

41.6

twh

twl

ten

t

—

B

Clock Pulse Duration, High

Clock Pulse Duration, Low

Input or I/O to Output Enabled

OE to Output Enabled

6

1

—

10

8

—

15

10

—

18

12

—

20

ns

8

—

B

tdis

t

C

Input or I/O to Output Disabled

OE to Output Disabled

C

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

3) Refer to fmax Descriptions section. Characterized but not 100% tested.

Capacitance (T_A= 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

Input Capacitance

I/O Capacitance

MAXIMUM*

UNITS

TEST CONDITIONS

V_CC= 5.0V, V_I= 2.0V

V_CC= 5.0V, V_I/O= 2.0V

C_I

8

pF

C_I/O

*Characterized but not 100% tested.

13

Specifications GAL16V8

Switching Waveforms

INPUT or

I/O FEEDBACK

VALID INPUT

su

h

t

CLK

INPUT or

I/O FEEDBACK

VALID INPUT

t

co

REGISTERED

OUTPUT

t_pd

COMBINATIONAL

OUTPUT

1/

fmax

(external fdbk)

Combinatorial Output

Registered Output

INPUT or

I/O FEEDBACK

OE

dis

en

t

dis

t

en

t

COMBINATIONAL

OUTPUT

REGISTERED

OUTPUT

Input or I/O to Output Enable/Disable

OE to Output Enable/Disable

wh

wl

t

CLK

1/ max (internal fdbk)

f

CLK

cf

t

su

t

1/ max

(w/o fb)

f

REGISTERED

FEEDBACK

Clock Width

fmax with Feedback

14

Specifications GAL16V8

fmax Descriptions

CLK

LOGIC

ARRAY

REGISTER

LOGIC

ARRAY

t

su

tco

REGISTER

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured

t

cf

pd

tsu and tco.

t

CLK

fmax with Internal Feedback 1/(tsu+tcf)

LOGIC

REGISTER

ARRAY

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The

value of tcf is used primarily when calculating the delay from

clocking a register to a combinatorial output (through registered

feedback), as shown above. For example, the timing from clock

to a combinatorial output is equal to tcf + tpd.

t

su + th

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

Switching Test Conditions

Input Pulse Levels

GAL16V8D-10

GND to 3.0V

2 – 3ns 10% – 90%

(and slower)

+5V

Input Rise

and Fall Times

GAL16V8D-3/-5/-7

1.5ns 10% – 90%

R

1

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

Output Load

FROM OUTPUT (O/Q)

UNDER TEST

See figure at right

TEST POINT

Table 2-0003/16V8

3-state levels are measured 0.5V from

steady-state active level.

C _L*

R

2

GAL16V8D (except -3) Output Load Conditions (see figure

above)

Test Condition

R1

R2

CL

*C_LINCLUDES TEST FIXTURE AND PROBE CAPACITANCE

A

200Ω

∞

390Ω

50pF

5pF

B

Active High

Active Low

Active High

Active Low

200Ω

∞

C

200Ω

5pF

15

Specifications GAL16V8

Switching Test Conditions (Continued)

GAL16V8D-3 Output Load Conditions (see figure at right)

+1.45V

Test Condition

R1

CL

TEST POINT

A

50Ω

35pF

R

1

B

High Z to Active High at 1.9V

High Z to Active Low at 1.0V

Active High to High Z at 1.9V

Active Low to High Z at 1.0V

FROM OUTPUT (O/Q)

UNDER TEST

Z0 = 50Ω, CL = 35pF*

C

*C_Lincludes test fixture and probe capacitance.

Electronic Signature

Output Register Preload

An electronic signature is provided in every GAL16V8 device. It

contains 64 bits of reprogrammable memory that can contain user

defined data. Some uses include user ID codes, revision numbers,

or inventory control. The signature data is always available to the

user independent of the state of the security cell.

When testing state machine designs, all possible states and state

transitions must be verified in the design, not just those required

in the normal machine operations. This is because, in system

operation, certain events occur that may throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

NOTE: The electronic signature is included in checksum calcula-

tions. Changing the electronic signature will alter the checksum.

Security Cell

GAL16V8 devices include circuitry that allows each registered

output to be synchronously set either high or low. Thus, any present

state condition can be forced for test sequencing. If necessary,

approved GAL programmers capable of executing text vectors

perform output register preload automatically.

A security cell is provided in the GAL16V8 devices to prevent un-

authorized copying of the array patterns. Once programmed, this

cell prevents further read access to the functional bits in the device.

This cell can only be erased by re-programming the device, so the

original configuration can never be examined once this cell is pro-

grammed. The Electronic Signature is always available to the user,

regardless of the state of this control cell.

Input Buffers

GAL16V8 devices are designed with TTL level compatible input

buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

devices.

Latch-Up Protection

GAL16V8 devices are designed with an on-board charge pump

to negatively bias the substrate. The negative bias minimizes the

potential of latch-up caused by negative input undershoots. Ad-

ditionally, outputs are designed with n-channel pull-ups instead of

the traditional p-channel pull-ups in order to eliminate latch-up due

to output overshoots.

The GAL16V8 input and I/O pins have built-in active pull-ups. As

a result, unused inputs and I/O's will float to a TTL "high" (logical

"1"). Lattice Semiconductor recommends that all unused inputs

and tri-stated I/O pins be connected to another active input, V_CC

,

or Ground. Doing this will tend to improve noise immunity and re-

duce I_CCfor the device.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-

approved Logic Programmer, available from a number of manu-

facturers. Complete programming of the device takes only a few

seconds. Erasing of the device is transparent to the user, and is

done automatically as part of the programming cycle.

Typical Input Pull-up Characteristic

0

- 2 0

- 4 0

- 6 0

0

1 . 0

2 . 0

3 . 0

4 . 0

5 . 0

Input Voltage (Volts)

16

Specifications GAL16V8

Power-Up Reset

Vcc (min.)

Vcc

t

su

t

wl

CLK

t

pr

Internal Register

Reset to Logic "0"

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Device Pin

Reset to Logic "1"

Circuitry within the GAL16V8 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q

outputs set low after a specified time (tpr, 1μs MAX). As a result,

the state on the registered output pins (if they are enabled) will

always be high on power-up, regardless of the programmed

polarity of the output pins. This feature can greatly simplify state

machine design by providing a known state on power-up. Be-

cause of the asynchronous nature of system power-up, some

conditions must be met to provide a valid power-up reset of the

device. First, the VCC rise must be monotonic. Second, the clock

input must be at static TTL level as shown in the diagram during

power up. The registers will reset within a maximum of tpr time.

As in normal system operation, avoid clocking the device until all

input and feedback path setup times have been met. The clock

must also meet the minimum pulse width requirements.

Input/Output Equivalent Schematics

INPUT/OUTPUT EQUIVALENT SCHEMATICS

Feedback

Vcc

Active Pull-up

Circuit

Active Pull-up

Circuit

Vcc

Tri-State

Control

Vref

Vcc

Vref

ESD

Protection

Circuit

Data

Output

ESD

Protection

Circuit

Feedback

(To Input Buffer)

Typ. Vref = 3.2V

Typical Input

Typical Output

17

Specifications GAL16V8

GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

Normalized Tco vs Vcc

N

ormalized Tpd vs Vcc

Normalized Tsu vs Vcc

1.2

1.1

1

1.2

1.1

1.2

1.1

1

PT H->L

PT L->H

RISE

FALL

PT H->L

PT L->H

1

0.9

0.8

0.9

0.8

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Normalized Tpd vs Temp

Normalized Tco vs Temp

Normalized Tsu vs Temp

1.3

1.2

1.1

1.3

1.2

1.1

1

1.2

1.1

PT H->L

PT L->H

PTH->L

PT L->H

RISE

FALL

1

0.9

0.8

0.7

0.8

0.7

0.8

0.7

-55

-25

0

25

50

75

100

125

-55

-25

0

25

50

75

100

125

-55

-25

0

25

50

75

100 125

Temperature (deg. C)

Delta Tco vs # of Outputs

Switching

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.2

-0.3

RISE

FALL

RISE

FALL

-0.4

1

-0.4

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

14

12

10

14

12

10

RISE

FALL

RISE

FALL

8

6

4

8

6

4

2

0

2

0

-2

0

50

100

150

200

250

300

50

100

150

200

250

300

Output Loading (pF)

18

Specifications GAL16V8

GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams

Vol vs Iol

Voh vs Ioh

3.25

1

0.75

0.5

5

4

3

2

1

0

3

2.75

2.5

0.25

0

10

20

30

40

50

0

1

2

3

4

0

10

20

30

40

Ioh (mA)

Iol (mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq.

1.2

1.15

1.1

1.3

1.2

1.1

1

1.2

1.1

1

1.05

1

0.9

0.95

0.9

0.8

4.50

4.75

5.00

5.25

5.50

-55

-25

0

25

50

75

100

125

0

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

10

0

10

20

30

40

8

6

50

60

70

80

4

2

0

90

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

Vik (V)

Vin (V)

19

Specifications GAL16V8

GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.15

1.1

1.05

1

1.2

1.1

1

1.15

1.1

RISE

FALL

RISE

FALL

RISE

FALL

1.05

1

0.9

0.8

0.95

0.9

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

4.5

4.75

5

5.25

5.5

Supply Voltage (V)

Normalized Tsu vs Temp

Normalized Tpd vs Temp

Normalized Tco vs Temp

1.3

1.2

1.1

1

1.3

1.2

1.1

1

RISE

FALL

RISE

FALL

RISE

FALL

1.2

1.1

1

0.9

0.8

0.9

0.8

-55 -25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs Switching

Delta Tco vs # of Outputs Switching

0

-0.1

-0.2

-0.3

-0.4

-0.5

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

RISE

FALL

RISE

FALL

-0.7

-0.8

-0.9

-1

-0.8

-0.9

-1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

12

8

12

8

RISE

FALL

RISE

FALL

4

0

-4

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Loading (pF)

20

Specifications GAL16V8

GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams

Voh vs Ioh

Vol vs Iol

Voh vs Ioh

4

3

2

1

0

0.5

0.4

0.3

0.2

0.1

0

4

3.5

3

2.5

0

5

10

15

20

25

1

6

11

16

21

26

0.00

1.00

2.00

3.00

4.00

5.00

Ioh (mA)

Iol (mA)

Ioh (mA)

Normalized Icc vs Vcc

Normalized Icc vs Temp

Normalized Icc vs Freq

1.1

1.2

1.1

1

1.15

1.1

1

1.05

1

0.9

0.8

0.9

0.8

0.95

3

3.15

3.3

3.45

3.6

-55

-25

0

25

50

88

100 125

1

15

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Input Clamp (Vik)

Delta Icc vs Vin (1 input)

0

10

20

30

40

50

60

70

80

90

9

8

7

6

5

4

3

2

1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

-3

-2.5

-2

-1.5

-1

-0.5

0

Vin (V)

Vik (V)

21

Specifications GAL16V8

GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Normalized Tsu vs Vcc

Normalized Tco vs Vcc

1.2

1.1

1

1.2

1.1

1

1.2

1.1

1

RISE

FALL

PT H->L

PT L->H

PT H->L

PT L->H

0.9

0.8

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Normalized Tco vs Temp

Normalized Tpd vs Temp

Normalized Tsu vs Temp

1.3

1.2

1.1

1

1.3

1.2

1.1

1

1.3

1.2

1.1

1

RISE

FALL

PT H->L

PT L->H

PT H->L

PT L->H

0.9

0.8

0.7

0.9

0.8

0.7

0.9

0.8

0.7

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

-55

-25

0

25

50

75

100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

Delta Tco vs # of Outputs

Switching

0

-0.2

-0.4

-0.6

-0.8

-1

0

-0.2

-0.4

-0.6

-0.8

-1

RISE

FALL

RISE

FALL

-1.2

1

-1.2

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Number of Outputs Switching

Delta Tpd vs Output Loading

Delta Tco vs Output Loading

12

10

8

12

10

8

RISE

FALL

RISE

FALL

6

4

2

0

-2

-4

-6

-2

-4

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Loading (pF)

22

Specifications GAL16V8

GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams

Voh vs Ioh

Vol vs Iol

5

4

3

2

1

0

4

3.8

3.6

3.4

3.2

3

0.6

0.4

0.2

0

10

20

30

40

50

0

1

2

3

4

0

10

20

30

40

Ioh (mA)

Normalized Icc vs Temp

Ioh (mA)

Iol (mA)

Normalized Icc vs Vcc

Normalized Icc vs Freq.

1.2

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

1.1

1

0.9

0.8

0.7

0.9

0.8

0.9

0.8

4.50

4.75

5.00

5.25

5.50

-55

-25

0

25

50

75

100 125

0

25

50

75

100

Supply Voltage (V)

Temperature (deg. C)

Frequency (MHz)

Delta Icc vs Vin (1 input)

Input Clamp (Vik)

8

6

4

2

0

10

20

30

40

50

60

0

0.5

1

1.5

2

2.5

3

3.5

4

-2

-1.5

-1

-0.5

0

Vin (V)

Vik (V)

23

Specifications GAL16V8

Revision History

Date

Version

16v8_10

16v8_11

Change Summary

-

Previous Lattice release.

August 2006

Updated for lead-free package options.

24

型号:	GAL16V8D-15LPN
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	LATTICE SEMICONDUCTOR CORP
零件包装代码：	DIP
包装说明：	DIP, DIP20,.3
针数：	20
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.7
Is Samacsys：	N
架构：	PAL-TYPE
最大时钟频率：	45.5 MHz
JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e3
长度：	26.162 mm
专用输入次数：	8
I/O 线路数量：	8
输入次数：	18
输出次数：	8
产品条款数：	64
端子数量：	20
最高工作温度：	70 °C
最低工作温度：
组织：	8 DEDICATED INPUTS, 8 I/O
输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	260
电源：	5 V
可编程逻辑类型：	EE PLD
传播延迟：	15 ns
认证状态：	Not Qualified
座面最大高度：	5.334 mm
子类别：	Programmable Logic Devices
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.62 mm
Base Number Matches：	1

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