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  • GM16C550-48图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • GM16C550-48 现货库存
  • 数量5000 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • GM16C550 现货库存
  • 数量6980 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • GM16C550-48
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  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • GM16C550
  • 数量2015 
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  • 深圳市赛尔通科技有限公司

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  • GM16C550
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • GM16C550-48
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • GM16C550
  • 数量37 
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  • 集好芯城

     该会员已使用本站13年以上
  • GM16C550
  • 数量18222 
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  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • GM16C550
  • 数量9000 
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  • 封装DIP 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • GM16C550CJ44
  • 数量13860 
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  • GM16C550图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • GM16C550
  • 数量15280 
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  • GM16C550图
  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • GM16C550
  • 数量92845 
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  • 毅创腾(集团)有限公司

     该会员已使用本站16年以上
  • GM16C550-48
  • 数量568 
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  • GM16C550图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • GM16C550
  • 数量2439 
  • 厂家HYUNDAI 
  • 封装DIP40 
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  • ★只做原装★正品现货★原盒原标★
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  • GM16C550-40P图
  • 首天国际(深圳)集团有限公司

     该会员已使用本站17年以上
  • GM16C550-40P
  • 数量5000 
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  • GM16C55040图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • GM16C55040
  • 数量10438 
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  • GM16C550(ST16C550C图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GM16C550(ST16C550C
  • 数量65000 
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  • GM16C550图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GM16C550
  • 数量12500 
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  • GM16C550-40P图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • GM16C550-40P
  • 数量5000 
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  • GM16C550(ST16C550CJ)图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • GM16C550(ST16C550CJ)
  • 数量8639 
  • 厂家√ 欧美㊣品 
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  • GM16C550-46图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • GM16C550-46
  • 数量6500 
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  • GM16C550图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • GM16C550
  • 数量68000 
  • 厂家LGS 
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  • 批号22+ 
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  • GM16C550图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • GM16C550
  • 数量6800 
  • 厂家HYNIX(海力士) 
  • 封装DIP-40 
  • 批号24+ 
  • 真实库存全新原装正品!代理此型号
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  • GM16C550图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • GM16C550
  • 数量5000 
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  • 批号16+ 
  • 百分百原装正品,现货库存
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  • GM16C550CJ44图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • GM16C550CJ44
  • 数量12603 
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • GM16C550
  • 数量37076 
  • 厂家LGS 
  • 封装PLCC44 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
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  • GM16C550图
  • 深圳市浩兴林电子有限公司

     该会员已使用本站16年以上
  • GM16C550
  • 数量23500 
  • 厂家LGS 
  • 封装PLCC44 
  • 批号2017+ 
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  • GM16C550图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • GM16C550
  • 数量5500 
  • 厂家HYUNDAI 
  • 封装PLCC44 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • GM16C550图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • GM16C550
  • 数量30000 
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  • GM16C550-46图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • GM16C550-46
  • 数量260 
  • 厂家GENESIS 
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  • GM16C550.图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • GM16C550.
  • 数量8650 
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  • GM16C550-40图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • GM16C550-40
  • 数量27779 
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  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • GM16C550
  • 数量5000 
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  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • GM16C550
  • 数量99000 
  • 厂家LGS 
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  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • GM16C550
  • 数量5500 
  • 厂家LGS 
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产品型号GM16C550的概述

芯片GM16C550的概述 GM16C550是一款广泛应用于计算机通信、嵌入式系统及自动化设备中的多功能串行通讯芯片。它是基于16C550标准设计的,具备高性能的数据传输能力,支持双通道串口设计。该芯片通过其硬件和软件的灵活性,能够满足多种应用需求,方便用户在各种系统中进行串行数据交换。 GM16C550主要集成了多种功能,包括异步串口、FIFO缓存、可编程分频器等。它的FIFO(先进先出)队列结构能够有效缓解CPU的负担,提高数据传输的可靠性。随着通信技术的发展,GM16C550逐渐成为多种设备,如工业控制、医疗设备、POS机等的核心组件。 芯片GM16C550的详细参数 GM16C550的典型参数如下: - 工作电压范围:4.5V至5.5V - 工作频率:高达16MHz - 数据位:5、6、7或8位可选 - 停止位:1或2位可选 - 奇偶校验:无、单奇校验或双奇校验可选 - FIF...

产品型号GM16C550的Datasheet PDF文件预览

GM16C550  
GM16C550  
ASYNCHRONOUS COMMUNICATIONS  
ELEMENT WITH FIFOs  
Descriptions  
Features  
The GM16C550 is an asynchronous communi-  
cations element (ACE) that is functionally  
equivalent to the GM16C450, and addition-ally  
incorporates a 16byte FIFOs are available on both  
the transmitter and receiver, and can be activated by  
placing the device in the FIFO mode. After a reset,  
the registers of the GM16C550 are identical to those  
of the GM16C450.  
l
l
Fully compatible with GM16C450.  
Modem controm signals include  
,
,
CTS RTS  
DSR , DTR , RI and -DCD .  
Programmable serial characteristics:  
5-, 6-, 7- or 8-bit characters  
— Even-, odd-, or no-parity bit generation and  
detection  
1-, 11/2- or 2-stop bit generation  
l
The UART performs serial-to-parallel conver- sion  
on data characters received from a peri-pheral  
— Baud rate generation (DC to 256K baud)  
l
l
16 byte FIFO reduces CPU interrupts.  
Independent control of transmit, receive, line  
status, data set interrupts, FIFOs.  
device or  
a MODEM, and parallel-to- serial  
conversion on data characters received from the  
CPU. The CPU can read the com- plete status of l Full status reporting capabilities  
the UART at any time during  
operation. Status information reported includes the  
the functional  
l
Three-state, TTL drive capabilities for bi-  
derectional data bus and control bus.  
40DIP/44PLCC  
type and condition of  
being performed by  
the transfer operations  
the UART, as well as any  
l
error conditions (parity, overrun, framing, or break  
interrupt).  
Pin Configulation  
D0  
VCC  
D1  
D2  
D3  
RI  
DCD  
DSR  
D5  
D6  
D7  
RCLK  
SIN  
N.C.  
MR  
OUT1  
DTR  
D4  
CTS  
MR  
OUT1  
D5  
D6  
RTS  
OUT2  
N.C.  
INTRPT  
D7  
DTR  
RCLK  
RTS  
SOUT  
CS0  
CS1  
SIN  
SOUT  
CS0  
RXRDY  
A0  
A1  
OUT2  
INTRPT  
CS2  
BAUDQUT  
RXRDY  
A0  
A2  
CS1  
A1  
CS2  
A2  
BAUDQUT  
XTAL1  
ADS  
TXRDY  
XTAL2  
DDIS  
DOSTR  
DOSTR  
DISTR  
VSS  
DISTR  
1
GM16C550  
Absolute Maximum Ratings  
Temperature under Bias  
Storage Temperature  
All Input or Output Voltages  
with respect to VSS  
Power Dissipation  
°
0 C  
to +  
°
70 C  
Note: Maximum ratings indicates limits beyond which  
permanent damage may occur. Continuous opera-tion  
at these limits is not intended and should be limited  
to those conditions specified under DC electrical  
characteristics.  
-
°
to +  
°
150 C  
65 C  
- 0.5V to + 7.0V  
500 mW  
DC Electrical Characteristics  
T
= 0°C TO +  
, V  
= 5V ± 5% , V = 0V unless otherwise specified  
70°C  
A
CC SS  
Symbol  
VILX  
Parameter  
Min  
Max  
Units  
Conditions  
Clock Input Low Voltage  
Clock Input High Voltage  
-0.5  
2.0  
0.8  
V
VIHX  
VCC  
V
V
V
V
V
VIL  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
-0.5  
2.2  
0.8  
VIH  
VOL  
VOH  
VCC  
0.4  
IOL =1.6 mA on all, Note 1  
IOH = - 1.0 mA , Note 1  
2.4  
Average Power Supply  
10  
(Note 2)  
VCC =5.25  
output SIN DSR, DCD, CTS  
, No loads on  
V
ICC (AV)  
mA  
Current( VCC  
)
IIL  
Input Leakage  
±
±
mA  
mA  
10  
VCC =5.25  
All other pins floating.  
VIN = 0V , 5.25  
, V =0  
.
V
V
SS  
V
ICL  
Clock Leakage  
3-State Leakage  
10  
VCC =5.25 V , GND =0 V .  
VOUT = 0V ,5.25  
1) Chip Deselected  
V
IOZ  
mA  
±20  
2) Write mode, chip selected  
VILMR  
VIHMR  
MR Schmitt VIL  
MR Schmitt VIH  
0.8  
V
V
2.2  
Note 1. Does not apply to XOUT.  
Note 2. Ta=25C  
Capitance TA = 25°C , VCC =VSS = 0V  
Symbol  
CXIN  
CXOUT  
CIN  
Parameter  
Clock Input Capitance  
Clock Output Capitance  
Input Capitance  
Min  
Tye  
Max  
15 20  
20 30  
10  
10 20  
Units  
pF  
pF  
pF  
pF  
Conditions  
fC = 1MHz  
Unmeasured pins  
Returned to VSS  
6
COUT  
Output Capitance  
2
GM16C550  
AC Characteristics TA = 0°C to + 70°C,VCC = 5V ± 5%  
Symbol  
Parameter  
Min  
Max  
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Conditions  
t
Address Srobe Width  
ADS  
AH  
60  
t
t
t
t
t
t
t
t
t
t
t
t
r
t
t
t
t
t
t
t
t
t
t
t
Address Hold Time  
0
30  
60  
30  
0
AR  
RD,RD Delay from Address  
Address Setup Time  
Note 1  
Note 1  
AS  
WR, WR Delay from Select  
Chip Select Hold Time  
Chip Select Setup time  
RD,RD Delay from Chip Select  
WR,WR Delay from Select  
Data Hold Time  
AW  
CH  
CS  
60  
30  
30  
30  
30  
0
Note 1  
Note 1  
CSR  
CSW  
DH  
Date Setup Time  
DS  
HZ  
RD,RD to Floating Data Delay  
Master Reset Pulse Width  
Address Hold Time from RD,RD  
Read Cycle Delay  
100 pF loading, Note 3  
Note 1  
100  
MR  
RA  
5
20  
125  
20  
125  
RC  
Chip Select Hold Time from  
RD, RD Strobe Width  
Note 1  
RCS  
RD  
RD, RD  
RDD  
RVD  
WA  
WC  
WCA  
WR  
XH  
to Driver Enable/Disable  
100 pF loading, Note 3  
100 pF loading,  
Note 1  
RD, RD  
60  
Delay from - RD, RD to Data  
Address Hold Time from WR,WR  
Write Cycle Delay  
125  
20  
150  
20  
Chip Select Hold Time from WR,WR  
WR,WR Strobe Width  
Note 1  
100  
55  
Duration of clock High Pulse  
External Clock (8.0 MHz Max.)  
Exrternal Clock (8.9 MHz Max.)  
Note 4  
XL  
Duration of clock Low Pulse  
55  
t
t
t
RC  
Read Cycle=  
Write Cycle=  
AR+ RD+ RC  
280  
280  
t
t
t
WC  
AW+ WR+ WC  
Baud Generator  
N
t BHD  
t BLD  
t HW  
t LW  
Baud Divisor  
1
216 -1  
175  
Baud Output Positive Edge Delay  
Baud Output Negative Edge Delay  
Baud Output Up Time  
ns  
ns  
ns  
ns  
100 pF load  
175  
100 pF load  
75  
f X = 8.0MHz , +2, 100 pF load  
f X = 8.0MHz , +2, 100 pF load  
Baud Output Down Time  
100  
3
GM16C550  
AC Characteristics T = 0°C to + ° , V = 5V ± 5%  
70 C  
CC  
A
Symbol  
Parameter  
Min Max  
Units  
Conditions  
Receiver  
Delay from RD,RD (RD RBR/ or  
RD LSR) to Reset Interupt  
t
1
2
1
ms  
100 pF load  
RINT  
t
Delay from RCLK to Sample Time  
ms  
SCD  
RCLK  
Cycles  
t
Delay from Stop to Set Interrupt  
Note 2  
SINT  
Transmitter  
Delay from WR,WR (WR THR)  
To Reset Interrupt  
t
HR  
175  
250  
ns  
ns  
100 pF load  
100 pF load  
Delay from RD,RD (RD IIR)  
To Reset Interrupt (THRE)  
Delay from Initial INTR Reset  
To Transmit Start  
t
IR  
Baudout  
Cycles  
Baudout  
Cycles  
Baudout  
Cycles  
Baudout  
Cycles  
ns  
t
8
16  
8
24  
24  
8
IRS  
t
Delay from Initial Write to Interrupt  
Delay from Stop to Interrupt (THRE)  
Note 5  
Note 5  
SI  
t
STI  
t
Delay from Start to TXRDY Active  
Delay from Write to TXRDY inactive  
8
100 pF load  
100 pF load  
SXV  
t
195  
WXI  
Modem Control  
t
Delay from WR,WR (WR MCR) to Output  
200  
250  
250  
ns  
ns  
ns  
100 pF load  
100 pF load  
100 pF load  
MDO  
Delay to Reset Interrupt from RD,RD  
(RD MSR)  
t
RIM  
t
Delay to Set Interrupt from MODEM Input  
SIM  
Notes  
1. Applicable only when  
is tied low.  
ADS  
2. In the FIFO mode (FCRO=1) the trigger level interrupts, the receiver data available indication, the active RXRDY indica-tion  
and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first  
byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes  
inactive. Timeout interrupt is delayed 8 RCLKs.  
3. Change and discharge time is determined by VOL, VOH and the external loading.  
4.In FIFO mode RC=425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identifica-  
register or line status register).  
tion  
5. This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active  
(See FIFO Interrupt Mode Operatione)  
4
GM16C550  
Timing Waveforms (All timings are referenced to valid 0 and valid)  
External Clock Input (8.0 MHz Max.)  
AT Test Points  
t
XH  
2.4V  
2.2V  
(Note 2)  
0.8V  
2.4V  
XIN  
2.2V  
0.8V  
(Note 1)  
0.4V  
0.4V  
t
XL  
Note 1: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing.  
Note 2: The 2.2V and 0.8V levels are the voltages at which the timing tests are made.  
BAUDOUT Timing  
N
XIN  
t
BHD  
t
t
t
HW  
t
BLD  
BAUD OUT  
LW  
t
(¸ 1)  
BHD  
t
BLD  
LW  
BAUD OUT  
(¸ 2)  
t
t
t
HW  
HW  
LW  
t
t
BHD  
BLD  
BLD  
BAUD OUT  
(¸ 3)  
t
t
BHD  
HW = (N - 2)XIN CYCLES  
t
BAUD OUT  
(¸ N.N > 3)  
t
=2 XIN CTLES  
LW  
5
GM16C550  
Timing Waveforms (Continued)  
Write Cycle  
tADS  
ADS  
tAS  
tAH  
tCH  
A2,A1,A0  
VALID  
tCS  
tWA*  
CS2 ,CS1,CS0  
VALID  
tSCW*  
tAW*  
tCSW*  
tWC  
WC  
tWR  
WR ,WR  
RD ,RD  
ACTIVE  
ACTIVE  
OR  
ACTIVE  
tDS  
tDH  
DATA  
D0- D7  
VALID DATA  
*Applicable Only When ADS is Tied Low.  
Read Cycle  
tADS  
ADS  
tAS  
tAH  
VALID  
A2,A1,A0  
tCS  
tCH  
tRA*  
VALID  
CS2 ,CS1,CS0  
tCSR*  
tAR*  
tRCS*  
RC  
tRD  
tRC  
ACTIVE  
ACTIVE  
OR  
ACTIVE  
RD ,RD  
WR ,WR  
tRDD  
tHZ  
tRDD  
DDIS  
tRVD  
DATA  
D0- D7  
VALID  
DATA  
*Applicable Only When  
is Tied Low.  
ADS  
6
GM16C550  
Receiver Timing  
RCKK  
8 CLKS  
SAMPLE CLK  
SIN  
RECEIVER  
INPUT  
START  
DATA BITS(5-8)  
STOP  
PARITY  
DATA  
SAMPLE  
CLK  
tSINT  
INTERRUPT  
(DATA READY OR  
RCVR ERR  
tRIN  
DISTR /DOSTR  
ACTIVE  
(READ REC  
DATA BUFFER  
OR RDLSR)  
Transmitter Timing  
START  
START  
SERIAL OUT  
(SOUT)  
DATA(5-  
PARITY  
STOP(1  
tiRS  
tSTI  
INTERRUPT  
(THRE)  
tMR  
tHR  
tSI  
DISTR/DISTR  
(WR, THR)  
tIR  
DISTR/DISTR  
(RD IIR)  
MODEM Comtrol Timing  
DISTR/DISTR  
(WR MCR)  
tMDO  
tMDO  
RTS. DTR  
OUT1. OUT2  
CTS. DSR. DCD  
INTERRUPT  
tSIM  
tRIM  
tSIM  
tRIM  
tSIM  
DISTR/DISTR  
(RD MSR)  
RI  
Note 1: See Write Cycle Timing  
Note 2: See Read Cycle Timing  
7
GM16C550  
Timing Waveforms (continued)  
RAVR FIFO First byte (This Sets RDR)  
SIN  
DATA (5-6)  
STOP  
SAMPLE CLOCK  
FIFO OR  
ABOVE TRIGGER LEVEL  
TRIGGER LEVEL  
INTERRUPT  
(FCR6,7 = 0.0)  
FIFO BELOW  
TRIGGER LEVEL  
NOTE 2  
tSINT  
tRINT  
LSI INTERRUPT  
tRINT  
RD, RD  
ACTIVE  
(RDLS  
RD, RD  
(RDRBR)  
ACTIVE  
RCVR FIFO Byte Other Than the First Byte (RDR is Already Set)  
SIN  
SAMPLE CLOCK  
FIFO AT OR  
ABOVE TRIGGER LEVEL  
TIMEOUT OR  
TRIGGER LEVEL  
INTERRUPT  
(FIFO BELOW  
TRIGGER LEVEL)  
NOTE 2  
tSINT  
tRINT  
TOP BYTE OF FIFO  
tSINT  
LSI INTERRUPT  
tRINT  
RD, RD  
(RDLSR)  
ACTIVE  
RD, RD  
(RDRBR)  
ACTIVE  
ACTIVE  
PREVIOUS BYTE  
READ FROM FIFO  
Receiver Ready (pin 29) FCRO = 0 or FCRO = 1 and FCRO = 3 (Mode 0)  
RD, RD  
(RDRBR)  
ACTIVE  
NOTE 1  
SIN  
STOP  
(FIRST BYTE)  
SAMPLE CLK  
RXRDY  
tSINT  
tRINT  
NOTE 2  
Note 1: This is the reading of the last byte in the FIFO  
Note 2: If FCRO =1, then Tsint = 3 RCLKs. For a timeout tSINT = 0 RCLKs.  
8
GM16C550  
Timing waveforms(Continued)  
Receiver Ready (pin 29) FCRO = 0 or FCRO = 1 and FCRO = 1 (Mode 1)  
RD, RD  
(RDRBR)  
ACTIVE  
NOTE 1  
SIN  
STOP  
(FIRST  
SAMPLE CLK  
RXRDY  
tSINT  
tRINT  
NOTE 2  
Note 1 : This si the reading of the last byte in the FIFO  
Note 2 : If FCRO = 1, Tsint = 3 RCLKs.  
RCVR FIFO Byte Other Than First Byte (RDR is Already Set)  
WR, WR  
(WRTHR)  
BYTE 1  
DATA  
SOUT  
PARITY  
START  
STOP  
TXRDY  
tWXI  
tSXA  
Transmitter Ready (pin 24) FCRO = 1 and FCR = 1 (Mode 1)  
WR WR  
(WRTHR)  
BYTE 16  
SOUT  
START  
PARITY  
tWXI  
DATA  
STOP  
FIFO FULL  
TXRDY  
tSXA  
9
GM16C550  
INTERNAL BLOCK DIAGRAM  
RECEIVER  
FIFO  
INTERNAL  
DATA BUS  
DATA  
BUS  
BUFFER  
RECEIVER  
BUFFER  
REGISTER  
RECEIVER  
SHIFT  
REGISTER  
(10)  
SIN  
D7-D0  
(1-8)  
RECEIVER  
TIMING  
&
LINE  
CONTROL  
REGISTER  
(9)  
RCLK  
(28)  
CONTROL  
(27)  
(26)  
DIVIOR  
LATCH(LS)  
(12)  
(13)  
(15)  
BAUD  
GENERATOR  
CSO  
CS1  
CS2  
ASD  
BAUDIUT  
DIVISOR  
LATCH(MS)  
(14)  
(25)  
(35)  
(22)  
(21)  
(19)  
18  
RECEIVER  
TIMING  
&
SELENT  
&
CONTROL  
LOGIC  
MR  
RD  
LINE  
STATUS  
REGISTER  
CONTROL  
RD  
WR  
WR  
TRANSMITTER  
FIFO  
(23)  
(24)  
(16)  
TRANSTMTTER  
HOLDING  
REGISTER  
TRANSTMTTER  
HOLDING  
REGISTER  
DDIS  
TXRDY  
XIN  
(11)  
SOUT  
(32)  
(36)  
RTS  
CTS  
DTR  
DSR  
(17)  
(29)  
MODEM  
CONTROL  
REGISTER  
XOUT  
RXRDY  
(33)  
(37)  
(38)  
(39)  
(34)  
(31)  
MONDEM  
CONTROL  
LOGIC  
MODEM  
STATUS  
REGISTER  
DCD  
R1  
(40)  
+5v  
GND  
POWER  
SUPPLY  
(20)  
OUT1  
OUT2  
{
INTERRUPT  
CONTROL  
LOGIC  
INTERRUPT  
ENABLE  
REGISTER  
(30)  
INTR  
INTERRUPT  
ID  
REGISER  
FIFO  
CONTROL  
REGISTER  
10  
GM16C550  
Register Address  
DLAB A2  
Pin Descriptions  
The following describes the function of all UART pins. Some  
of these descriptions reference internal circuits.  
In the following descriptions, a low represents a logic 0 (0V  
nominal) and a high represents a logic 1 (+2.4V nominal).  
A1  
0
A0  
0
Register  
0
0
Receiver Buffer (read)  
Transmitter Holding  
Register (Write)  
Interrupt Enable  
Interrupt Identification (read)  
FIFO Control (Write)  
Line Control  
MODEM Control  
Line Status  
MODEM Status  
Scratch  
Divisor Latch  
0
×
×
×
×
×
×
×
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
INPUT SIGNALS  
Chip Select (CS0, CS1,  
) Pins 12-14: When CS0 and  
CS2  
is low, the chip is selected. This  
CS1 are high and  
CS2  
enable communication between the UART and the CPU. The  
positive edge of an active Address Strobe signal latches the  
decoded chip select signals, completing chip selection. If  
ADS is always low, valid chip selects should stabilize  
according to the CSW parameter.  
(least significant byte)  
Divisor Latch  
(most significant byte)  
Read (RD, RD ), Pins 22 and 21: When Rd is high or RD is  
low while the chip selected, the CPR can read status information  
or data from the selected UART register.  
0
0
1
Serial Input (SIN), Pin 10: Serial data input from the  
Note: Only an active RD or RD input is required to transfer  
data from the UART during a read operation. Therefore  
tie either the RD input permanently low or the RD input  
permanently high, when it is not used.  
communications link (peripheral device, MODEM, or data set).  
Clear to Send (  
), Pin 36: When low, this indicates that  
CTS  
the MODEM or data set is ready to exchange data. The CTS  
signal is a MODEM status input whose conditions can be  
tested by the CPU reading bit 4 (CTS) of the MODEM Status  
Register. Bit 4 is the complement of the CTS signal. Bit 0  
(DCTS) of the MODEM Status Register indicates whether the  
Write (WR, WR ), Pin 19 and 18: When WR is high or  
is low while the chip selected, the CPU can write  
WR  
control words or data into the selected UART register.  
Note: Only an active WR or input is required to transfer  
WR  
input has changed state since the previous reading of  
CTS  
the MODEM Status Register.  
data to the UART during a write operation. Therefore, tie  
either the WR input permanently low or the WR input  
permanently high, when it is not used.  
has no effect on the  
CTS  
Transmitter.  
Note: Whenever the CTS bit of the MODEM Status Register  
changes state, an interrupt is generated if the  
MODEM Status Interrupt is enabled.  
Address Strobe (  
ADS  
active Address Strobe (  
), Pin 25: The positive edge of an  
) signal latches the Register  
ADS  
Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals.  
Note: An active ADS input is required when the Register  
Select (A0, A1, A2) signals are not stable for the  
duration of a read or a write operation. If not required, tie  
the ADS input permanently low.  
Data Set Ready (  
), Pin 37: When low, this indicates that  
DSR  
the MODEM or data set is ready to establish the  
communications link with the UART. The signal is a  
DSR  
MODEM status input whose condition can be tested by the CPU  
reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the  
complement of the  
signal. Bit 1 (DDSR) of the  
DSR  
Register Select (A0, A1, A2), Pins 26-28: Address signals  
connected to these 3 inputs select a UART register for the CPU  
to read from or write to during data transfer. A table of  
registers and addresses is shown below. Note that the state of  
the Divisor Latch Access Bit (DLAB), which is the most  
significant bit of the Line Control Register, affects the  
selection of certain UART registers. The DLAB must be set  
high by the system software to access the Baud Generator  
Divisor Latches.  
MODEM Status Register indicates whether the DSR input  
has changed state since the previous reading of the MODEM  
Status Register.  
Note: Whenever the DSR bit of the MODEM Status Register  
changes state, an interrupt is generated if the  
MODEM Status interrupt is enabled.  
Data Carrier Detect (  
), Pin 38: When low, indicates  
DCD  
that the data carrier has been detected by the MODEM or data  
set. The DCD signal is a MODEM status input whose  
condition can be tested by the Register. Bit 7 is the  
complement of the DCD signal. Bit 3 (DDCD) of the  
Master Reset (MR), Pin 35: When this input is high it clears  
all the registers (except the Receiver Buffer, Transmitter  
Holding, and Divisor Latches), and the control logic of the  
UART. The state of various output signals (SOUT, INTR,  
MODEM Status Register indicates whether the  
input  
DCD  
has changed state since the previous reading of the MODEM  
Status Register. has no effect on the receiver.  
,
,
, DTR) are affected by an active MR  
OUT1 OUT2 RTS  
DCD  
input (Refer to Table 1). This input is buffered with a TTL-  
compatible Schmitt Trigger with 0.5V typical hysteresis.  
Note: Whenever the DCD bit of the MODEM Status Register  
changes state, an interrupt is generated if the  
MODEM Status Interrupt is enabled.  
Receiver Clock (RCLK), Pin 9: This input is the 16 X baud  
rate clock for the receiver section of the chip.  
Ring Indicator ( RI ), Pin 39: When low, this indicates  
that a telephone ringing signal is received by the MODEM  
or data set. The RI signal is a MODEM status input  
whose condition can be tested by the CPU reading bit 6  
( RI ) of the MODEM Status Register. Bit 6is the  
complement of the RI signal. Bit 2 (TERI) of the MODEM  
11  
GM16C550  
Status Register indicates whether the RI input signal  
has changed from a low to a high state since the previous  
reading of the MODEM Status Register  
Note : Whenever the RI bit of the MODEM Status Regi-  
ster changes from a high to a low state, an inter-  
rupt is generated if the MODEM Status Interrupt  
is enabled.  
RXRDY Mode 1: In the FIFO Mode (FCR0 = 1) when the  
FRC3 = 1 and the trigger level or the timeout has been  
reached, the RXRDY pin will go low active. Once it is  
activated it will go inactive when there are no more characters  
in the FIFO or holding register.  
TXRDY Mode 0: in the GM16C450 Mode (FCR0 = 0) or in  
the FIFO Mode (FCR = 1, FCR3 = 0) and there are no  
characters in the XMIT FIFO or XMIT hold register, the  
TXRDY pin(24) will be low active. Once it is activated the  
TXRDY pin will go inactive after the first character is loaded  
into the XMIT FIFO or holding register.  
Vcc, Pin 40 : +5V supply.  
Vss, Pin 20 : Ground(0V) reference.  
OUTPUT SIGNALS  
Data Terminal Ready ( DTR ), Pin 33: When low, this  
informs the MODEM or data set that the UART is ready to  
establish communications link. The DTR output signal  
can be set to an active low by programming bit 0 (DTR) of  
the MODEM Control Register to high level. A Master  
Reset operation sets this signal to its inactive (high) state.  
Loop mode operation holds this signal in its inactive state.  
TXRDY Mode 1: In the FIFO Mode (FCR0 = 1) when  
FCR3 = 1 and there is at least one unfilled position in the  
XMIT FIFO, it will go low active. This pin will become  
inactive when the XMIT FIFO is completely full.  
Driver Disable (DDIS), Pin 23: this goes low whenever  
the CPU is reading data from the UART. It can disable or  
control the direction of a data bus transceiver between the  
CPU and the UART.  
Request to Send (  
), Pin 32: When low, this informs  
RTS  
the MODEM and data set that the UART is ready to  
exchange data. The output signal can be set to an  
RTS  
active low by programming bit 1 (RTS) of the MODEM  
Control Register. A Master Reset operation sets this signal  
to its inactive state. Loop node operation holds this signal  
in its inactive state.  
Baud Out (  
), Pin 23: This is the 16X clock  
BAUDOUT  
signal from the transmitter section of the UART. The clock  
rate is equal to the main reference oscillator frequency  
divided by the specified divisor in the Baud Generator  
Divisor Latches. The  
may also be used for  
BAUDOUT  
Output 1 (  
), Pin 34: This user-designed out-put  
the receiver section by tying this output to the RCLK input  
OUT1  
can be set to an active low by programming bit 2 (OUT1)  
of the MODEM Control Register to a high level. A Master  
Reset operation sets this signal to its inactive state. Loop  
Mode operation holds this signal to its inactive state.  
of the chip.  
Interrupt (INTR), Pin 30: This pin goes high when-ever  
any one of the following interrupt types has an active high  
cognition and is enabled via the IER; Receiver Error Flag;  
Received Data Avail-able; timeout (FIFO Mode only);  
Transmitter Holding Register Empty; and MODEM Status,  
The INTR signal is reset low upon the appropriate  
interrupt service or a Master Reset operation.  
Output 2 (  
), Pin 31: This user-designated output  
OUT2  
can be set to an active low by programming bit 3 (OUT2)  
of the MODEM Control Register to a high level. A Master  
Reset operation sets this signal to its inactive (high) state.  
Loop mode operation holds this signal to its inactive state.  
Serial output (SOUT), Pin 11: Composite serial data  
output to the communications link (peripheral. MODEM  
or data set). The SOUT signal is set to the Marking (logic  
1) state upon a Master Reset operation.  
TXRDY, RXRDY, Pin 24, 29: Transmitter and Receiver  
DMA signaling is available through two pins (24 and 29).  
When operating in the FIFO mode, one of two types DMA  
signaling per pin can be selected via FCR3, When  
operating as in the GM16C16450 Mode., only DMA Mode  
0 is allowed. Mode 0 supports single transfer DMA where  
a transfer is made between CPU bus cycles. Mode 1  
supports multi-transfer DMA where multiple transfers ard  
made continuously until the RCVR FIFO has been  
emptied or the XMIT FIFO has been filled.  
INPUT / OUTPUT SIGNALS  
Data (D7-D0) Bus, Pin 1-8: This bus comprises eight  
TRI-state input/output lines. The bus provides bi-  
directional communications between the UART and the  
CPU, Data, control words. And status information are  
transferred via the D7-D0 Data Bus.  
RXRDY Mode 0: When in the GM16C450 Mode (FCR0 =  
0) or in the FIFO Mode (FCRO = 1, RCR3 = 0) and there is  
at least 1 character in the RCVR FIFO of RCVR holding  
register, the RXRDY pin (29) will be low active. Once it is  
activated the RXRCY pin will go inactive when there are no  
more characters in the FIFO of holding register.  
External Clock Input/Output (XIN, XOUT), Pins 16 and  
17: These two pins connect the main timing reference (crystal  
or signal clock) to the UART.  
12  
GM16C550  
TABLE I. UART Reset Configuration  
Register / Signal  
Reset Control  
Reset State  
Interrupt Enable Register  
Interrupt Identification Register  
FIFO Control  
Line Control Register  
MODEM Control Register  
Line status Register  
MODEM Status Register  
SOUT  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
Read LSR/MR  
Read RBR/MR  
0000 0000 (Note 1)  
0000 0001  
0000 0000  
0000 0000  
0000 0000  
0110 0000  
xxxx 0000 (Note 2)  
High  
INTR (RCVR Errs)  
INTR (RCVR Data Ready)  
INTR (THRE)  
Low  
Low  
Low  
Low  
High  
High  
Read IIR/Write THR/MR  
Read MSR/MR  
INTR (Modem Status Changes)  
OUT2  
RTS  
Master Reset  
Master Reset  
Master Reset  
Master Reset  
MR/RCR1-FCR0/ FCR0  
MR/RCR1-FCR0/ FCR0  
High  
High  
All Bits Low  
All Bits Low  
DTR  
OUT1  
RCVR FIFO  
XMIT FIFO  
Note 1 : Boldface bits are Permanently low.  
Note 2 : Bits 7-4 are driven by the input signals.  
13  
GM16C550  
14  
GM16C550  
are summed).  
Registers  
Bit 4: This bit is the Even Parity Select bit. When bit 3 is  
a logic 1 and bit 4 is a logic 0, and odd number of logic  
1s is transmitted or checked in the data word bits and  
Parity bit. When bit 3is a logic 1 and it 4 is a logic 1, an  
even number of logic 1s is transmitted or checked.  
The system programmer may be Access any of the  
UART registers summarized in Table II via the CPU.  
These registers control UART operations including  
transmission and reception of data. Each register bit in  
Table II has its name and reset state shown.  
Bit 5: This bit is the Stick Parity bit. When bit3, 4 and 5  
are logic 1 the Parity bit is transmitted and checked as a  
logic 0. If bit 3 and 5 are 1 and bit 4 is a logic 0 then the  
Parity bit is transmitted and checked as a logic 1. If bit  
5 is a logic 0 Stick Parity is disabled.  
LINE CONTROL REGISTER  
The system programmer specifies the format of the  
asynchronous data communications exchange and set the  
Divisor Latch Access bit via the Line Control Register  
(LCR). The programmer can also read the contents of the  
Line Control Register. The read capability simplifies  
system programming and eliminates the need for  
separate storage in system memory of the LCR. Details  
on each bit follow:  
Bit 6: This bit is the Break Control bit. It causes a break  
condition to be transmitted to the received UART. When  
it is set to logic 1, The serial output (SOUT) is forced to  
the Spacing (logic 0) state. The break is disabled by  
setting bit 6 to a logic 0. The Break Control bit acts only  
on SOUT and has no effect on the transmitted logic.  
Bit 0 and 1: These two bits specify the number of bits  
in each transmitted or received serial character. The  
encoding of bits 0 and 1 is as follows.  
Note : This feature enables the CPU to alert a terminal in  
during the break. The Transmitter can be used as a  
character timer to accurately establish the break duration.  
a computer communications system.  
Bit 1  
Bit 0  
Character Length  
5 Bits  
0
0
1
1
0
1
0
1
6 Bits  
7 Bits  
8 Bits  
If the following sequence is followed. no  
erroneous or extraneous characters will be  
transmitted because of the break.  
Bit 2: This bit specifies the number of Stop bits  
transmitted and received in each serial character. If bit 2  
is a logic 0, one Stop bit is generated in the transmitted  
data. If Bit 2 is a logic 1 when a 5-bit word length is  
selected via bits 0 and 1, one and a half Stop bits are  
generated. If bit 2 is a logic 1 When either a 6-, 7-, or 8-  
bit word length is selected, two Stop bit are generated.  
The Receiver checks the first Stop bit only, regardless of  
the number of Stop bit selected.  
1. Load on all Os, pad character, in response to THRE.  
2. Set break after the next THRE  
3. Wait for the transmitter to be idle. (TEMT = 1), and  
clear break when normal transmission has to be tired.  
During the bread, the Transmitter can be used as a  
character timer to accurately establish the break duration.  
Bit 7: This bit is the Divisor Latch Access Bit (DLAB).  
It must be set high (logic) to access the Divisor Latches  
of the Baud Generator during a Read or Write operation.  
It must be set low (logic 0) to access the Receiver Buffer,  
the Transmitter Holding Register, or the Interrupt Enable  
Register.  
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic  
1, a Parity bit is generated (transmit data) or checked  
(receive data) between the last data word bit and Stop bit of  
the serial data. (The Parity bit is used to produce an even or  
odd number of 1s when the data word bits and the Parity bit  
Typical Clock Circuits  
VCC  
VCC  
DRIVER  
EXTERNAL  
XIN  
CLOCK  
XIN  
C1  
RP  
CRYSTAL  
OSC CLOCK TO  
BAUD GEN. LOGIC  
OPTIONAL  
DRIVER  
OSC CLOCK TO  
BAUD GEN. LOGIC  
R´ 2  
OPTIONAL  
CLOCK  
OUTPUT  
XOUT  
XOUT  
C2  
15  
GM16C550  
Typical Crystal Oscillator Network  
Crystal  
RP  
C1  
C2  
R´  
2
1M  
1M  
W
3.1MHz  
1.8MHz  
1.5k  
1.5k  
10-30pF  
10-30pF  
40-60pF  
40-60pF  
W
TABLE III. Baud Rates Using 1.8432 MHz Crystal  
Decimal Divisor  
Percent Error Difference  
Between Desired and Actual  
Used to Generate  
Desired Baud Rate  
16 ´ Clock  
50  
75  
110  
134.5  
150  
300  
2304  
1536  
1047  
857  
768  
384  
192  
96  
64  
58  
48  
32  
24  
16  
12  
6
3
2
-
-
0.026  
0.058  
0.69  
-
-
-
-
-
-
-
600  
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
56000  
2.86  
16  
GM16C550  
TABLE IV. Baud Rates Using 3.072 MHz crystal  
Decimal Divisor  
Percent Error Difference  
Between Desired and Actual  
Used to Generate  
Desired Baud Rate  
16´Clock  
50  
75  
110  
134.5  
150  
300  
3840  
2560  
1745  
1428  
1280  
640  
320  
160  
107  
96  
80  
53  
40  
27  
20  
10  
5
-
-
0.026  
0.034  
-
-
-
-
0.312  
-
-
0.628  
-
1.23  
600  
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
-
-
-
TABLE V. Baud Rate Using 8MHz Crystal  
Decimal Divisor  
Percent Error Difference  
Between Desired and Actual  
Used to Generate  
Desired Baud Rate  
16´Clock  
50  
75  
110  
134.5  
150  
300  
10000  
6667  
4545  
3717  
3333  
1667  
833  
417  
277  
250  
208  
139  
104  
69  
-
0.005  
0.010  
0.013  
0.010  
0.020  
0.040  
0.080  
0.080  
-
0.160  
0.080  
0.160  
0.644  
0.160  
0.160  
0.160  
0.790  
2.344  
2.344  
600  
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
56000  
128000  
256000  
52  
26  
13  
9
4
2
17  
GM16C550  
18  
GM16C550  
PROGRAMMABLE BAUD  
GENERATOR  
The UART contains a programmable Baud Generator that is  
capable of taking any clock input from 2 to 216–1. 4MHz is  
the highest input clock frequency recommended when the  
divisor = 1. The output frequency of the Baud Generator is 16  
´ the Baud [divisor # = (frequency input) ¸ (baud rate ´ 16)]  
Two 8-bit latches store the divisor in a 16-bit binary format.  
These Divisor Latches must be loaded during initialization to  
ensure proper operation of the Baud Generator. Upon loading  
either or the Divisor Latches, a 16-bit Baud counter is  
immediately loaded.  
its associated character is at the top of the FIFO. The UART  
will try to resynchronize after a framing error. To do this it  
assumes that the framing error was due to the next start bit so  
it samples this “start” bit twice and then takes in the “data”.  
Bit 4: This bit is the Break Interrupt (BI) indicator.  
Bit 4 is set to a logic 1 when ever the received data input is  
held in the spacing (logic) state for longer than a full word  
transmission time (that is, the total time of Start Bit + data  
bits + Parity + Stop bits). The BI indicator is reset whenever  
the CPU reads the contents of the line Status Register. In the  
FIFO mode this error is associated with the particular  
character in the FIFO it applies to. This error is revealed to  
the CPU when its associated character is at the top of the  
FIFO. When break occurs only one zero character is loaded  
into the FIFO. The next character transfer is enabled after  
SIN goes to the marking state and receives the next valid start  
bit.  
Tables III, IV and V provide decimal divisors to use with  
crystal frequencies of 1.8432 MHz 3.072MHz and 8 MHz,  
respectively. For baud rates of 38400 and below, the error  
obtain is minimal. The accuracy of the desired baud rate is  
dependent on the crystal frequency chosen. Using a divisor of  
zero is not recommended.  
LINE STATUS REGISTER  
This register provides status information to the CPU  
concerning the data transfer. Table II shows the contents of  
the Line Status Register. Details on each bit follow.  
Note: Bits 1 through 4 are the error conditions that produce a  
Receiver Line Status interrupt whenever any of the  
corresponding conditions are detected and the interrupt is  
enabled.  
Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit  
0 is set to logic 1whenever a complete incoming character has  
been received and transferred into the Receiver Buffer  
Register or the FIFO. Bit 1 is reset to a logic 0 by reading all  
of the data in the Receiver Buffer Register or the FIFO.  
Bit 5: This bit is the Transmitter Holding Register Empty  
(THRE) indicator. Bit 5 indicates that the UART is ready to  
accept a new character for transmission. In addition, this bit  
causes the UART to issue an interrupt to the CPU when the  
Transmit Holding Register Empty Interrupt enable is set high.  
The THRE bit is set to logic 1 when a character is transferred  
from the Transmitter Holding Register into the Transmitter  
Shift Register. The bit is reset to logic 0 concurrently with the  
loading of the Transmitter Holding Register by the CPU, In  
the FIFO mode this bit is set when the XMIT FIFO is empty;  
it is cleared when at least 1 byte is written to the XMIT FIFO.  
Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1  
indicates that data in the Receiver Buffer Register was not  
read by the CPU before the next character was transferred  
into the Receiver Buffer Register, thereby destroying the  
previous character. The OE indicator is set to a logic 1 upon  
detection of an overrun condition and reset whenever the  
CPU reads the contents of the Line Status Register  
If the FIFO mode data continues to fill the FIFO beyond the  
trigger level, An overrun error will occur only been  
completely received in the shift register. OE is indicated to  
the CPU as soon as it happens. The character on the shift  
register is overwritten, but is not transferred to the FIFO.  
Bit 6: This bit is the Transmitter Empty (TEMT) indicator.  
Bit 6 is set to a logic 1 whenever the Transmitter Holding  
Register (THR) and the Trans-mitter shift register (TSR) are  
both empty. It is reset to a logic 0 whenever either the THR or  
TSR contains a data character. In the FIFO mode this bit is set  
to one whenever the transmitter FIFO and shift register are  
both empty.  
Bit 2: This bit is the Parity Error (PE) indicator. Bit 2  
indicates that the received data character does not have the  
correct even or odd parity. As selected by the even –parity-  
select bit. The PE bit is set to a logic 1 upon detection of a  
parity error and is reset to a logic 0 whenever the CPU reads  
the contents of the Line Status Register. In the FIFO mode  
this error is associated with the particular character in the  
when its associated character is at the top of the FIFO.  
Bit 7: in the GM16C450 Mode this is a 0. In the FIFO mode  
LSR7 is set when there is least one parity error, framing error  
or break indication in the FIFO. LSR7 is cleared when the  
CPU reads the LSR, if there are no subsequent errors in the  
FIFO.  
Note: The Line Status Register is intended for read op-  
erations only. Writing to this register is not recom-mended as  
this operation is only used for factory testing.  
Bit 3: This bit is the Framing Error (FE) indicator.  
Bit3 indicates that the received character did not have a valid  
Stop bit. Bit 3is set to logic 1 whenever the Stop bit following  
the last data bit or parity bit is detected as a logic 0 bit  
(Spacing level). The FE indicator is reset whenever the CPU  
reads the contents of the Line Status Register. In the FIFO  
mode this error is associated with the particular character in  
the FIFO it applies to. This error is revealed to the CPU when  
FIFO CONTROL REGISTER  
This is a write only register at the same location as the IIR  
(the IIR is a read only register). This register is used to enable  
the FIFOs, set the RCVR FIFO trigger level, and select the  
type of DMA signaling.  
19  
GM16C550  
Bit 0: Writing a 1 to FCR0 enables both the XMIT and  
RCVR FIFOs. Resetting FCR0 will clear all bytes in both  
FIFOs. When changing from FIFO Mode to GM16C450  
Mode and vice versa, data is automatically cleared from the  
FIFOs. This bit must be a 1 when other RCR bits are written  
to or they will not be programmed.  
Bit 4 and 5: These two bits of the IIR are always logic 0.  
Bit 6 and 7: These two bits are set when FCR0 =1.  
INTERRUPT ENABLE REGISTER  
This register enables the five types of UART interrupts. Each  
interrupt can individually activate the interrupt (INTR) output  
signal. It is possible to totally disable the interrupt system by  
resetting bits 0 through 3 of the Interrupt Enable Register  
(IER).  
Similarly, setting bits of the IER register to a logic 1, enables  
the selected interrupt(s). Disabling an interrupt prevents it  
from being indicated as active in the IIR and from activating  
the INTR output signal. All other system functions operate in  
their normal manner, including the setting of the Line Status  
and MODEM Status Registers. Table II shows the contents of  
the IER. Details on each bit follow.  
Bit 1: Writing a 1 to FCR1 clears all bytes in the RCVR FIFO  
and resets its counter logic to 0. The shift register is not  
cleared. The 1 that is written to this bit position is self-  
clearing.  
Bit 2: Writing a 1 to FCR2 clears all bytes in the XMIT FIFO  
and resets its counter logic to 0. The shift register is not  
cleared. The 1 that is written to this bit position is self-  
clearing.  
Bit 3: Setting FCR 3 to a 1 will cause the RXRDY and  
TXRDY pins to change from mode 0 to mode 1 if FCR0 = 1  
(see description of RXRDY and TXRDY pins).  
Bit 0: This bit enables the Received Data Available Interrupt  
(and timeout interrupts in the FIFO mode) when set to logic1.  
Bit4, 5: FCR4 to FCR5 are reserved for future use.  
Bit 2: This bit enables the Receiver Line Status interrupt  
when set to logic 1  
Bit6, 7: FCR6 to FCR7 are used to set the trigger level for the  
RCVR FIFO interrupt.  
Bit 3: This bit enables the MODEM Status interrupt when set  
to logic 1  
RCVR FIFO  
Trigger Level  
Bit 4 through 7: These four bits are always logic 0.  
7
6
(Bytes)  
01  
MODEM CONTROL REGISTER  
0
0
1
1
0
1
0
1
This register controls the interface with the MODEM or data  
set (or peripheral device emulating a MODEM). The contents  
of the MODEM Control Register are indicated in Table II and  
are described below.  
04  
08  
14  
INTERRUPT IDENTIFICATION  
REGISTER  
Bit 0: This bit controls the Data Terminal Ready  
(DTR) output. When bit 0 is set to a logic 1, the DTR output  
is forced to a logic 0. When bit 0 is reset to a logic 0, the DTR  
output is forced to a logic 1.  
In order to provide minimum software overhead during data  
character transfers, the UART prioritizes interrupts into four  
levels and records these in the interrupt Identification Register.  
The four levels of interrupt conditions in order of priority are  
Receiver Line Status; Received Data Ready; Transmitter  
Holding Register Empty; and MODEM Status. When the  
CPU accesses the IIR, the UART freezes all interrupts and  
indicates the highest priority pending interrupt to the CPU.  
While this CPU access is occurring, the UART records niw  
interrupts, but access is complete. Table II shows the contents  
of the IIR. Details on each bit follow:  
Note: The DTR output of the UART may be applied to  
an EIA inverting line driver (such as the GD751-  
88) to obtain the proper polarity input at the succ-  
eeding MODEM or data set.  
Bit 1: This bit controls the Request to Send (RTS) output. Bit  
1 affects the RTS output in a manner identical to that  
described above for bit 0.  
Bit 2: This bit controls the output 1 (OUT1) signal , which is  
an auxillary user-designated output. Bit 2 affects the OUT1  
output in a manner identical to that described above for bit 0.  
Bit 0: This bit can be used in  
a prioritized interrupt  
environment to indicate whether an interrupt is pending.  
When bit 0 is a logic 0, an interrupt is pending and the IIR  
contents may be used as a pointer to the appropriate interrupt  
service routine. When bit 0 is a logic 1, no interrupt is  
pending.  
Bit 3: This bit controls the output 2(OUT2) signal, which is  
an auxillary user-designated output . Bit 3 affects the OUT2  
output in a manner identical to that described above for bit 0.  
Bit 1 and 2: These two of the IIR are used to identify  
highest priority interrupt pending as indicated in Table VI.  
Bit 4: This bit provides  
a local loopback feature for  
Diagnostic testing of the UART. When bit 4 is set to logic 1,  
the following occur ; the transmitter Serial output (SOUT) is  
set to the Marking (logic 1) State; the receiver Serial Input  
(SIN) is disconnected; the output of the Transmitter Shift  
Bit 3: In the GB16C450 Mode this bit is 0. In the FIFO mode  
this bit is set along with bit 2 when a timeout interrupt is  
pending.  
20  
GM16C550  
Register is “looped back” into the Receiver Shift Register  
input; the four MODEM Control inputs ( , RI ,  
is equivalent to out2 in the MCR.  
,
CTS RTS  
) are disconnected; and the four MODEM Control  
SCRATCHPAD REGISTER  
and  
DCD  
outputs ( DTR ,  
,
and  
) are internally  
OUT2  
This 8-bit Read/Write Register does not control the UART in  
anyway. It is intended as a scratchpad register to be used by  
the programmer to hold data temporarily.  
RTS OUT1  
connected to the four MODEM Control inputs, and the  
MODEM Control output pins are forced to their inactive state  
(high). In the diagnostic mode, data that is transmitted is  
immediately received. This feature allows the processor to  
verify the transmitter and received-data paths of the UART.  
FIFO INTERRUPT MODE OPERATION  
When the RCVR FIFO and receiver interrupts are enabled  
(FCR0 = 1, IER0 =1) RCVR interrupts will occur as follows:  
In the diagnostic mode, the receiver and transmitter interrupts  
are fully operational. Their sources are external to the part.  
The MODEM Control Interrupts are also operational, but the  
interrupts sources are now the lower four bits or the MODEM  
Control inputs. The interrupts are still controlled by the  
Interrupt Enable Register.  
A. The receive data available interrupts will be issued to the  
CPU when the FIFO has reached its programmed trigger  
level; it will be cleared as soon as the FIFO drops below its  
programmed trigger level.  
B. The IIR receive data available indicate also occurs when  
the FIFO trigger level is reached, and like the interrupt it is  
cleared when the FIFO drops below the trigger level.  
Bits 5 through 7: These bits are permanently set to logic 0.  
MODEM STATUS REGISTER  
This register provides the current state of the control lines  
from the MODEM (or peripheral device) to the CPU. In  
addition to this current-state information, four bits of the  
MODEM Status Register provide change information. These  
bits are set to a logic 1 Whenever a control input from the  
MODEM changes state. They are reset to logic 0 whenever  
the CPU reads the MODEM Status Register.  
C. The receiver line status interrupt (IIR-06), as before, has  
higher priority than received data available (IIR-04) interrupt.  
D. The data ready bit (LSR0)is set as soon as a character is  
transferred from the shift register to the RCVR FIFO. It is  
reset when the FIFO is empty.  
When RCVR FIFO and receiver interrupts are enabled,  
RCVR FIFO timeout interrupts will occur as follows:  
The contents of the MODEM Status Register are indicated in  
Table II and described below.  
A. A FIFO timeout interrupt will occur, if the following  
Bit 0: This bit is the Delta Clear to Send (DCTS) indicator.  
conditions exist:  
Bit 0 indicates that the  
input to the chip has changed  
-
at least one character is in the FIFO  
CTS  
state since the last time it was read by the CPU.  
-
the most recent serial character received was  
longer than 4 continuous character times ago (if  
2 stop bits are programmed the second one is  
included in this time delay).  
Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator.  
Bit 1 indicates that the  
input to the chip has changed  
DSR  
state since the last tome it was read by the CPU.  
-
The most recent CPU read if the FIFO was longer  
than 4continuous character times age.  
Bit 2: This bit is the Trailing Edge of Ring Indicator (TERI)  
detector. Bit 2 indicates that the RI input to the chip has  
changed from a low to a high state.  
This will cause a maximum character received to interrupt  
issued delay of 160ms at 300BAUD with a 12 bit character.  
Bit 3: This bit is the Delta Data Carrier Detect (DDCD)  
B. character times are calculated by using the RCLK input for  
a clock signal (This makes the delay proportional to the  
baudrate).  
indicator. Bit 3 indicates that the  
input to the chip has  
DCD  
changed state.  
Note: Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM  
Status Interrupt is generated.  
C. When a timeout interrupt has occurred it is cleared and the  
timer rest when the CPU reads one character from the RCVR  
FIFO.  
Bit 4: This bit is the complement of the Clear to Send (  
)
CTS  
input. If bit 4(loop) of the MCR is set to a 1, this bit is  
equivalent to RTS in the MCR.  
D. When a timeout interrupt has not occurred the timeout  
timer is reset after a new character is received or after the  
CPU reads the RCVR FIFO.  
Bit 5: This bit is the complement of the Data Set Ready  
(
) input. If Bit 4 of the MCR is set to a 1, this bit is  
DSR  
equivalent to DTR in the MCR.  
When the XMIT FIFO and transmitter interrupts are enabled  
(FCR0=1, IER=1) XMIT interrupts will occur as follows:  
Bit 6: This bit is the complement of the Ring Indicator. ( RI )  
input. If bit 4 of the MCR is set to a 1, this bit is equivalent to  
OUT1 in the MCR.  
A. The transmitter holding register interrupt (02) occurs when  
the XMIT FIFO is empty; it is cleared as soon as the  
transmitter holding register is written to (1 to 16 characters  
may be written to the XMIT FIFO while servicing this  
interrupt) or the IIR is read.  
Bit 7: This bit is the complement of the Data Carrier  
Detect(DCD) input. If but 4 of the MCR is set to a 1, this bit  
21  
GM16C550  
In this mode the user’ s program will check RCVR and  
XMITTER status via the LSR. As stated previously:  
LSR0 will be set as long as there is one byte in the RCR FIFO.  
LSR1 to LSR4 will specify which error(s) has occurred.  
Character error status is handled the same way when in the  
interrupt mode, the IIR is not affected since IER2=0.  
LSR5 will indicate when the XMIT FIFO is empty.  
LSR6 will indicate that both the XMIT FIFO and shift  
register are empty.  
The transmitter FIFO empty indications will be delayed 1  
character time minus the last stop bit time whenever the  
following occurs: THRE = 1 and there have not been at least  
two bytes at the same time in the transmit FIFO, since the last  
THRE = 1. The first transmitter interrupt affect changing  
FCR0 will be immediate, if it is enabled.  
Character timeout and RCVR FIFO trigger level interrupts  
have the same priority as the current received data available  
interrupt; XMIT FIFO empty has the same priority as the  
current transmitter holding register empty interrupt.  
LSR7 will indicate whether there are any errors in the RCVR  
FIFO.  
FIFO POLLED MODE PRERATION  
There is no trigger level reached or timeout condition  
indicated in the FIFO polled Mode, however, the RCVR and  
XMIT FIFOs still fully capable of holding characters.  
With FCRQ = 1 resetting IER0, IER1, IER2, IER3 or all to  
zero puts the RCVR and MITTER are controlled separately  
either one or both can be in the polled mode of operation.  
Application Circuit  
SYSTEM BUS  
XTAL1  
XTAL2  
A0 A23  
A0 A2  
CS2  
LATCH  
ADDRESS  
DECODER  
+5  
CS1  
CS0  
CPU  
RCLK  
SOUT  
RESET  
MR  
GM16C550  
SIN  
RST  
DATA  
BUFFER  
D0 D7  
D0 D15  
D0 D7  
DTR  
DSR  
EIA  
DRIVERS  
RS-232-C D  
INTERFACE  
DCD  
CTS  
tOR  
DISTR  
tCW  
RI  
DOSTR  
INTRPT  
DISTR  
DOSTR  
ADS  
TXRDY  
DDIS  
RXRDY  
D0-D15  
22  
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