PLUTO
CDMA TX Section Analog Interface
CDMA Receive Calibration Circuit
The ITx and QTx outputs can be d.c. or a.c. coupled to the
external circuits and will differentially drive a minimum
resistiveloadof5 kΩandamaximumcapacitiveloadof20 pF.
When the CDMA transmit path is in power-down mode the
positive outputs goes high and the negative output goes low.
OnenteringintoCDMAmode frompowerdownorfromFM
mode the calibration circuits are activated. These circuits
measure the differences between the receive path gain in the
pass band and in the transition band of both I and Q filters. Via
a successive approximation process they tune the receive
filterscut-offfrequencyandamplitudematchingusingthe8bit
DACs provided for this purpose (I_FC, Q_FC and BAL). Once
both filters (I and Q) have been calibrated in this way the DAC
outputs will not change until the chip is powered down or the
calibration circuit is re-activated in some other way.
FM Transmit Signal Path
FM TX DAC
In FM mode, the Q-Channel DAC is used to generate an
analog FM modulation signal from the data transmitted from
the digital baseband processor. In this mode, all other CDMA
TX circuits are powered down.
FM Receive Signal Path
In FM mode two low speed 8-bit ADCs are used to digitise
the incoming signals before subsequent transmission to the
baseband digital signal processor as two serial 8-bit words
(FMRXI&FMRXQ). Thesamplerateisentirelydeterminedby
the digital baseband processor (up-to the maximum allowed)
via the FMCLK input.
In FM mode the receive filters are assumed to track the
filters used in CDMA mode i.e. there is no separate tuning
mechanism.
FM Mode Analog Reconstruction Filters
The frequency spectrum at the output of the transmit DAC
contains unwanted frequency components. A reconstruction
filter is used to smooth the DAC output signals.
Low-pass filters are used with a cut-off frequency of
approximately 13 kHz. These filters are 3rd order Butterworth
filters.
FM TX Section Analog Interface
SYNTHESISERS
The FMTX output can be d.c. or a.c. coupled to the radio
circuits and will drive a minimum resistive load of 5 kΩ and a
maximum capacitive load of 20 pF.
When the FM mode is in power-down the output is in high
impedance state.
The Synthesiser block comprises the input buffers, main
dividers, phase comparator, charge pump and lock detect
circuitforaTXandRXsynthesiser.Theloopfiltercomponents
andtheVCOsareexternaltothedevice. Acommonreference
divider chain is also included together with bias and control
circuitry. All blocks apart from reference divider, bias and
control logic are duplicated exactly for RX and TX
synthesisers.
CDMA Receive Signal Path
CDMA Receive ADC
In CDMA mode two high speed 4-bit ADCs are used to
digitise the incoming signals before subsequent transmission
to the baseband digital signal processor as two parallel 4 bit
words (RXI<3:0> and RXQ<3:0>). The sample rate of
9.8304MHz is generated via an on chip synthesiser that
requiresnosettinguporexternalcomponents. Oneachfalling
edge of the synthesised clock (CHIPx8) a new digital sample
is output on the digital bus.
The receive intermediate frequency (RX_IF) is
programmable and the transmit intermediate frequency
(TX_IF) is fixed at 130.38MHz.
AUX ADC
The auxiliary converter section contains a single 8-bit
successive approximation analog to digital converter, with
serial output. In order to maximise the flexibility of Pluto, a 4
way analog multiplexer is provided, which enables the
converter to encode any one of four selectable channels. The
converter is intended for such applications as power supply
and temperature monitoring. When not in use, the converter is
powered down, and its outputs are held low.
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