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GS82032AT-180/166/150/133/100/66/4/5/6

180 MHz–66 MHz

TQFP

Commercial Temp

Industrial Temp

64K x 32

2Mb Synchronous Burst SRAM

3.3 V V

DD

3.3 V and 2.5 V I/O

counter may be configured to count in either linear or

Features

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• FT pin for user-configurable flow through or pipelined opera-

tion

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

Flow Through/Pipeline Reads

• 2.5 V or 3.3 V I/O supply

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode,

activating the rising-edge-triggered Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

SCD Pipelined Reads

The GS82032A is an SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

The GS82032A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E¹, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Core and Interface Voltages

The GS82032A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuit.

Parameter Synopsis

-180

-166

-150

-133 (-4) -100 (-5) -66 (-6)

Pipeline tCycle

5.5 ns

3.2 ns

155 mA

6 ns

3.5 ns

140 mA

6.6 ns

3.8 ns

130 mA

7.5 ns

4 ns

115 mA

10 ns

5 ns

90 mA

12.5 ns

6 ns

65 mA

3-1-1-1

t^KQ

IDD

Flow

Through

2-1-1-1

tCycle

t^KQ

IDD

9.1 ns

8 ns

100 mA

10 ns

8.5 ns

90 mA

10.5 ns

9 ns

85 mA

12 ns

10 ns

80 mA

15 ns

12 ns

65 mA

20 ns

18 ns

50 mA

Rev: 1.12 10/2004

1/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

GS82032A 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

DQB

DQ^B

V

NC

DQC

DQ^C

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

DQ^C

DQC

64K x 32

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQB

DQC

V

FT

DD

NC

SS

NC

V

ZZ

DD

V

SS

DQ^A

DQA

V

DQD

V

DDQ

SS

V

SS

DQA

DQD

V

SS

DDQ

SS

V

DDQ

DQA

NC

DQD

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.12 10/2004

2/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

TQFP Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

NC

BW

No Connect

I

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

B^A, BB

B^C, BD

CK

GW

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E¹, E3

E²

Chip Enable; active high

G

Output Enable; active low

ADV

ADSP, ADSC

ZZ

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

FT

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

LBO

V

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.12 10/2004

3/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

GS82032A Block Diagram

^RegisteQ^r

A0–An

D

A0

A1

A0

A1

D0

D1

Counter

Load

Q0

Q1

A

LBO

ADV

CK

Memory

Array

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

32

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

E2

E3

D

Q

Register

D

Q

FT

G

Power Down

Control

DQx1–DQx8

ZZ

Rev: 1.12 10/2004

4/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Mode Pin Functions

Mode Name

Pin Name

State

L

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

Output Register Control

Power Down Control

LBO

H or NC

L

FT

ZZ

H or NC

L or NC

H

Active

Standby, I = I

DD SB

Note:

There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will

operate in the default states as specified in the above table.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Rev: 1.12 10/2004

5/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Byte Write Truth Table

Function

Read

GW

BW

H

L

B

A

B

C

B

D

Notes

1

H

L

X

H

L

X

H

L

X

H

L

X

H

L

Read

1

Write byte ^A

Write byte ^B

Write byte ^C

Write byte ^D

Write all bytes

L

2, 3

L

H

L

2, 3

L

H

L

2, 3, 4

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B^A, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

Rev: 1.12 10/2004

6/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Synchronous Truth Table

Operation

State

Address

Used

2

3

4

Diagram

E1

ADSP ADSC ADV

E

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

X

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

F

T

X

High-Z

None

X

L

H

L

High-Z

External

X

L

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E²= 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.12 10/2004

7/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E^1,E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control

inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.12 10/2004

8/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data

Input Set Up Time.

Rev: 1.12 10/2004

9/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

–0.5 to V

DD

V

DDQ

V

Voltage on Clock Input Pin

Voltage on I/O Pins

–0.5 to 6

–0.5 to V +0.5 (≤ 4.6 V max.)

V

CK

I/O

V

DDQ

V

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

I

OUT

P

1.5

D

o

T

–55 to 125

STG

BIAS

C

o

T

Temperature Under Bias

C

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V

Supply Voltage

3.135

2.375

1.7

3.3

2.5

—

3.6

V

1

2

3

DD

V

I/O Supply Voltage

Input High Voltage

Input Low Voltage

DDQ

DD

V

V +0.3

DD

V

IH

V

–0.3

0

—

0.8

V

IL

T

Ambient Temperature (Commercial Range Versions)

25

70

85

°C

A

T

Ambient Temperature (Industrial Range Versions)

–40

A

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V

≤ 2.375 V (i.e., 2.5 V I/O)

DDQ

and 3.6 V ≤ V

≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case.

DDQ

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evalu-

ated for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.

DD

Rev: 1.12 10/2004

10/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+- 2.0 V

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Capacitance

(T = 25°C, f = 1 MHZ, V = 3.3 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

C

V

= 3.3 V

= 0 V

Control Input Capacitance

Input Capacitance

3

4

6

4

5

7

pF

I

DD

C

V

IN

C

V

= 0 V

OUT

Output Capacitance

OUT

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Conditions

Input high level

Input low level

2.3 V

0.2 V

Input slew rate

1 V/ns

1.25 V

Fig. 1& 2

Input reference level

Output reference level

Output load

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for t , t , t and t

LZ HZ OLZ

OHZ

4. Device is deselected as defined by the Truth Table.

Output Load 2

2.5 V

Output Load 1

DQ

225Ω

DQ

*

50Ω

VT = 1.25 V

30pF

*

5pF

* Distributed Test Jig Capacitance

Rev: 1.12 10/2004

11/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

–1 uA

1 uA

300 uA

DD

IN

IH

I

ZZ Input Current

INZZ

0V ≤ V ≤ V

IN

V

≥ V ≥ V

–300 uA

–1 uA

1 uA

DD

IN

IL

I

Mode Pin Input Current

Output Leakage Current

INM

0V ≤ V ≤ V

IN

Output Disable,

V

I

–1 uA

1 uA

OL

= 0 to V

OUT

DD

V

I

= –4 mA, V

= 2.375 V

Output High Voltage

Output Low Voltage

1.7 V

2.4 V

OH

DDQ

V

= 3.135 V

OH

V

I

= 4 mA

OL

0.4 V

OL

Rev: 1.12 10/2004

12/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Rev: 1.12 10/2004

13/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

AC Electrical Characteristics

-180

-166

-150

-133

-100

-66

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

tKC

tKQ

5.5

—

3.2

—

8

6

—

3.5

—

8.5

—

6.6

—

3.8

—

9

7.5

—

4

10

—

1.5

15

—

3

—

5

12.5

—

6

ns

Clock to Output Valid

—

1.5

10

—

3

Pipeline

Clock to Output Invalid

tKQX

1.5

9.1

—

1.5

10.5

—

1.5

12

—

10

—

4

—

12

—

5

1.5

20

—

18

—

6

1

Clock to Output in Low-Z

Clock Cycle Time

tLZ

tKC

tKQ

Clock to Output Valid

Flow

Through

Clock to Output Invalid

Clock to Output in Low-Z

Clock HIGH Time

tKQX

3

—

3.2

—

3

—

3

1

3

tLZ

tKH

tKL

1.3

1.5

—

1.3

1.5

1.3

1.5

1.3

1.5

1.3

1.5

—

0

1.3

1.5

—

Clock LOW Time

1

Clock to Output in High-Z

G to Output Valid

1.5 3.5 1.5 3.8 1.5

tHZ

tOE

—

0

3.5

—

0

3.8

—

0

4

5

6

1

G to output in Low-Z

0

—

0

—

tOLZ

1

G to output in High-Z

Setup time

—

1.5

0.5

5

3.2

—

1.5

0.5

5

3.5

—

1.5

0.5

5

3.8

—

1.5

0.5

5

4

—

1.5

0.5

5

—

1.5

0.5

5

6

ns

tOHZ

tS

tH

—

Hold time

2

ZZ setup time

tZZS

2

ZZ hold time

ZZ recovery

1

—

1

—

1

—

1

—

1

—

1

—

ns

tZZH

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.12 10/2004

14/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Pipeline Mode Timing

Begin

Read A Cont

Single Read

Cont

Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont

Deselect

Single Write

tKL

Burst Read

tKH

tKC

CK

ADSP

tS

tH

tS

ADSC initiated read

ADSC

ADV

tH

A

B

C

A0–An

GW

tS

tH

BW

tS

Ba–Bd

E1

tS

Deselected with E1

tH

E1 masks ADSP

tH

E2 and E3 only sampled with ADSP and ADSC

E2

E3

G

tS

D(B)

tKQ

tKQX

tHZ

Q(C+2) Q(C+3)

tOE

tOHZ

Q(A)

tH

tLZ

Q(C)

Q(C+1)

DQa–DQd

Rev: 1.12 10/2004

15/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Flow Through Mode Timing

Begin

Read A Cont

tKH

Cont

Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont

Deselect

tKL

tKC

CK

Fixed High

ADSP

tS

tH

tS

tH

ADSC initiated read

ADSC

ADV

A0–An

GW

tS

tH

tS

tH

A

B

C

tS

tH

tS

tH

BW

tS

tH

Ba–Bd

E1

tS

Deselected with E1

tH

E2 and E3 only sampled with ADSC

E2

tS

tH

E3

G

tH

tS

tKQ

tLZ

tHZ

tOE

tOHZ

D(B)

tKQX

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

Rev: 1.12 10/2004

16/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Sleep Mode Timing

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output

drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there

will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on

dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address

boundary crossings), but greater care must be exercised to avoid excessive bus contention.

Rev: 1.12 10/2004

17/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

GS82032A Output Driver Characteristics

60

40

Pull Down Drivers

20

V_DDQ

I Out

0

VOut

V_SS

-20

-40

-60

-80

Pull Up Drivers

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

V_DDQ- V Out (Pull Up)

3.6V PD LD

3.3V PD LD

3.1V PD LD

3.1V PU LD

3.3V PU LD

3.6V PU LD

Rev: 1.12 10/2004

18/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

TQFP Package Drawing (Package T)

θ

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

0.10

7°

θ

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 1.12 10/2004

19/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Ordering Information for GSI Synchronous Burst RAMs

2

T

3

Speed

A

1

Org

Type

Package

Status

Part Number

(MHz/ns)

64K x 32

GS82032AT-180

GS82032AT-166

GS82032AT-150

GS82032AT-133

GS82032AT-100

GS82032AT-66

GS82032AT-4

Pipeline/Flow Through

TQFP

180/8

166/8.5

150/9

C

I

TQFP

133/10

100/12

66/18

TQFP

133/10

100/12

66/18

GS82032AT-5

TQFP

GS82032AT-6

TQFP

GS82032AT-180I

GS82032AT-166I

GS82032AT-150I

GS82032AT-133I

GS82032AT-100I

GS82032AT-66I

GS82032AT-4I

GS82032AT-5I

GS82032AT-6I

TQFP

180/8

TQFP

166/8.5

150/9

I

TQFP

I

TQFP

133/10

100/12

66/18

I

TQFP

I

TQFP

I

TQFP

133/10

100/12

66/18

I

TQFP

I

TQFP

I

64K x 32 GS82032AGT-180

64K x 32 GS82032AGT-166

64K x 32 GS82032AGT-150

64K x 32 GS82032AGT-133

64K x 32 GS82032AGT-100

64K x 32 GS82032AGT-66

Pb-free TQFP

180/8

C

I

166/8.5

150/9

133/10

100/12

66/18

64K x 32

GS82032AGT-4

GS82032AGT-5

GS82032AGT-6

133/10

100/12

66/18

64K x 32 GS82032AGT-180I

64K x 32 GS82032AGT-166I

180/8

166/8.5

150/9

I

64K x 32 GS82032AGT-150I

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.12 10/2004

20/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Ordering Information for GSI Synchronous Burst RAMs

2

T

3

Speed

A

1

Org

Type

Package

Status

Part Number

(MHz/ns)

64K x 32 GS82032AGT-133I

64K x 32 GS82032AGT-100I

64K x 32 GS82032AGT-66I

Pipeline/Flow Through

Pb-free TQFP

133/10

100/12

66/18

I

64K x 32

GS82032AGT-4I

GS82032AGT-5I

GS82032AGT-6I

133/10

100/12

66/18

64K x 32

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.12 10/2004

21/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82032AT-180/166/150/133/100/66/4/5/6

Revision History

Types of Changes

Format or Content

DS/DateRev. Code: Old;

Revisions

New

• First Release of A version. Added “A” Version to 82032T/Q,

820E32TQ, and 820H32TQ

GS82032 Rev 1.03 2/

2000D;GS820321.04 3/

2000E

Content

• Updated ADSC in timing diagrams on pages 16 and 18

GS820321.04 3/2000E;

GS82032A_r1_05

• Added 200 MHz, 180 MHz, and 166 MHz speed bins (all refer-

ences updated)

• Deleted 150 MHz, 138 MHz, and 66 MHz speed bins (all refer-

ences deleted)

82032A_r1_05;

82032A_r1_06

Content

• Deleted BGA reference in “Flow Through/Pipeline Reads” on

page 1

• Updated entire datasheet with new standards

• Updated table on page 1

• Updated Operating Currents table on page 12

• Updated Electrical Characteristics table on page 13

• Updated format to comply with Technical Publications stan-

dards

82032A_r1_06;

82032A_r1_07

• Added the following part numbers to the Ordering Information

table on page 22:

–GS82032AT-4

–GS82032AT-6

–GS82032AT-4I

–GS82032AT-6I

–GS82032AQ-4

–GS82032AQ-6

–GS82032AQ-4I

–GS82032AQ-6I

82032A_r1_07;

82032A_r1_08

Content

• Removed all references to 200 MHz parts (no longer active)

82032A_r1_08;

82032A_r1_09

Content

• Complete rewrite of datasheet in order to reflect parts

available

82032A_r1_09;

82032A_r1_10

• Reactiviated 180 MHz speed bin

• Updated format

82032A_r1_10;

82032A_r1_11

• Added Pb-free information for TQFP

82032A_r1_11;

82032A_r1_12

Rev: 1.12 10/2004

22/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

型号:	GS82032AT-5
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	LQFP, QFP100,.63X.87
针数：	100
Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41
风险等级：	5.83
Is Samacsys：	N
最长访问时间：	12 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0
长度：	20 mm
内存密度：	2097152 bit
内存集成电路类型：	CACHE SRAM
内存宽度：	32
湿度敏感等级：	3
功能数量：	1
端子数量：	100
字数：	65536 words
字数代码：	64000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	64KX32
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP
封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
最大待机电流：	0.01 A
最小待机电流：	3.14 V
子类别：	SRAMs
最大压摆率：	0.18 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

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