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产品型号HA9P2425-5的Datasheet PDF文件预览

HA-2420, HA-2425  
3.2µs Sample and Hold Amplifiers  
November 1996  
Features  
Description  
• Maximum Acquisition Time  
The HA-2420 and HA-2425 is a monolithic circuit consisting  
- 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . 4µs (Max) of a high performance operational amplifier with its output in  
series with an ultra-low leakage analog switch and JFET  
input unity gain amplifier.  
- 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . 6µs (Max)  
• Low Droop Rate (C = 1000pF). . . . . . . . 5µV/ms (Typ)  
H
With an external hold capacitor connected to the switch output,  
a versatile, high performance sample-and-hold or track-and-  
hold circuit is formed. When the switch is closed, the device  
behaves as an operational amplifier, and any of the standard op  
amp feedback networks may be connected around the device  
to control gain, frequency response, etc. When the switch is  
opened the output will remain at its last level.  
• Gain Bandwidth Product . . . . . . . . . . . . . 2.5MHz (Typ)  
• Low Effective Aperture Delay Time . . . . . . . 30ns (Typ)  
• TTL Compatible Control Input  
±12V to ±15V Operation  
Applications  
Performance as a sample-and-hold compares very favorably  
with other monolithic, hybrid, modular, and discrete circuits.  
Accuracy to better than 0.01% is achievable over the  
temperature range. Fast acquisition is coupled with superior  
droop characteristics, even at high temperatures. High slew  
rate, wide bandwidth, and low acquisition time produce  
excellent dynamic characteristics. The ability to operate at  
gains greater than 1 frequently eliminates the need for  
external scaling amplifiers.  
• 12-Bit Data Acquisition  
• Digital to Analog Deglitcher  
• Auto Zero Systems  
• Peak Detector  
• Gated Operational Amplifier  
Ordering Information  
The device may also be used as a versatile operational  
amplifier with a gated output for applications such as analog  
switches, peak holding circuits, etc. For more information,  
please see Application Note AN517.  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
HA1-2420-2  
HA1-2425-5  
HA3-2425-5  
HA4P2425-5  
HA9P2425-5  
-55 to 125 14 Ld CERDIP  
F14.3  
0 to 75  
0 to 75  
0 to 75  
0 to 75  
14 Ld CERDIP  
14 Ld PDIP  
20 Ld PLCC  
14 Ld SOIC  
F14.3  
The MIL-STD-883 data sheet for this device is available on  
request.  
E14.3  
N20.35  
M14.15  
Pinouts  
HA-2420 (CERDIP)  
HA-2425 (CERDIP, PDIP, SOIC)  
TOP VIEW  
HA-2425  
(PLCC)  
TOP VIEW  
-IN  
1
2
3
4
5
6
7
14 S/H CONTROL  
13 GND  
3
2
1
20 19  
+IN  
4
5
OFFSET ADJ.  
OFFSET ADJ.  
V-  
12 NC  
18  
17  
16  
OFFSET ADJ.  
NC  
NC  
NC  
11 HOLD CAP.  
10 NC  
HOLD CAP.  
OFFSET ADJ.  
6
7
8
15 NC  
14 NC  
NC  
V-  
NC  
9
8
V+  
NC  
OUTPUT  
9
10 11 12 13  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2856.2  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
5-1  
HA-2420, HA-2425  
Absolute Maximum Ratings  
Thermal Information  
o
o
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 40V  
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V  
Digital Input Voltage (Sample and Hold Pin) . . . . . . . . . . +8V, -15V  
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
CERDIP Package . . . . . . . . . . . . . . . . . .  
PDIP Package . . . . . . . . . . . . . . . . . . . . .  
PLCC Package . . . . . . . . . . . . . . . . . . . .  
SOIC Package. . . . . . . . . . . . . . . . . . . . .  
90  
100  
75  
35  
N/A  
N/A  
120  
N/A  
o
Maximum Junction Temperature (Ceramic Packages) . . . . . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
Operating Conditions  
o
Temperature Range  
HA-2420-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
HA-2425-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C  
o
o
o
o
o
o
o
(PLCC and SOIC - Lead Tips Only)  
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±12V to ±15V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications Test Conditions (Unless Otherwise Specified) V  
= ±15.0V; C = 1000pF; Digital Input: V = +0.8V  
(Sample), V = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input)  
SUPPLY  
H
IL  
IH  
HA-2420-2  
TYP  
HA-2425-5  
TYP  
TEST  
CONDITIONS  
TEMP.  
( C)  
o
PARAMETER  
INPUT CHARACTERISTICS  
Input Voltage Range  
MIN  
MAX  
MIN  
MAX UNITS  
Full  
25  
±10  
-
2
-
4
±10  
-
3
-
6
V
Offset Voltage  
-
-
mV  
mV  
nA  
nA  
nA  
nA  
MΩ  
V
Full  
25  
-
3
6
-
4
8
Bias Current  
-
40  
-
200  
400  
50  
100  
-
-
40  
-
200  
400  
50  
100  
-
Full  
25  
-
-
Offset Current  
-
-
10  
-
-
-
10  
-
Full  
25  
Input Resistance  
5
10  
-
5
10  
-
Common Mode Range  
Full  
±10  
-
±10  
-
TRANSFER CHARACTERISTICS  
Large Signal Voltage Gain  
Common Mode Rejection  
R = 2k, V = 20V  
Full  
Full  
Full  
25  
80  
-
50  
90  
-
-
-
25  
74  
-
50  
90  
-
-
-
kV/V  
dB  
L
O
P-P  
V
= ±10V  
CM  
Hold Mode Feedthrough Attenuation  
(Note 2)  
f
100kHz  
-76  
-76  
dB  
IN  
Gain Bandwidth Product (Note 2)  
OUTPUT CHARACTERISTICS  
Output Voltage Swing  
25  
-
2.5  
-
-
2.5  
-
MHz  
R = 2kΩ  
Full  
25  
±10  
-
-
-
-
-
±10  
-
-
-
-
-
V
mA  
kHz  
L
Output Current  
±15  
-
±15  
-
Full Power Bandwidth (Note 2)  
Output Resistance  
V
= 20V  
P-P  
25  
-
-
100  
0.15  
-
-
100  
0.15  
O
DC  
25  
TRANSIENT RESPONSE  
Rise Time (Note 2)  
V
= 200mV  
V = 200mV  
O
25  
25  
25  
-
-
75  
25  
5
100  
40  
-
-
-
75  
25  
5
100  
40  
-
ns  
%
O
P-P  
Overshoot (Note 2)  
P-P  
Slew Rate (Note 2)  
V
= 10V  
3.5  
3.5  
V/µs  
O
P-P  
DIGITAL INPUT CHARACTERISTICS  
Digital Input Current  
V
V
= 0V  
= 5V  
Full  
Full  
Full  
Full  
-
-
-
-
-
-
-0.8  
20  
0.8  
-
-
-
-
-
-
-
-0.8  
20  
0.8  
-
mA  
µA  
V
IN  
IN  
Digital Input Voltage  
Low  
-
-
High  
2.0  
2.0  
V
SAMPLE AND HOLD CHARACTERISTICS  
Acquisition Time (Note 2) To 0.1% 10V Step  
25  
-
2.3  
4
-
2.3  
4
µs  
5-2  
HA-2420, HA-2425  
Electrical Specifications Test Conditions (Unless Otherwise Specified) V  
= ±15.0V; C = 1000pF; Digital Input: V = +0.8V  
IL  
(Sample), V = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued)  
SUPPLY  
H
IH  
HA-2420-2  
HA-2425-5  
TEST  
CONDITIONS  
TEMP.  
( C)  
o
PARAMETER  
Acquisition Time (Note 2)  
Hold Step Error  
MIN  
TYP  
3.2  
10  
860  
30  
30  
5
MAX  
MIN  
TYP  
3.2  
10  
860  
30  
30  
5
MAX UNITS  
To 0.01% 10V Step  
25  
25  
-
-
-
-
-
-
-
-
-
-
6
20  
-
-
-
-
-
-
-
-
-
-
-
6
µs  
mV  
ns  
V
= 0V  
20  
IN  
To ±1mV  
Hold Mode Settling Time  
Aperture Time (Note 3)  
Effective Aperture Delay Time  
Aperture Uncertainty  
Drift Current (Note 2)  
HA1-2420  
25  
-
25  
-
-
ns  
25  
-
-
ns  
25  
-
-
-
ns  
V
= 0V  
25  
5
-
5
pA  
nA  
nA  
nA  
IN  
Full  
Full  
Full  
1.8  
-
10  
-
-
-
HA1-2425  
0.1  
7.5  
1.0  
10.0  
HA3-2425, HA4P2425, HA9P2425  
POWER SUPPLY CHARACTERISTICS  
Supply Current (+)  
-
-
25  
25  
-
-
3.5  
2.5  
90  
5.5  
3.5  
-
-
-
3.5  
2.5  
90  
5.5  
3.5  
-
mA  
mA  
dB  
Supply Current (-)  
Power Supply Rejection  
NOTES:  
Full  
80  
74  
2. A = ±1, R = 2k, C = 50pF.  
V
L
L
3. Derived from computer simulation only; not tested.  
Functional Diagram  
OFFSET  
ADJUST  
V+  
9
3
4
1
7
-
-INPUT  
OUT  
-
+
+
2
+INPUT  
HA-2420/2425  
14  
S/H  
CONTROL  
11  
13  
GND  
5
V-  
HOLD  
CAPACITOR  
Test Circuits and Waveforms  
-IN  
OUTPUT  
HOLD  
SAMPLE  
INPUT  
S/H  
CONTROL  
S/H  
CONTROL  
HOLD  
CAP  
+IN  
GND  
OUTPUT  
C
H
V
STEP  
S/H CONTROL  
INPUT  
NOTE: Set rise/fall times of S/H Control to approximately 20ns.  
FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT  
FIGURE 2. HOLD STEP ERROR TEST  
5-3  
HA-2420, HA-2425  
Test Circuits and Waveforms (Continued)  
+5V  
EN  
HI-508A  
MUX  
SINE WAVE  
INPUT  
IN2  
IN1  
IN3  
IN4  
IN5  
IN6  
IN7  
IN8  
A2  
HA-2420/2425  
-IN  
V
O
OUT  
GND  
+IN  
OUT  
S/H  
HOLD  
HOLD  
S/H  
CONTROL CAP  
CONTROL  
SAMPLE  
C
V
H
INP-P  
OUTPUT  
A0  
A1  
V  
S/H CONTROL INPUT  
t  
NOTE: Compute hold mode feedthrough attenuation from the formula:  
HOLD  
V
OUT  
----------------------------------  
Feedthrough Attenuation = 20log  
V
HOLD  
IN  
NOTE: Measure the slope of the output during hold, V/t,  
and compute drift current from: I = C V/t.  
Where V  
OUT  
sinewave during the hold mode.  
HOLD = Peak-to-Peak value of output  
D
H
FIGURE 3. DRIFT CURRENT TEST  
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION  
Schematic Diagram  
OFFSET ADJ.  
V+  
R
R
Q
Q
1
2
64  
Q
89  
J
63  
Q
Q
58  
Q
Q
Q
29  
30  
65  
Q
Q
17  
23  
Q
5
Q
Q
106  
90  
Q
66  
Q
2
Q
72  
Q
4
82  
59  
Q
Q
Q
R
74  
45  
46  
J
R
61  
Q
P
73  
Q
Q
7
9
Q
91  
Q
105  
Q
87  
Q
51  
Q
Q
52  
Q
15  
Q
Q
6
C
7
Q
H
47  
Q
Q
Q
48  
11  
Q
53  
Q
54  
49  
Q
50  
27  
D
1
Q
75  
Q
19  
Q
20  
21  
Q
8
Q
31  
C
3
Q
R
32  
15pF  
9
Q
Q
100  
R
8
OUT  
Q
101  
Q
Q
3
24  
Q
Q
33 34  
Q
R
18  
10  
56  
Q
25  
Q
10  
Q
Q
38  
13  
Q
77  
S/H  
Q
Q
35  
76  
CONTROL  
Q
Q
55  
22  
Q
C
26  
4
Q
Q
83  
Q
69  
67  
GND  
J
60  
Q
68  
R
121  
Q
12  
Q
14  
GND  
Q
78  
J
86  
R
11  
Q
83  
Q
Q
Q
39  
40  
Q
Q
79  
70  
J
Q
57  
41  
Q
103  
Q
42  
43  
Q
102  
Q
44  
Q
Q
71  
Q
80  
62  
Q
16  
R
14  
R
13  
Q
81  
-IN  
+IN  
V-  
5-4  
HA-2420, HA-2425  
INPUT  
Application Information  
HOLD STEP VOLTAGE (mV)  
+10  
OUTPUT  
+IN  
-IN  
OUT  
S/H  
CONTROL  
5
R
F
-10  
-5  
+5  
+10  
S/H CONTROL  
INPUT  
R
I
0
R
F
DC INPUT VOLTAGE (V)  
NOTE: GAIN ~ 1 + -------  
0.002R  
I
-5  
R
I
C
= 0.1µF  
H
-10  
C
C
= 10,000pF  
= 1000pF  
H
H
FIGURE 7. NON-INVERTING CONFIGURATION  
-15  
-20  
-25  
-30  
-35  
Figure 8 shows a typical unity gain circuit, with Offset Zero-  
ing. All of the other normal op amp feedback configurations  
may be used with the HA-2420/2425. The input amplifier  
may be used as a gated amplifier by utilizing Pin 11 as the  
output. This amplifier has excellent drive capabilities along  
with exceptionally low switch leakage.  
C
= 100pF  
H
CONTROL  
FIGURE 5. HOLD STEP vs INPUT VOLTAGE  
V+  
Offset Adjustment  
C
H
The offset voltage of the HA-2420 and HA-2425 may be  
adjusted using a 100ktrim pot, as shown in Figure 8. The  
recommended adjustment procedure is:  
Apply 0V to the sample-and-hold input, and a square wave  
to the S/H control.  
-
+
-
+
Adjust the trim pot for 0V output in the hold mode.  
Gain Adjustment  
The linear variation in pedestal voltage with sample-and- hold  
OUT  
input voltage causes a -0.06% gain error (C = 1000pF). In  
IN  
100kΩ  
V-  
H
some applications (D/A deglitcher, A/D converter) the gain  
error can be adjusted elsewhere in the system, while in other  
applications it must be adjusted at the sample-and-hold. The  
two circuits shown below demonstrate how to adjust gain error  
at the sample-and-hold.  
OFFSET TRIM (±25mV RANGE)  
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)  
The method used to reduce leakage paths on the PC board  
and the device package is shown in Figure 9. This guard ring  
is recommended to minimize the drift during hold mode.  
The recommended procedure for adjusting gain error is:  
1. Perform offset adjustment.  
The hold capacitor should have extremely high insulation  
resistance and low dielectric absorption. Polystyrene (below  
2. Apply the nominal input voltage that should produce a  
+10V output.  
o
85 C), Teflon, or Parlene types are recommended.  
3. Adjust the trim pot for +10V output in the hold mode.  
For more applications, consult Intersil Application Note  
AN517, or the factory applications group.  
4. Apply the nominal input voltage that should produce a  
-10V output.  
CONTROL  
5. Measure the output hold voltage (V  
-10NOMINAL  
). Adjust  
GND  
the trim pot for an output hold voltage of  
-IN  
+IN  
(V10NOMINAL) + (-10V)  
HOLD  
CAPACITOR  
----------------------------------------------------------------------------  
2
R
0.002R  
OUT  
F
F
INPUT  
R
OUTPUT  
I
V-  
OUT  
-IN  
S/H  
CONTROL  
V+  
+IN  
R  
F
R
I
----------  
NOTE: GAIN  
S/H CONTROL INPUT  
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)  
FIGURE 6. INVERTING CONFIGURATION  
5-5  
HA-2420, HA-2425  
EADT may be positive, negative or zero. If zero, the S/H ampli-  
Glossary of Terms  
fier will output a voltage equal to V at the instant the Hold  
IN  
Acquisition Time  
command was received. For negative EADT, the output in Hold  
(exclusive of pedestal and droop errors) will correspond to a  
The time required following a “sample” command, for the output  
to reach its final value within ±0.1% or ±0.01%. This is the mini-  
mum sample time required to obtain a given accuracy, and  
includes switch delay time, slewing time and settling time.  
value of V that occurred before the Hold command.  
IN  
Aperture Uncertainty  
The range of variation in Effective Aperture Delay Time. Aper-  
ture Uncertainty (also called Aperture Delay Uncertainty,  
Aperture Time Jitter, etc.) sets a limit on the accuracy with  
which a waveform can be reconstructed from sample data.  
Aperture Time  
The time required for the sample-and-hold switch to open,  
independent of delays through the switch driver and input  
amplifier circuitry. The switch opening time is that interval  
between the conditions of 10% open and 90% open.  
Drift Current  
The net leakage current from the hold capacitor during the  
hold mode. Drift current can be calculated from the droop  
rate using the formula:  
Effective Aperture Delay Time (EADT)  
The difference between the digital delay time from the Hold  
command to the opening of the S/H switch, and the propaga-  
tion time from the analog input to the switch.  
V  
t  
-------  
I
(pA) = C (pF) ×  
(V s)  
D
H
Typical Performance Curves  
1000  
1000  
MIN. SAMPLE TIME  
FOR 0.1% ACCURACY  
10V SWINGS (µs)  
DRIFT DURING HOLD  
AT 25 C (mV/s)  
EQUIV. INPUT NOISE  
o
“SAMPLE” MODE - 100kΩ  
SOURCE RESISTANCE  
100  
10  
OUTPUT NOISE  
“HOLD” MODE  
UNITY GAIN PHASE  
MARGIN (DEGREES)  
HOLD STEP  
OFFSET  
100  
10  
1
ERROR (mV)  
1.0  
UNITY GAIN  
BANDWIDTH  
(MHz)  
EQUIV. INPUT NOISE  
“SAMPLE” MODE - 0Ω  
SOURCE RESISTANCE  
0.1  
SLEW RATE  
(V/µs)  
0.01  
10pF  
100pF  
1000pF  
0.01µF  
0.1µF  
1.0µF  
10  
100  
1K  
10K  
100K  
1M  
C
VALUE  
H
BANDWIDTH (LOWER 3dB FREQUENCY = 10Hz)  
FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE AS  
A FUNCTION OF HOLDING CAPACITOR  
FIGURE 11. BROADBAND NOISE CHARACTERISTICS  
1000  
100  
10  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
C
C
C
= 100pF  
= 1000pF  
= 0.01µF  
H
H
H
C
C
= 1.0µF  
= 0.1µF  
H
H
-10  
-20  
-30  
1
10  
100  
1K  
10K  
100K  
1M  
10M  
100M  
-50  
-25  
0
25  
50  
75  
100  
125  
o
TEMPERATURE ( C)  
FREQUENCY (Hz)  
FIGURE 12. DRIFT CURRENT vs TEMPERATURE  
FIGURE 13. OPEN LOOP FREQUENCY RESPONSE  
5-6  
HA-2420, HA-2425  
Typical Performance Curves (Continued)  
0
20  
C
= 0.01µF  
H
-30  
-40  
-50  
-60  
-70  
-80  
-90  
C
= 1.0µF  
H
C
= 1000pF  
C
= 1000pF  
H
H
C
100pF  
H
40  
60  
80  
100  
120  
140  
160  
180  
200  
220  
240  
C
= 0.1µF  
H
100  
1K  
10K  
100K  
1M  
10M  
10  
100  
1K  
10K  
100K  
1M  
10M  
100M  
±10V SINUSOIDAL INPUT FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 14. HOLD MODE FEED THROUGH ATTENUATION  
FIGURE 15. OPEN LOOP PHASE RESPONSE  
4V  
S/H  
SAMPLE  
HOLD  
CONTROL  
0V  
S/H  
S/H  
(5V/DIV.)  
(5V/DIV.)  
+10V  
0V  
V
OUT  
(2V/DIV.)  
V
OUT  
(2V/DIV.)  
0V  
-10V  
TIME (1µs/DIV.)  
TIME (1µs/DIV.)  
FIGURE 16. ACQUISITION TIME (C = 1000pF)  
FIGURE 17. ACQUISITION TIME (C = 1000pF)  
H
H
S/H  
(5V/DIV.)  
S/H  
(5V/DIV.)  
0V  
+1V  
OUT  
V
(0.5V/DIV.)  
V
OUT  
(0.5V/DIV.)  
-1V  
0V  
TIME (1µs/DIV.)  
TIME (1µs/DIV.)  
FIGURE 18. ACQUISITION TIME (C = 1000pF)  
FIGURE 19. ACQUISITION TIME (C = 1000pF)  
H
H
5-7  
HA-2420, HA-2425  
Typical Performance Curves (Continued)  
S/H  
(5V/DIV.)  
S/H  
(5V/DIV.)  
0.1V  
0V  
0V  
V
OUT  
V
OUT  
(50mV/DIV.)  
(50mV/DIV.)  
-0.1V  
TIME (500ns/DIV.)  
TIME (500ns/DIV.)  
FIGURE 20. ACQUISITION TIME (C = 1000pF)  
FIGURE 21. ACQUISITION TIME (C = 1000pF)  
H
H
5-8  
HA-2420, HA-2425  
Die Characteristics  
DIE DIMENSIONS:  
102 mils x 61 mils x 19 mils  
2590µm x 1550µm x 483µm  
PASSIVATION:  
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)  
Silox Thickness: 12kÅ ±2kÅ  
3
4
2
Nitride Thickness: 3.5kÅ ±1.5kÅ  
METALLIZATION:  
Type: Al, 1% Cu  
TRANSISTOR COUNT:  
Thickness: 16kÅ ±2kÅ  
78  
SUBSTRATE POTENTIAL:  
PROCESS:  
V-  
Bipolar Dielectric Isolation  
BACKSIDE FINISH:  
Gold, Nickel, Silicon, etc.  
Metallization Mask Layout  
HA-2420, HA-2425  
GND  
VOS ADJ  
VOS ADJ  
HOLD CAP  
V-  
V+  
OUTPUT  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
5-9  
配单直通车
HA9P2425-5产品参数
型号:HA9P2425-5
生命周期:Obsolete
零件包装代码:SOIC
针数:14
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.33.00.01
风险等级:5.79
Is Samacsys:N
最长采集时间:6 µs
标称采集时间:3.2 µs
放大器类型:SAMPLE AND HOLD CIRCUIT
最大模拟输入电压:10 V
最小模拟输入电压:-10 V
JESD-30 代码:R-PDSO-G14
负供电电压上限:-20 V
标称负供电电压 (Vsup):-15 V
功能数量:1
端子数量:14
最高工作温度:75 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
认证状态:Not Qualified
采样并保持/跟踪并保持:SAMPLE
子类别:Sample and Hold Circuit
供电电压上限:20 V
标称供电电压 (Vsup):15 V
表面贴装:YES
技术:BIPOLAR
温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING
端子位置:DUAL
Base Number Matches:1
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