HCPL-2630-500E全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

6N137, HCNW137, HCNW2601, HCNW2611, HCPL-0600,

HCPL-0601, HCPL-0611, HCPL-0630, HCPL-0631, HCPL-0661,

HCPL-2601, HCPL-2611, HCPL-2630, HCPL-2631, HCPL-4661

High CMR, High Speed TTL Compatible Optocouplers

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

Features

• 15 kV/µs minimum Common Mode Rejection (CMR)

at V_CM= 1 kV for HCNW2611, HCPL-2611, HCPL-4661,

HCPL-0611, HCPL-0661

• High speed: 10 MBd typical

• LSTTL/TTL compatible

• Low input current capability: 5 mA

• Guaranteed AC and DC performance over temper-

ature: -40 °C to +85 °C

The 6N137, HCPL-26xx/06xx/4661, HCNW137/26x1 are

optically coupled gates that combine a GaAsP light emit-

ting diode and an integrated high gain photo detector.

An enable input allows the detector to be strobed. The

output of the detector IC is an open collector Schottky-

clamped transistor. The internal shield provides a guar-

anteed common mode transient immunity speciﬁcation

up to 15,000 V/µs at V_cm= 1000 V.

This unique design provides maximum AC and DC circuit

isolation while achievingTTL compatibility. The optocou-

pler AC and DC operational parameters are guaranteed

from -40 °C to +85 °C allowing troublefree system per-

formance.

• Available in 8-Pin DIP, SOIC-8, widebody packages

• Strobable output (single channel products only)

• Safety approval

UL recognized - 3750 V_rmsfor 1 minute and 5000 V_rms

for 1 minute per UL1577 CSA approved

IEC/EN/DIN EN 60747-5-5 approved with

*

Functional Diagram

6N137, HCPL-2601/2611

HCPL-0600/0601/0611

HCPL-2630/2631/4661

HCPL-0630/0631/0661

V

_IORM= 567 V_peakfor 06xx Option 060

V_IORM= 630 V_peakfor 6N137/26xx Option 060

V_IORM=1414 V_peakfor HCNW137/26x1

1

2

V

ANODE 1

CATHODE 1

CATHODE 2

ANODE 2

1

2

V

8

7

8

7

NC

CC

E

CC

O1

O2

ANODE

• MIL-PRF-38534 hermetic version available

(HCPL-56xx/66xx)

V

CATHODE

NC

3

4

6

5

3

4

6

5

O

GND

Applications

SHIELD

• Isolated line receiver

TRUTH TABLE

(POSITIVE LOGIC)

• Computer-peripheral interfaces

• Microprocessor system interfaces

• Digital isolation for A/D, D/A conversion

• Switching power supply

• Instrument input/output isolation

• Ground loop elimination

• Pulse transformer replacement

• Power transistor isolation in motor drives

• Isolation of high speed logic systems

LED

ENABLE

OUTPUT

LED

OUTPUT

L

ON

H

L

NC

L

H

L

ON

OFF

ON

OFF

ON

OFF

H

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

*5000 V_rms/1 Minute rating is for HCNW137/26X1 and Option 020

(6N137, HCPL-2601/11/30/31, HCPL-4661) products only.

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

The6N137,HCPL-26xx,HCPL-06xx,HCPL-4661,HCNW137,

and HCNW26x1 are suitable for high speed logic interfac-

ing, input/output buﬀering, as line receivers in environ-

ments that conventional line receivers cannot tolerate

and are recommended for use in extremely high ground

or induced noise environments.

Selection Guide

Widebody

(400 Mil)

Minimum CMR

8-Pin DIP (300 Mil)

Small-Outline SO-8

Hermetic

Input

On-

Current Output

(mA)

Single

and Dual

Channel

Packages

Single

Channel

Package

Dual

Channel

Package

Single

Channel

Package

Dual

Channel

Package

Single

Channel

Package

dV/dt

(V/µs)

V

(V)

CM

Enable

YES

NO

1000

10

5

6N137

5,000

1,000

5

HCPL-0600

HCPL-0601

HCPL-0611

HCNW137

HCNW2601

HCNW2611

HCPL-2630

HCPL-2631

HCPL-4661

HCPL-0630

HCPL-0631

HCPL-0661

10,000

15,000

1,000

YES

NO

HCPL-2601

HCPL-2611

YES

NO

1,000

3, 500

1,000

50

300

50

YES

NO

HCPL-2602^[1]

HCPL-2612^[1]

HCPL-261A^[1]

3

HCPL-061A^[1]

HCPL-061N^[1]

HCPL-263A^[1]

HCPL-263N^[1]

HCPL-063A^[1]

HCPL-063N^[1]

1,000^[2]

1,000

50

YES

HCPL-261N^[1]

NO

[3]

12.5

HCPL-193x^[1]

HCPL-56xx^[1]

HCPL-66xx^[1]

Notes:

1. Technical data are on separate Avago publications.

2. 15 kV/µs with V_CM= 1 kV can be achieved using Avago application circuit.

3. Enable is available for single channel products only, except for HCPL-193x devices.

2

Ordering Information

HCPL-xxxx is UL Recognized with 3750 V_rmsfor 1 minute per UL1577.

HCNWxxxx is UL Rcognized with 5000 V_rmsfor 1 minute per UL1577.

Option

UL 5000 V_rms/

1 Minute

Rating

Part

Number

RoHS

Non RoHS

Compliant Compliant

Surface Gull Tape &

IEC/EN/DIN

EN 60747-5-5 Quantity

Package

Mount Wing

Reel

-000E

-300E

-500E

-020E

-320E

-520E

-060E

-560E

-000E

-300E

-500E

-020E

-320E

-520E

-060E

-360E

-000E

-300E

-500E

-020E

-320E

-520E

-060E

-360E

-560E

-000E

-300E

-500E

-020E

-320E

-520E

-000E

-300E

-500E

-020E

-320E

-520E

No option

#300

50 per tube

X

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

50 per tube

1000 per reel

#500

X

#020

X

6N137

300mil

DIP-8

#320

X

#520

X

#060

X

-560

X

No option

#300

X

#500

X

#020

X

300mil

DIP-8

HCPL-2601

#320

X

#520

#060

X

-

X

No option

#300

X

#500

X

#020

X

HCPL-2611

300mil

DIP-8

#320

X

#520

#060

X

#360

X

#560

No option

#300

X

#500

HCPL-2630

300mil

DIP-8

#020

X

#320

X

-520

No option

#300

X

#500

HCPL-2631

HCPL-4661

300mil

DIP-8

#020

X

#320

X

#520

3

Option

Non RoHS

Compliant Compliant

UL 5000 V_rms/

1 Minute

Rating

Part

Number

RoHS

Surface Gull Tape &

IEC/EN/DIN

EN 60747-5-5 Quantity

Package

Mount Wing

Reel

-000E

-500E

-060E

-560E

-000E

-500E

No option

#500

X

100 per tube

HCPL-0600

HCPL-0601

HCPL-0611

X

1500 per reel

100 per tube

1500 per reel

100 per tube

1500 per reel

SO-8

#060

X

#560

X

HCPL-0630

HCPL-0631

HCPL-0661

No option

#500

SO-8

X

-000E

-300E

-500E

No option

#300

X

42 per tube

750 per reel

HCNW137

HCNW2601

HCNW2611

400 mil

DIP-8

X

#500

X

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry. Combination of Option 020 and Option 060 is not available.

Example 1:

HCPL-2611-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packag

ing with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant.

Example 2:

HCPL-2630 to order product of 300mil DIP package in tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Notes:

The notation ‘#xxx’is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant option will use ‘-xxxE‘.

Schematic

HCPL-2630/2631/4661

HCPL-0630/0631/0661

6N137, HCPL-2601/2611

I

CC

I

HCPL-0600/0601/0611

V

CC

O1

8

7

HCNW137, HCNW2601/2611

I

F

1

+

I

F1

CC

V

O1

CC

O

8

6

2+

I

O

V

F1

–

2

V

F

SHIELD

–

3

–

GND

I

F2

5

I

O2

SHIELD

I

V

E

7

E

O2

6

5

V

F2

USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED

BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).

+

4

GND

SHIELD

4

Package Outline Drawings

8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)

7.63 0.35

(0.ꢀ00 0.010ꢁ

9.65 0.35

(0.ꢀ80 0.010ꢁ

8

1

7

6

5

6.ꢀ5 0.35

(0.350 0.010ꢁ

TYPE NUMBER

OPTION CODE*

DATE CODE

A XXXXZ

YYWW

U R

UL

3

ꢀ

4

RECOGNITION

1.78 (0.070ꢁ MAX.

1.19 (0.047ꢁ MAX.

+ 0.076

- 0.051

0.354

5° TYP.

+ 0.00ꢀꢁ

- 0.003ꢁ

ꢀ.56 0.1ꢀ

(0.140 0.005ꢁ

(0.010

4.70 (0.185ꢁ MAX.

0.51 (0.030ꢁ MIN.

DIMENSIONS IN MILLIMETERS AND (INCHESꢁ.

3.93 (0.115ꢁ MIN.

*MARKING CODE LETTER FOR OPTION NUMBERS

"L" = OPTION 030

"V" = OPTION 060

1.080 0.ꢀ30

(0.04ꢀ 0.01ꢀꢁ

0.65 (0.035ꢁ MAX.

OPTION NUMBERS ꢀ00 AND 500 NOT MARKED.

3.54 0.35

(0.100 0.010ꢁ

NOTE: FLOATING LEAD PROTRUSION IS 0.35 mm (10 milsꢁ MAX.

**JEDEC Registered Data (for 6N137 only).

8-pin DIP Package with Gull Wing Surface Mount Option 300

(6N137, HCPL-2601/11/30/31, HCPL-4661)

LAND PATTERN RECOMMENDATION

ꢁ.0ꢁ6 (0.040ꢂ

9.65 0.ꢀ5

(0.380 0.0ꢁ0ꢂ

6

5

8

ꢁ

7

6.350 0.ꢀ5

(0.ꢀ50 0.0ꢁ0ꢂ

ꢁ0.9 (0.430ꢂ

ꢀ.0 (0.080ꢂ

ꢀ

3

4

ꢁ.ꢀ7 (0.050ꢂ

9.65 0.ꢀ5

ꢁ.780

(0.070ꢂ

MAX.

(0.380 0.0ꢁ0ꢂ

ꢁ.ꢁ9

(0.047ꢂ

MAX.

7.6ꢀ 0.ꢀ5

(0.300 0.0ꢁ0ꢂ

+ 0.076

0.ꢀ54

- 0.05ꢁ

+ 0.003ꢂ

- 0.00ꢀꢂ

3.56 0.ꢁ3

(0.ꢁ40 0.005ꢂ

(0.0ꢁ0

ꢁ.080 0.3ꢀ0

(0.043 0.0ꢁ3ꢂ

0.635 0.ꢀ5

(0.0ꢀ5 0.0ꢁ0ꢂ

ꢁꢀ° NOM.

0.635 0.ꢁ30

(0.0ꢀ5 0.005ꢂ

ꢀ.54

(0.ꢁ00ꢂ

BSC

DIMENSIONS IN MILLIMETERS (INCHESꢂ.

LEAD COPLANARITY = 0.ꢁ0 mm (0.004 INCHESꢂ.

NOTE: FLOATING LEAD PROTRUSION IS 0.ꢀ5 mm (ꢁ0 milsꢂ MAX.

5

Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)

LAND PATTERN RECOMMENDATION

8

1

7

2

6

5

4

5.994 ꢀ.2ꢀ3

(ꢀ.236 ꢀ.ꢀꢀ8ꢁ

XXX

YWW

3.937 ꢀ.127

TYPE NUMBER

(LAST 3 DIGITSꢁ

DATE CODE

7.49 (0.295)

(ꢀ.155 ꢀ.ꢀꢀ5ꢁ

3

PIN ONE

1.9 (0.075)

ꢀ.4ꢀ6 ꢀ.ꢀ76

(ꢀ.ꢀ16 ꢀ.ꢀꢀ3ꢁ

1.27ꢀ

(ꢀ.ꢀ5ꢀꢁ

BSC

0.64 (0.025)

ꢀ.432

(ꢀ.ꢀ17ꢁ

*

7°

5.ꢀ8ꢀ ꢀ.127

(ꢀ.2ꢀꢀ ꢀ.ꢀꢀ5ꢁ

45° X

3.175 ꢀ.127

(ꢀ.125 ꢀ.ꢀꢀ5ꢁ

ꢀ ~ 7°

ꢀ.228 ꢀ.ꢀ25

(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ1ꢁ

1.524

(ꢀ.ꢀ6ꢀꢁ

ꢀ.2ꢀ3 ꢀ.1ꢀ2

(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4ꢁ

TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASHꢁ

5.2ꢀ7 ꢀ.254 (ꢀ.2ꢀ5 ꢀ.ꢀ1ꢀꢁ

*

ꢀ.3ꢀ5

(ꢀ.ꢀ12ꢁ

MIN.

DIMENSIONS IN MILLIMETERS (INCHESꢁ.

LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢁ MAX.

NOTE: FLOATING LEAD PROTRUSION IS ꢀ.15 mm (6 milsꢁ MAX.

8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)

11.ꢀꢀ

(ꢀ.433ꢁ

11.23 ꢀ.15

(ꢀ.442 ꢀ.ꢀꢀ6ꢁ

MAX.

9.ꢀꢀ ꢀ.15

(ꢀ.354 ꢀ.ꢀꢀ6ꢁ

7

6

5

8

TYPE NUMBER

DATE CODE

A

HCNWXXXX

YYWW

1

3

2

4

1ꢀ.16 (ꢀ.4ꢀꢀꢁ

TYP.

1.55

(ꢀ.ꢀ61ꢁ

MAX.

7° TYP.

+ ꢀ.ꢀ76

ꢀ.254

- ꢀ.ꢀꢀ51

+ ꢀ.ꢀꢀ3ꢁ

- ꢀ.ꢀꢀ2ꢁ

(ꢀ.ꢀ1ꢀ

5.1ꢀ

(ꢀ.2ꢀ1ꢁ

MAX.

3.1ꢀ (ꢀ.122ꢁ

3.9ꢀ (ꢀ.154ꢁ

ꢀ.51 (ꢀ.ꢀ21ꢁ MIN.

2.54 (ꢀ.1ꢀꢀꢁ

TYP.

1.8ꢀ ꢀ.15

(ꢀ.ꢀ71 ꢀ.ꢀꢀ6ꢁ

ꢀ.4ꢀ (ꢀ.ꢀ16ꢁ

ꢀ.56 (ꢀ.ꢀ22ꢁ

DIMENSIONS IN MILLIMETERS (INCHESꢁ.

NOTE: FLOATING LEAD PROTRUSION IS ꢀ.25 mm (1ꢀ milsꢁ MAX.

6

8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300

(HCNW137, HCNW2601/11)

11.23 0.1ꢀ

(0.442 0.00ꢁ6

LAND PATTERN RECOMMENDATION

7

ꢁ

ꢀ

8

9.00 0.1ꢀ

(0.3ꢀ4 0.00ꢁ6

13.56

(0.534)

1

3

2

4

2.29

(0.09)

1.3

(0.0ꢀ16

12.30 0.30

1.55

(0.061)

MAX.

(0.484 0.0126

11.00

MAX.

(0.4336

4.00

MAX.

(0.158)

1.80 0.15

(0.071 0.006)

1.00 0.1ꢀ

(0.039 0.00ꢁ6

0.7ꢀ 0.2ꢀ

(0.030 0.0106

+ 0.076

- 0.0051

2.54

(0.100)

BSC

0.254

+ 0.003)

- 0.002)

(0.010

DIMENSIONS IN MILLIMETERS (INCHES).

7° NOM.

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

Reﬂow Soldering Proﬁle

The recommended reﬂow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide ﬂux

should be used.

Regulatory Information

The 6N137, HCPL-26xx/06xx/46xx, and HCNW137/26xx have been approved by the following organizations:

UL

IEC/EN/DIN EN 60747-5-5

Recognized under UL 1577, Component Recognition

Program, File E55361.

CSA

Approved under CSA Component Acceptance Notice

#5, File CA 88324.

7

Insulation and Safety Related Speciﬁcations

8-pin DIP

(300 Mil)

Value

Widebody

(400 Mil)

Value

SO-8

Value

Parameter

Symbol

Unit

Conditions

Minimum External

Air Gap

(External Clearance)

L(101)

7.1

4.9

9.6

10.0

1.0

mm

Measured from input terminals

to output terminals, shortest

distance through air.

Minimum External

Tracking

(External Creepage)

L(102)

7.4

4.8

mm

Measured from input terminals

to output terminals, shortest

distance path along body.

Minimum Internal

Plastic Gap

(Internal Clearance)

0.08

Through insulation distance,

conductor to conductor, usually

the direct distance between the

photoemitter and photodetector

inside the optocoupler cavity.

Minimum Internal

Tracking

(Internal Creepage)

NA

4.0

mm

V

Measured from input terminals

to output terminals, along

internal cavity.

Tracking Resistance

(Comparative Tracking Index)

CTI

200

IIIa

200

IIIa

200

IIIa

DIN IEC 112/VDE 0303 Part 1

Isolation Group

Material Group

(DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classiﬁcation is Class A in accordance with CECC 00802.

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*

(HCPL-06xx Option 060 Only)

Description

Symbol

Characteristic

Unit

Installation classiﬁcation per DIN VDE 0110, Table 1

for rated mains voltage ≤ 150 V_rms

I-IV

for rated mains voltage ≤ 300 V_rms

for rated mains voltage ≤ 600 V_rms

Climatic Classiﬁcation

I-III

40/85/21

2

Pollution Degree (DIN VDE 0110/39)

Maximum Working Insulation Voltage

V

567

V_peak

IORM

Input-to-Output Test Voltage, Method b*

V_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

Partial Discharge < 5 pC

V_PR

1063

907

Input-to-Output Test Voltage, Method a*

V_IORMx 1.6 = V_PR, Type and Sample Test, t_m= 10 sec,

Partial Discharge < 5 pC

V_peak

Highest Allowable Overvoltage

(Transient Overvoltage, t_ini= 60 sec)

V_IOTM

6000

V_peak

Safety Limiting Values (Maximum values allowed in the event of a failure)

Case Temperature

Input Current**

Output Power**

T_S

I_S,INPUT

P_S,OUTPUT

150

600

°C

mA

mW

Insulation Resistance at T_S, V_IO= 500 V

R_S

≥10⁹

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-5, for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

8

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*

(HCPL-26xx; 46xx; 6N13x Option 060 Only)

Description

Symbol

Characteristic

Unit

Installation classiﬁcation per DIN VDE 0110, Table 1

for rated mains voltage ≤ 300 V_rms

for rated mains voltage ≤ 450 V_rms

Climatic Classiﬁcation

Pollution Degree (DIN VDE 0110/39)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

V_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

Partial Discharge < 5 pC

I-IV

40/85/21

2

V

630

V_peak

IORM

V_PR

1181

1008

6000

Input to Output Test Voltage, Method a*

V_IORMx 1.6 = V_PR, Type and sample test, t_m= 10 sec,

Partial Discharge < 5 pC

V_peak

Highest Allowable Overvoltage

(Transient Overvoltage, t_ini= 60 sec)

Safety Limiting Values (Maximum values allowed in the event of a failure)

Case Temperature

Input Current

Output Power

Insulation Resistance at T_S, V_IO= 500 V

V_IOTM

V_peak

T_S

I_S,INPUT

P_S,OUTPUT

175

230

600

≥10⁹

°C

mA

mW

R_S

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-5, for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application.

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*

(HCNW137/2601/2611 Only)

Description

Symbol

Characteristic

Unit

Installation classiﬁcation per DIN VDE 0110, Table 1

for rated mains voltage ≤ 600 V_rms

for rated mains voltage ≤ 1000 V_rms

Climatic Classiﬁcation

Pollution Degree (DIN VDE 0110/39)

Maximum Working Insulation Voltage

I-IV

I-III

40/85/21

2

V

1414

V_peak

IORM

Input to Output Test Voltage, Method b*

V_IORMx 1.875 = V_PR, 100% Production Test with t_m= 1 sec,

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V_IORMx 1.6 = V_PR, Type and sample test, t_m= 10 sec,

Partial Discharge < 5 pC

V_PR

2651

2262

8000

V_peak

Highest Allowable Overvoltage

(Transient Overvoltage, t_ini= 60 sec)

V_IOTM

V_peak

Safety Limiting Values (Maximum values allowed in the event of a failure)

Case Temperature

Input Current

Output Power

T_S

I_S,INPUT

P_S,OUTPUT

150

400

700

°C

mA

mW

Insulation Resistance at T_S, V_IO= 500 V

R_S

≥10⁹

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-5, for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application.

9

Absolute Maximum Ratings* (No Derating Required up to 85 °C)

Parameter

Symbol

Package**

Min.

-55

-40

Max.

125

85

Units

°C

Note

Storage Temperature

Operating Temperature^†

Average Forward Input Current

T_S

T

°C

A

I_F

Single 8-Pin DIP

Single SO-8

Widebody

20

mA

2

Dual 8-Pin DIP

Dual SO-8

15

1, 3

1

Reverse Input Voltage

Input Power Dissipation

V_R

P_I

8-Pin DIP, SO-8

Widebody

5

3

V

Widebody

40

7

mW

V

Supply Voltage

V

CC

(1 Minute Maximum)

Enable Input Voltage (Not to

Exceed V_CCby more than

500 mV)

V_E

Single 8-Pin DIP

Single SO-8

Widebody

V_CC+ 0.5

V

Enable Input Current

I_E

I_O

5

50

7

mA

V

Output Collector Current

Output Collector Voltage

1

V_O

P_O

Output Collector Power

Dissipation

Single 8-Pin DIP

Single SO-8

Widebody

85

mW

Dual 8-Pin DIP

Dual SO-8

60

1, 4

Lead Solder Temperature

(Through Hole Parts Only)

T_LS

8-Pin DIP

260 °C for 10 sec.,

1.6 mm below seating plane

Widebody

260 °C for 10 sec.,

up to seating plane

Solder Reﬂow Temperature

Proﬁle (Surface Mount Parts Only)

SO-8 and

Option 300

See Package Outline

Drawings section

*JEDEC Registered Data (for 6N137 only).

**Ratings apply to all devices except otherwise noted in the Package column.

†0 °C to 70 °C on JEDEC Registration.

Recommended Operating Conditions

Parameter

Symbol

Min.

0

Max.

250

15

Units

µA

mA

V

Input Current, Low Level

Input Current, High Level^[1]

Power Supply Voltage

Low Level Enable Voltage^†

High Level Enable Voltage^†

Operating Temperature

Fan Out (at R_L= 1 kΩ)^[1]

Output Pull-up Resistor

I_FL*

I_FH**

5

V

4.5

0

5.5

CC

V_EL

V_EH

T_A

0.8

V

2.0

-40

V

CC

85

5

°C

N

TTL Loads

R_L

330

4 k

Ω

*The oﬀ condition can also be guaranteed by ensuring that V_FL≤ 0.8 V.

**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20%

LED degradation guardband.

†For single channel products only.

10

Electrical Speciﬁcations

Over recommended temperature (T_A= -40 °C to +85 °C) unless otherwise speciﬁed. All Typicals at V_CC= 5 V, T_A= 25 °C.

All enable test conditions apply to single channel products only. See note 5.

Parameter

Sym.

Package

Min.

Typ.

Max.

Units

Test Conditions

Fig.

Note

High Level Output

Current

I_OH*

All

5.5

100

µA

V

_CC= 5.5 V, V_E= 2.0 V,

1

1, 6,

19

V = 5.5 V, I_F= 250 µA

O

Input Threshold

Current

I_TH

Single Channel

Widebody

Dual Channel

2.0

5.0

0.6

mA

V

_CC= 5.5 V, V_E= 2.0 V,

2, 3

19

1, 19

7

V_O= 0.6 V,

I_OL(Sinking) = 13 mA

2.5

Low Level Output

Voltage

V_OL*

8-Pin DIP

SO-8

Widebody

0.35

V_CC= 5.5 V, V_E= 2.0 V,

I_F= 5 mA,

I_OL(Sinking) = 13 mA

2, 3,

4, 5

0.4

High Level Supply

Current

I_CCH

Single Channel

7.0

6.5

10

10.0*

15

mA

V_E= 0.5 V

V_E= V_CC

Both

V = 5.5 V

CC

I_F= 0 mA

Dual Channel

Channels

Low Level Supply

Current

I_CCL

Single Channel

Dual Channel

9.0

8.5

13

13.0*

21

mA

V_E= 0.5 V

V_E= V_CC

Both

V = 5.5 V

I_F= 10 mA

8

CC

Channels

High Level Enable

Current

I_EH

I_EL*

V_EH

V_EL

V_F

Single Channel

-0.7

-0.9

-1.6

mA

V

V_CC= 5.5 V, V = 2.0 V

E

Low Level Enable

Current

V_CC= 5.5 V, V = 0.5 V

9

E

High Level Enable

Voltage

2.0

19

Low Level Enable

Voltage

0.8

V

Input Forward

Voltage

8-Pin DIP

SO-8

Widebody

1.4

1.3

1.25

1.2

1.5

1.75*

1.80

1.85

2.05

V

T_A= 25 °C

I_F= 10 mA

6, 7

1

1.64

Input Reverse

Breakdown

Voltage

BV *

8-Pin DIP

SO-8

Widebody

5

V

I_R= 10 µA

1

R

3

I_R= 100 µA, T_A= 25°C

Input Diode

Temperature

Coeﬃcient

DV /

8-Pin DIP

SO-8

Widebody

-1.6

mV/°C I_F= 10 mA

7

F

∆T

A

-1.9

60

Input Capacitance

C_IN

8-Pin DIP

SO-8

pF

f = 1 MHz, V_F= 0 V

Widebody

70

*JEDEC registered data for the 6N137. The JEDEC Registration speciﬁes 0 °C to +70 °C. Avago speciﬁes -40 °C to +85 °C.

11

Switching Speciﬁcations (AC)

Over Recommended Temperature (T = -40 °C to +85 °C), V_CC= 5 V, I_F= 7.5 mA unless otherwise speciﬁed.

A

All Typicals at T = 25 °C, V_CC= 5 V.

A

Parameter

Sym.

Package**

Min. Typ. Max.

Units

Test Conditions

Fig.

Note

Propagation Delay

Time to High

t_PLH

20

48

75*

100

ns

T = 25°C

R_L= 350 Ω

C_L= 15 pF

8, 9, 1, 10,

A

10

19

Output Level

Propagation Delay

Time to Low

Output Level

t_PHL

25

50

75*

100

ns

T = 25°C

1, 11,

19

A

Pulse Width

Distortion

|t_PHL- t_PLH

|

8-Pin DIP

SO-8

Widebody

3.5

35

8, 9, 13, 19

10,

11

40

Propagation Delay

Skew

t_PSK

t_r

ns

12, 13,

19

Output Rise

Time (10-90%)

24

10

30

12

1, 19

14

Output Fall

Time (90-10%)

t_f

Propagation Delay

Time of Enable

from V_EHto V_EL

t_ELH

Single Channel

R_L= 350 Ω,

C_L= 15 pF,

V_EL= 0 V, V_EH= 3 V

13,

14

Propagation Delay

Time of Enable

from V_ELto V_EH

t_EHL

20

ns

15

*JEDEC registered data for the 6N137.

**Ratings apply to all devices except otherwise noted in the Package column.

Parameter

Sym.

Device

Min.

Typ.

Units

Test Conditions

Fig.

Note

Logic High

Common

Mode

Transient

Immunity

|CM_H| 6N137

1,000 10,000 V/µs |V_CM| = 10 V

V_CC= 5 V, I_F= 0 mA,

V_O(MIN)= 2 V,

15

1, 16,

18, 19

HCPL-2630

HCPL-0600/0630

HCNW137

HCPL-2601/2631 10,000 15,000

HCPL-0601/0631

HCNW2601

5,000 10,000

|V_CM| = 1 kV

R_L= 350 Ω, T = 25 °C

A

HCPL-2611/4661 15,000 25,000

HCPL-0611/0661

HCNW2611

Logic Low

Common

Mode

Transient

Immunity

|CM_L| 6N137

HCPL-2630

1,000 10,000 V/µs |V_CM| = 10 V

V_CC= 5 V, I_F= 7.5 mA,

V_O(MAX)= 0.8 V,

15

1, 17,

18, 19

5,000 10,000

|V_CM| = 1 kV

HCPL-0600/0630

HCNW137

HCPL-2601/2631 10,000 15,000

HCPL-0601/0631

HCNW2601

HCPL-2611/4661 15,000 25,000

HCPL-0611/0661

R_L= 350 Ω, T = 25°C

A

HCNW2611

12

Package Characteristics

All Typicals at T = 25 °C.

A

Parameter

Sym.

Package

Min.

Typ.

Max.

Units

Test Conditions

45% RH, t = 5 s,

_I-O= 3 kV dc, T = 25 °C

Fig.

Note

Input-Output

Insulation

I_I-O*

Single 8-Pin DIP

Single SO-8

1

µA

20, 21

V

A

Input-Output

Momentary With-

stand Voltage**

V_ISO

8-Pin DIP, SO-8

Widebody

OPT 020†

3750

5000

V rms RH ≤ 50%, t = 1 min,

20, 21

20, 22

T = 25 °C

A

Input-Output

Resistance

R_I-O

8-Pin DIP, SO-8

Widebody

10¹²

10¹³

Ω

V_I-O= 500 V_dc

1, 20,

23

10¹²

10¹¹

T = 25 °C

A

T = 100 °C

A

Input-Output

Capacitance

C_I-O

I_I-I

8-Pin DIP, SO-8

Widebody

0.6

0.5

pF

f = 1 MHz, T = 25 °C

1, 20,

23

A

0.6

Input-Input

Insulation

Dual Channel

0.005

µA

RH ≤ 45%, t = 5 s,

24

V = 500 V

I-I

Leakage Current

Resistance

(Input-Input)

R_I-I

C_I-I

Dual Channel

10¹¹

Ω

24

Capacitance

(Input-Input)

Dual 8-Pin DIP

Dual SO-8

0.03

0.25

pF

f = 1 MHz

*JEDEC registered data for the 6N137. The JEDEC Registration speciﬁes 0 °C to 70 °C. Avago speciﬁes -40 °C to 85 °C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous volt-

age rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equipment

level safety speciﬁcation or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

†For 6N137, HCPL-2601/2611/2630/2631/4661 only.

Notes:

1. Each channel.

2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA.

3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.

4. Derate linearly above 80 °C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.

5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total

lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.

6. The JEDEC registration for the 6N137 speciﬁes a maximum I_OHof 250 µA. Avago guarantees a maximum I_OHof 100 µA.

7. The JEDEC registration for the 6N137 speciﬁes a maximum I_CCHof 15 mA. Avago guarantees a maximum I_CCHof 10 mA.

8. The JEDEC registration for the 6N137 speciﬁes a maximum I_CCLof 18 mA. Avago guarantees a maximum I_CCLof 13 mA.

9. The JEDEC registration for the 6N137 speciﬁes a maximum I_ELof –2.0 mA. Avago guarantees a maximum I_ELof -1.6 mA.

10. The t_PLHpropagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the

output pulse.

11. The t_PHLpropagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the

output pulse.

12. t_PSKis equal to the worst case diﬀerence in t_PHLand/or t_PLHthat will be seen between units at any given temperature and speciﬁed test conditions.

13. See application section titled“Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew”for more information.

14. The t_ELHenable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge

of the output pulse.

15. The t_EHLenable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge

of the output pulse.

16. CM_His the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V_O> 2.0 V).

17. CM_Lis the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V_O< 0.8 V).

18. For sinusoidal voltages, (|dV_CM| / dt)_max= πf_CMV_CM(p-p).

19. No external pull up is required for a high logic state on the enable input. If the V_Epin is not used, tying V_Eto V_CCwill result in improved CMR

performance. For single channel products only.

20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V_rmsfor one second (leakage detection

current limit, I_I-O≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-

5-5 Insulation Characteristics Table, if applicable.

22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second (leakage detection

current limit, I_I-O≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-

5-5 Insulation Characteristics Table, if applicable.

23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.

24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only

13

WIDEBODY

8-PIN DIP, SO-8

6

15

10

6

V

T

= 5 V

V

T

= 5 V

V

= 5.5 V

= 2.0 V*

= 250 µA

CC

= 25 °C

CC

= 25 °C

A

CC

O

E

A

5

4

3

2

5

4

3

2

I

F

* FOR SINGLE

CHANNEL

PRODUCTS

ONLY

R

= 350 Ω

= 1 KΩ

R

= 350 Ω

= 1 KΩ

L

R

L

5

0

R

= 4 KΩ

R

= 4 KΩ

L

1

0

1

0

1

2

3

4

6

-60 -40 -20

0

20 40 60 80 100

0

1

2

3

4

6

5

T

– TEMPERATURE – °C

I

– FORWARD INPUT CURRENT – mA

I

– FORWARD INPUT CURRENT – mA

A

F

Figure 1. Typical high level output current vs.

temperature

Figure 2. Typical output voltage vs. forward input current

8-PIN DIP, SO-8

6

WIDEBODY

6

V

= 5.0 V

V

= 5.0 V

CC

= 0.6 V

CC

= 0.6 V

O

5

4

3

2

5

4

3

2

R

= 350 Ω

L

R

= 1 KΩ

R = 350 Ω

L

R

= 1 KΩ

L

1

0

1

0

R

= 4 KΩ

R = 4 KΩ

L

-60 -40 -20

0

20 40

80 100

-60 -40 -20

0

20 40

80 100

60

T

– TEMPERATURE – °C

T

A

– TEMPERATURE – °C

A

Figure 3. Typical input threshold current vs. temperature

14

8-PIN DIP, SO-8

WIDEBODY

0.8

0.7

0.8

0.7

70

60

50

V

I

= 5.5 V * FOR SINGLE

V

I

= 5.5 V

CC

V

= 5.0 V

= 2.0 V*

= 0.6 V

* FOR SINGLE

CHANNEL

PRODUCTS ONLY

CC

E

F

CC

E

OL

= 2.0 V*

= 5.0 mA

CHANNEL

PRODUCTS ONLY

= 2.0 V

E

= 5.0 mA

F

0.6

0.5

0.4

0.3

0.2

0.6

0.5

0.4

0.3

0.2

I

= 16 mA

O

I

= 10-15 mA

F

I

= 16 mA

= 9.6 mA

I

= 12.8 mA

O

I

= 12.8 mA

= 6.4 mA

O

I

= 9.6 mA

I = 6.4 mA

O

I

O

I

= 5.0 mA

F

40

20

O

0.1

0

0.1

0

-60 -40 -20

0

20 40

80 100

-60 -40 -20

0

20 40

80 100

-60 -40 -20

0

20 40

80 100

60

T

– TEMPERATURE – °C

T

– TEMPERATURE – °C

T – TEMPERATURE – °C

A

Figure 4. Typical low level output voltage vs. temperature

Figure 5. Typical low level output current vs.

temperature

WIDEBODY

8-PIN DIP, SO-8

1000

T

A

= 25 ^o

C

T

= 25 °C

A

100

10

100

10

I

F

+

F

+

F

V

-

–

1.0

0.1

0.01

0.1

0.01

0.001

1.2

1.3

1.4

1.5

1.6

1.7

1.1

1.2

1.3

1.4

1.5

1.6

V

- FORWARD VOLTAGE - V

V

– FORWARD VOLTAGE – V

F

Figure 6. Typical input diode forward characteristic

WIDEBODY

8-PIN DIP, SO-8

-2.4

-2.3

-2.2

-2.0

-1.8

-1.6

-2.1

-2.0

-1.9

-1.8

-1.4

-1.2

0.1

1

10

100

0.1

1

10

100

I

– PULSE INPUT CURRENT – mA

I

– PULSE INPUT CURRENT – mA

F

Figure 7. Typical temperature coeﬃcient of forward voltage vs. input current

15

PULSE GEN.

= 50 Ω

Z

f

O

t

= t = 5 ns

r

SINGLE CHANNEL

DUAL CHANNEL

V

+5 V

I

F

I

F

PULSE GEN.

V

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CC

Z

= 50 Ω

O

R

L

t

= t = 5 ns

r

f

INPUT

MONITORING

NODE

OUTPUT V

O

MONITORING

NODE

0.1µF

BYPASS

R

L

0.1µF

BYPASS

OUTPUT V

MONITORING

NODE

INPUT

MONITORING

NODE

O

*C

L

R

C *

L

M

R

M

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

L

PROBE AND STRAY WIRING CAPACITANCE.

I

= 7.50 mA

= 3.75 mA

F

INPUT

I

F

t

PHL

PLH

OUTPUT

V

O

1.5 V

Figure 8. Test circuit for t_PHLand t_PLH

100

105

90

V

F

= 5.0 V

CC

= 7.5 mA

V

A

= 5.0 V

CC

I

T = 25°C

80

t

, R = 4 KΩ

t

, R = 4 KΩ

L

PLH

L

PLH

t

, R = 350 Ω

PHL

L

1 KΩ

4 KΩ

60

40

75

60

t

, R = 350 Ω

L

PLH

t

, R = 1 KΩ

L

PLH

t

, R = 1 KΩ

L

PLH

t

, R = 350 Ω

L

PLH

20

0

45

30

t

, R = 350 Ω

PHL

L

1 KΩ

4 KΩ

-60 -40 -20

0

20 40

80 100

60

5

7

9

11

13

15

I

– PULSE INPUT CURRENT – mA

T

– TEMPERATURE – °C

F

A

Figure 9. Typical propagation delay vs. tem-

perature

Figure 10. Typical propagation delay vs. pulse

input current

40

V

I

= 5.0 V

t

CC

= 7.5 mA

RISE

FALL

R

= 4 kΩ

L

F

30

20

10

0

V

I

= 5.0 V

CC

= 7.5 mA

R

= 4 kΩ

= 1 kΩ

300

290

60

F

L

R

= 350Ω

L

R

L

40

R

= 350 Ω

L

20

0

R

= 1 kΩ

L

= 350 Ω, 1 kΩ, 4 kΩ

20 40 60 80 100

L

0

-10

-60

-40 -20

0

20 40

80 100

-60 -40 -20

60

- TEMPERATURE - ^oC

T

– TEMPERATURE – °C

A

T

A

Figure 11. Typical pulse width distortion vs.

temperature

Figure 12. Typical rise and fall time vs. tempera-

ture

16

PULSE GEN.

= 50 Ω

Z

f

O

t

= t = 5 ns

r

INPUT V

E

MONITORING NODE

+5 V

V

3.0 V

1.5 V

1

2

3

4

8

7

6

5

CC

INPUT

V

7.5 mA

E

0.1 µF

BYPASS

R

L

I

F

t

EHL

ELH

OUTPUT V

MONITORING

NODE

O

OUTPUT

V

O

1.5 V

*C

L

GND

*C IS APPROXIMATELY 15 pF WHICH INCLUDES

L

PROBE AND STRAY WIRING CAPACITANCE.

Figure 13. Test circuit for t_EHLand t_ELH

120

V

= 5.0 V

= 3.0 V

= 0 V

CC

EH

EL

I

= 7.5 mA

F

90

60

t

, R = 4 kΩ

L

ELH

t

, R = 1 kΩ

ELH

L

30

0

t

, R = 350 Ω

ELH

L

t

, R = 350 Ω, 1 kΩ, 4 kΩ

EHL

L

-60 -40 -20

0

20 40 60 80 100

T

– TEMPERATURE – °C

A

Figure 14. Typical enable propagation delay vs.

temperature

I

F

SINGLE CHANNEL

DUAL CHANNEL

B

I

F

V

1

2

3

4

8

7

6

5

+5 V

V

CC

8

+5 V

1

2

3

4

CC

A

B

A

R

L

OUTPUT V

MONITORING

NODE

0.1 µF

BYPASS

O

R

7

6

5

L

V

FF

OUTPUT V

MONITORING

NODE

O

V

FF

0.1 µF

BYPASS

GND

V

CM

V

CM

+

–

+

–

PULSE

GENERATOR

= 50 Ω

PULSE

GENERATOR

= 50 Ω

Z

O

V

(PEAK)

CM

V

CM

0 V

5 V

SWITCH AT A: I = 0 mA

F

CM

H

V

O

V

(MIN.)

O

SWITCH AT B: I = 7.5 mA

F

V

(MAX.)

O

V

O

0.5 V

CM

L

Figure 15. Test circuit for common mode transient immunity and typical waveforms

17

HCPL-2611 OPTION 060

(mW)

HCNWXXXX

P (mW)

S

800

700

600

500

400

300

200

100

0

P

S

I

(mA)

I (mA)

S

800

700

600

500

400

300

200

100

0

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

0

25

T – CASE TEMPERATURE – °C

S

50 75 100 125 150 175

T

S

Figure 16. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-5

GND BUS (BACK)

V

BUS (FRONT)

NC

CC

ENABLE

OUTPUT

0.1µF

NC

10 mm MAX.

(SEE NOTE 5)

SINGLE CHANNEL

DEVICE ILLUSTRATED.

Figure 17. Recommended printed circuit board layout

18

SINGLE CHANNEL DEVICE

5 V

8

6

V

CC1

V

CC2

390 Ω

470 Ω

I

F

+

2

3

D1*

V

0.1 µF

BYPASS

F

–

5

GND 1

GND 2

SHIELD

V

E

7

1

2

*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.

DUAL CHANNEL DEVICE

CHANNEL 1 SHOWN

5 V

8

7

V

CC1

V

CC2

390 Ω

470 Ω

I

F

+

1

2

D1*

V

0.1 µF

BYPASS

F

–

5

GND 1

GND 2

SHIELD

1

2

Figure 18. Recommended TTL/LSTTL to TTL/LSTTL interface circuit

19

Propagation Delay, Pulse-Width Distortion and Propagation

Delay Skew

puts of a group of optocouplers are switched either ON

or OFF at the same time, t_PSKis the diﬀerence between

the shortest propagation delay, either t_PLHor t_PHL, and the

Propagation delay is a ﬁgure of merit which describes

how quickly a logic signal propagates through a sys-

tem. The propagation delay from low to high (t_PLH) is the

amount of time required for an input signal to propagate

to the output, causing the output to change from low to

high. Similarly, the propagation delay from high to low

(t_PHL) is the amount of time required for the input signal

to propagate to the output causing the output to change

from high to low (see Figure8).

longest propagation delay, either t_PLHor t_PHL

.

As mentioned earlier, t_PSKcan determine the maximum

parallel data transmission rate. Figure 20 is the timing

diagram of a typical parallel data application with both

the clock and the data lines being sent through opto-

couplers. The ﬁgure shows data and clock signals at the

inputs and outputs of the optocouplers. To obtain the

maximum data transmission rate, both edges of the

clock signal are being used to clock the data; if only one

edge were used, the clock signal would need to be twice

as fast.

Pulse-width distortion (PWD) results when t_PLHand t_PHL

diﬀer in value. PWD is deﬁned as the diﬀerence be-

tween t_PLHand t_PHLand often determines the maximum

data rate capability of a transmission system. PWD can

be expressed in percent by dividing the PWD (in ns) by

the minimum pulse width (in ns) being transmitted. Typi-

cally, PWD on the order of 20-30% of the minimum pulse

width is tolerable; the exact ﬁgure depends on the par-

ticular application (RS232, RS422, T-l, etc.).

Propagation delay skew represents the uncertainty of

where an edge might be after being sent through an

optocoupler. Figure 20 shows that there will be uncer-

tainty in both the data and the clock lines. It is important

that these two areas of uncertainty not overlap, other-

wise the clock signal might arrive before all of the data

outputs have settled, or some of the data outputs may

start to change before the clock signal has arrived. From

these considerations, the absolute minimum pulse width

that can be sent through optocouplers in a parallel appli-

cation is twice t_PSK. A cautious design should use a slightly

longer pulse width to ensure that any additional uncer-

tainty in the rest of the circuit does not cause a problem.

Propagation delay skew, t_PSK, is an important parameter to

consider in parallel data applications where synchroniza-

tion of signals on parallel data lines is a concern. If the

parallel data is being sent through a group of optocou-

plers, diﬀerences in propagation delays will cause the

data to arrive at the outputs of the optocouplers at diﬀer-

ent times. If this diﬀerence in propagation delays is large

enough, it will determine the maximum rate at which

parallel data can be sent through the optocouplers.

The t_PSKspeciﬁed optocouplers oﬀer the advantages of

guaranteed speciﬁcations for propagation delays, pulse-

width distortion and propagation delay skew over the

recommended temperature, input current, and power

supply ranges.

Propagation delay skew is deﬁned as the diﬀerence be-

tween the minimum and maximum propagation delays,

either t_PLHor t_PHL, for any given group of optocouplers

which are operating under the same conditions (i.e., the

same drive current, supply voltage, output load, and op-

erating temperature). As illustrated in Figure 19, if the in-

DATA

I

F

50%

INPUTS

CLOCK

1.5 V

V

O

I

50%

F

DATA

OUTPUTS

t

PSK

V

1.5 V

O

CLOCK

t

PSK

t

PSK

Figure 19. Illustration of propagation delay skew - t_PSK

Figure 20. Parallel data transmission example

20

For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

AV02-0940EN - April 16, 2013

型号:	HCPL-2630-500E
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	AGILENT TECHNOLOGIES INC
包装说明：	0.300 INCH, LEAD FREE, SURFACE MOUNT, DIP-8
Reach Compliance Code：	unknown
HTS代码：	8541.40.80.00
风险等级：	5.16
Is Samacsys：	N
其他特性：	UL RECOGNIZED, OPEN COLLECTOR
配置：	SEPARATE, 2 CHANNELS
最大正向电流：	0.015 A
最大绝缘电压：	3750 V
JESD-609代码：	e3
安装特点：	SURFACE MOUNT
元件数量：	2
最大通态电流：	0.05 A
最高工作温度：	85 °C
最低工作温度：	-40 °C
光电设备类型：	LOGIC IC OUTPUT OPTOCOUPLER
最大功率耗散：	0.06 W
标称响应时间：	1e-7 ns
子类别：	Optocoupler - IC Outputs
最小供电电压：	4.5 V
标称供电电压：	5.5 V
表面贴装：	YES
端子面层：	Tin (Sn)
Base Number Matches：	1

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