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产品型号HEF4046BP的概述

HEF4046BP芯片概述 HEF4046BP是一款集成电路，属于CMOS技术制造。该芯片主要用于相位锁定环路（PLL）和频率合成器的应用，广泛应用于通信、音频处理和信号处理系统。HEF4046BP内部集成了相位比较器、低通滤波器和振荡器等模块，使得该芯片在处理频率和相位信号时具备了良好的性能。该芯片具有相对较高的灵敏度与宽工作频率范围，使其成为高精度信号处理的首选设备。HEF4046BP在各种条件下表现出了高可靠性及稳定性，因而在工程应用中获得了广泛认可。 HEF4046BP详细参数 HEF4046BP芯片的主要技术参数如下： - 工作电压（VDD）：3V至15V - 最大工作频率：20MHz - 相位比较器类型：两相比较器 - 输入频率范围：宽输入范围，通常低于VDD的一半 - 锁定时间：通常小于0.5ms - 输出波形：指数小于实际频率三倍 - 功耗：通常在15V供电条件下的功...

产品型号HEF4046BP的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4046B

MSI

Phase-locked loop

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

DESCRIPTION

The HEF4046B is a phase-locked loop circuit that consists

of a linear voltage controlled oscillator (VCO) and two

different phase comparators with a common signal input

amplifier and a common comparator input. A 7 V regulator

(zener) diode is provided for supply voltage regulation if

necessary. For functional description see further on in this

data.

Fig.1 Functional diagram.

FAMILY DATA

HEF4046BP(N):

HEF4046BD(F):

HEF4046BT(D):

16-lead DIL; plastic

(SOT38-1)

See Family Specifications

16-lead DIL; ceramic (cerdip)

(SOT74)

I_DDLIMITS category MSI

See further on in this data.

16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

PINNING

1. Phase comparator pulse output

2. Phase comparator 1 output

3. Comparator input

4. VCO output

5. Inhibit input

6. Capacitor C1 connection A

7. Capacitor C1 connection B

8. V_SS

9. VCO input

10. Source-follower output

11. Resistor R1 connection

12. Resistor R2 connection

13. Phase comparator 2 output

14. Signal input

15. Zener diode input for regulated supply.

Fig.2 Pinning diagram.

factor to obtain the maximum lock range. The average

output voltage of the phase comparator is equal to ¹⁄₂V_DD

when there is no signal or noise at the signal input. The

average voltage to the VCO input is supplied by the

low-pass filter connected to the output of phase

comparator 1. This also causes the VCO to oscillate at the

centre frequency (f_o). The frequency capture range (2 f_c) is

defined as the frequency range of input signals on which

the PLL will lock if it was initially out of lock. The frequency

lock range (2 f_L) is defined as the frequency range of input

signals on which the loop will stay locked if it was initially

in lock. The capture range is smaller or equal to the lock

range.

FUNCTIONAL DESCRIPTION

VCO part

The VCO requires one external capacitor (C1) and one or

two external resistors (R1 or R1 and R2). Resistor R1 and

capacitor C1 determine the frequency range of the VCO.

Resistor R2 enables the VCO to have a frequency off-set

if required. The high input impedance of the VCO simplifies

the design of low-pass filters; it permits the designer a wide

choice of resistor/capacitor ranges. In order not to load the

low-pass filter, a source-follower output of the VCO input

voltage is provided at pin 10. If this pin (SF_OUT) is used, a

load resistor (R_SF) should be connected from this pin to

V_SS; if unused, this pin should be left open. The VCO

output (pin 4) can either be connected directly to the

comparator input (pin 3) or via a frequency divider. A LOW

level at the inhibit input (pin 5) enables the VCO and the

source follower, while a HIGH level turns off both to

minimize stand-by power consumption.

With phase comparator 1, the range of frequencies over

which the PLL can acquire lock (capture range) depends

on the low-pass filter characteristics and this range can be

made as large as the lock range. Phase comparator 1

enables the PLL system to remain in lock in spite of high

amounts of noise in the input signal. A typical behaviour of

this type of phase comparator is that it may lock onto input

frequencies that are close to harmonics of the VCO centre

frequency. Another typical behaviour is, that the phase

angle between the signal and comparator input varies

between 0° and 180° and is 90° at the centre frequency.

Figure 3 shows the typical phase-to-output response

characteristic.

Phase comparators

The phase-comparator signal input (pin 14) can be

direct-coupled, provided the signal swing is between the

standard HE4000B family input logic levels. The signal

must be capacitively coupled to the self-biasing amplifier

at the signal input in case of smaller swings. Phase

comparator 1 is an EXCLUSIVE-OR network. The signal

and comparator input frequencies must have a 50% duty

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

(1) Average output voltage.

Fig.3 Signal-to-comparator inputs phase

difference for comparator 1.

Figure 4 shows the typical waveforms for a PLL employing

phase comparator 1 in locked condition of f_o.

Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of f_o.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

Phase comparator 2 is an edge-controlled digital memory

network. It consists of four flip-flops, control gating and a

3-state output circuit comprising p and n-type drivers

having a common output node. When the p-type or n-type

drivers are ON, they pull the output up to V_DDor down to

V_SSrespectively. This type of phase comparator only acts

on the positive-going edges of the signals at SIGN_INand

COMP_IN. Therefore, the duty factors of these signals are

not of importance.

comparator inputs are equal in both phase and frequency.

At this stable point, both p and n-type drivers remain OFF

and thus the phase comparator output becomes an open

circuit and keeps the voltage at the capacitor of the

low-pass filter constant.

Moreover, the signal at the phase comparator pulse output

(PCP_OUT) is a HIGH level which can be used for indicating

a locked condition. Thus, for phase comparator 2 no phase

difference exists between the signal and comparator

inputs over the full VCO frequency range. Moreover, the

power dissipation due to the low-pass filter is reduced

when this type of phase comparator is used because both

p and n-type output drivers are OFF for most of the signal

input cycle. It should be noted that the PLL lock range for

this type of phase comparator is equal to the capture

range, independent of the low-pass filter. With no signal

present at the signal input, the VCO is adjusted to its

lowest frequency for phase comparator 2 . Figure 5 shows

typical waveforms for a PLL employing this type of phase

comparator in locked condition.

If the signal input frequency is higher than the comparator

input frequency, the p-type output driver is maintained ON

most of the time, and both the n and p-type drivers are

OFF (3-state) the remainder of the time. If the signal input

frequency is lower than the comparator input frequency,

the n-type output driver is maintained ON most of the time,

and both the n and p-type drivers are OFF the remainder

of the time. If the signal input and comparator input

frequencies are equal, but the signal input lags the

comparator input in phase, the n-type output driver is

maintained ON for a time corresponding to the phase

difference. If the comparator input lags the signal input in

phase, the p-type output driver is maintained ON for a time

corresponding to the phase difference. Subsequently, the

voltage at the capacitor of the low-pass filter connected to

this phase comparator is adjusted until the signal and

Fig.5 Typical waveforms for phase-locked loop employing phase comparator 2 in locked condition.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

Figure 6 shows the state diagram for phase comparator 2.

Each circle represents a state of the comparator. The

number at the top, inside each circle, represents the state

of the comparator, while the logic state of the signal and

comparator inputs are represented by a ‘0’ for a logic LOW

or a ‘1’ for a logic HIGH, and they are shown in the left and

right bottom of each circle.

The state diagram assumes, that only one transition on

either the signal input or comparator input occurs at any

instant. States 3, 5, 9 and 11 represent the condition at the

output when the p-type driver is ON, while states 2, 4, 10

and 12 determine the condition when the n-type driver is

ON. States 1, 6, 7 and 8 represent the condition when the

output is in its high impedance OFF state; i.e. both p and

n-type drivers are OFF, and the PCP_OUToutput is HIGH.

The condition at output PCP_OUTfor all other states is LOW.

The transitions from one to another result from either a

logic change at the signal input (S) or the comparator input

(C). A positive-going and a negative-going transition are

shown by an arrow pointing up or down respectively.

S ↑: 0 to 1 transition at the signal input.

C ↓ : 1 to 0 transition at the comparator input.

Fig.6 State diagram for comparator 2.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

DC CHARACTERISTICS

V_SS= 0 V

T_amb(°C)

+ 25

V_DD

SYMBOL

−40

+ 85

TYP. MAX. TYP. MAX. TYP. MAX.

Supply current

(note 1)

−

300

750

−

µA

I_D

−

Quiescent device

current (note 2)

150

300

600

I_DD

−

Notes

1. Pin 15 open; pin 5 at V_DD; pins 3 and 9 at V_SS; pin 14 open.

2. Pin 15 open; pin 5 at V_DD; pins 3 and 9 at V_SS; pin 14 at V_DD; input current pin 14 not included.

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; C_L= 50 pF; input transition times ≤ 20 ns

V_DD

SYMBOL MIN.

TYP.

MAX.

Phase comparators

Operating supply voltage

Input resistance

at SIGN_IN

V_DD

750

220

140

150

200

kΩ

at self-bias

operating point

10 R_IN

A.C. coupled input

sensitivity

peak-to-peak values;

R1 = 10 kΩ; R2 = ∞;

C1 = 100 pF; independent

of the lock range

10 V_IN

at SIGN_IN

D.C. coupled input sensitivity

at SIGN_IN; COMP_IN

LOW level

1,5

3,0

4,0

10 V_IL

full temperature range

3,5

7,0

HIGH level

10 V_IH

11,0

Input current

at SIGN_IN

µA

10 + I_IN

SIGN_INat V_DD

SIGN_INat V_SS

10 −I_IN

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4046B

MSI

Phase-locked loop

V_DD

SYMBOL MIN.

TYP.

MAX.

VCO

Operating supply

voltage

V_DD

as ﬁxed oscillator only

phase-locked loop operation

Power dissipation

150

2500

µW

MHz

%/°C

f_o= 10 kHz; R1 = 1 MΩ;

10 P

R2 = ∞; VCO_INat ¹⁄₂V_DD

;

HEF4046BP相关文章

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HEF4046BP产品参数

型号:	HEF4046BP
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	NXP SEMICONDUCTORS
包装说明：	DIP, DIP16,.3
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.65
其他特性：	WITH TWO PHASE COMPARATORS
模拟集成电路 - 其他类型：	PHASE LOCKED LOOP
JESD-30 代码：	R-PDIP-T16
长度：	21.6 mm
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5/15 V
认证状态：	Not Qualified
座面最大高度：	4.7 mm
子类别：	PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：	15 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm
Base Number Matches：	1

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