HGTG30N60B3D, HGT4E30N60B3DS
Test Circuit and Waveforms
HGTG30N60B3D
90%
OFF
10%
ON
V
GE
E
E
L = 1mH
V
CE
R
= 3Ω
G
90%
10%
d(OFF)I
+
-
I
CE
t
t
rI
V
= 480V
DD
t
fI
t
d(ON)I
FIGURE 19. INDUCTIVE SWITCHING TEST CIRCUIT
FIGURE 20. SWITCHING TEST WAVEFORMS
Handling Precautions for IGBTs
Operating Frequency Information
Insulated Gate Bipolar Transistors are susceptible to
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
gate-insulation damage by the electrostatic discharge of
energy through the devices. When handling these devices,
care should be exercised to assure that the static charge built
in the handler’s body capacitance is not discharged through
the device. With proper handling and application procedures,
however, IGBTs are currently being extensively used in
production by numerous equipment manufacturers in military,
industrial and consumer applications, with virtually no damage
problems due to electrostatic discharge. IGBTs can be
handled safely if the following basic precautions are taken:
frequency vs collector current (I ) plots are possible using
CE
the information shown for a typical unit in Figures 5, 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows f
or f
; whichever is smaller at each
MAX1
MAX2
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
f
is defined by f
= 0.05/(t ).
+ t
MAX1
MAX1
d(OFF)I d(ON)I
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting springs
or by the insertion into conductive material such as
“ECCOSORBD™ LD26” or equivalent.
2. When devices are removed by hand from their carriers, the
hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
are possible. t
and t are defined in Figure 20.
d(OFF)I
d(ON)I
Device turn-off delay can establish an additional frequency
limiting condition for an application other than T . t
JM d(OFF)I
is important when controlling output ripple under a lightly
loaded condition.
f
is defined by f
MAX2
= (P - P )/(E
OFF
+ E ). The
ON
MAX2
allowable dissipation (P ) is defined by P = (T T )/R
JM - C θJC
D
C
.
D
D
5. Gate VoltageRating - Never exceed the gate-voltagerating
The sum of device switching and conduction losses must not
exceed P . A 50% duty factor was used (Figure 3) and the
of V
. Exceeding the rated V can result in permanent
D
GEM
GE
conduction losses (P ) are approximated by P = (V
x I )/2.
are defined in the switching waveforms
damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are
essentially capacitors. Circuits that leave the gate
open-circuited or floating should be avoided. These
conditions can result in turn-on of the device due to voltage
buildup on the input capacitor due to leakage currents or
pickup.
7. Gate Protection - These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate
protection is required an external Zener is recommended.
C
C
CE CE
E
and E
OFF
ON
shown in Figure 20. E
is the integral of the instantaneous
ON
x V ) during turn-on and E
power loss (I
CE
is the
CE
integral of the instantaneous power loss (I
OFF
x V ) during
CE
CE
turn-off. All tail losses are included in the calculation for
; i.e., the collector current equals zero (I = 0).
E
OFF
CE
©2001 Fairchild Semiconductor Corporation
HGTG30N60B3D, HGT4E30N60B3DS Rev. B1