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产品型号HI2300的Datasheet PDF文件预览

HI2300  
8-Bit, 18 MSPS, Video A/D Converter  
with 3.3V Power Supply Operation  
August 1997  
Features  
Description  
1
• Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit ± / LSB (DL)  
2
The HI2300 is an 8-bit, CMOS A/D converter for video with  
synchronizing clamp function and can operate on 3.3V  
power supply. The adoption of 2 step-parallel method  
achieves ultra-low power consumption and a maximum  
conversion speed of 18 MSPS.  
• Maximum Sampling Frequency . . . . . . . . . . . 18 MSPS  
• Low Power Consumption at 18 MSPS (Typ)  
(Reference Current Excluded) . . . . . . . . . . . . . . .18mW  
• Synchronizing Clamp Function  
Ordering Information  
• Clamp ON/OFF Function  
PART  
NUMBER  
TEMP.  
RANGE ( C)  
• Reference Voltage Self-Bias Circuit  
o
PACKAGE  
PKG. NO.  
• Input CMOS Compatible  
HI2300JCQ  
-40 to 85  
32 Ld MQFP  
Q32.7x7-S  
• Three-State TTL Compatible Output  
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 3.3V Single  
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . .8pF  
• Reference Impedance . . . . . . . . . . . . . . . . . . 330(Typ)  
• Direct Replacement for Sony CXD2300  
Applications  
• Portable Equipment  
• Hand-Held Instruments  
Pinout  
HI2300  
(MQFP)  
TOP VIEW  
3231 30 29 28 27 26 25  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
V
RB  
1
2
3
4
5
6
7
8
24  
AV  
AV  
V
SS  
SS  
23  
22  
21  
20  
19  
18  
17  
IN  
AV  
AV  
DD  
DD  
V
V
RT  
RTS  
9 10 11 12 13 14 15 16  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
File Number 4103.1  
4-1230  
HI2300  
Functional Block Diagram  
DV  
SS  
28  
OE 30  
REFERENCE  
SUPPLY  
25  
24  
V
V
RBS  
RB  
DV  
SS  
31  
D0 (LSB)  
D1  
1
2
3
23 AV  
22 AV  
SS  
SS  
LOWER SAMPLING  
LOWER ENCODER  
(4-BIT)  
LOWER  
DATA  
COMPARATOR (4-BIT)  
LATCH  
D2  
21  
V
IN  
D3  
D4  
4
5
LOWER SAMPLING  
20 AV  
19 AV  
LOWER ENCODER  
(4-BIT)  
DD  
DD  
COMPARATOR (4-BIT)  
D5  
D6  
6
7
8
UPPER  
DATA  
18  
17  
V
V
RT  
UPPER ENCODER  
(4-BIT)  
UPPER SAMPLING  
LATCH  
COMPARATOR (4-BIT)  
RTS  
D7 (MSB)  
16 AV  
DD  
DV  
10  
11  
DD  
TEST  
(DV  
)
DD  
CLOCK  
GENERATOR  
CLK 12  
-
+
TEST  
9
15 CLP  
TEST  
(OPEN)  
14  
(V  
OR V  
OR V  
)
)
NC 32  
DD  
SS  
TEST  
13  
M - M  
(V  
DD  
SS  
29  
27  
26  
CLE  
CCP  
V
REF  
4-1231  
HI2300  
Pin Descriptions  
PIN NUMBER  
SYMBOL  
EQUIVALENT CIRCUIT  
DESCRIPTION  
1 to 8  
D0 to D7  
D0 (LSB) to D7 (MSB) Output.  
Di  
9
TEST  
Leave open during normal usage.  
DV  
DD  
9
DV  
SS  
10  
12  
DV  
Digital +3.3V.  
Clock Input.  
DD  
CLK  
DV  
DD  
12  
DV  
SS  
11, 13, 14  
TEST  
Fix Pin 11 to V , Pins 13 and 14 to V  
DD  
or  
DD  
V
during normal usage.  
SS  
DV  
DD  
11  
13  
14  
DV  
SS  
15  
Inputs Clamp Pulse to Pin 15 (CLP). Clamps  
the signal voltage during Low interval.  
CLP  
DV  
DD  
15  
DV  
SS  
16, 19, 20  
17  
AV  
Analog +3.3V  
DD  
V
Generates approximately +1.8V when shorted  
RTS  
AV  
DD  
with V  
RT  
.
17  
18  
24  
V
Reference Voltage (Top).  
RT  
AV  
DD  
V
Reference Voltage (Bottom).  
RB  
18  
24  
AV  
SS  
4-1232  
HI2300  
Pin Descriptions (Continued)  
PIN NUMBER  
SYMBOL  
EQUIVALENT CIRCUIT  
DESCRIPTION  
21  
V
Analog Input.  
IN  
AV  
DD  
21  
AV  
SS  
25  
26  
V
V
Generates approximately +0.4V when shorted  
with V  
BRS  
AV  
SS  
.
RB  
25  
Clamp Reference Voltage Input. Clamps so  
that the reference voltage and the input signal  
during clamp interval are equal.  
REF  
AV  
DD  
26  
AV  
AV  
SS  
27  
CCP  
Integrates the clamp control voltage. The  
relationship between the changes in CCP  
DD  
voltage and in V voltage is positive phase.  
IN  
27  
AV  
SS  
28, 31  
29  
DV  
SS  
Digital Ground.  
CLE  
The clamp function is enabled when  
CLE = Low.  
DV  
DD  
The clamp function is set to off and the  
converter functions as a normal A/D converter  
when CLE = High.  
The clamp pulse can be measured by  
29  
connecting CLE to DV  
through  
a
DD  
several-hundred-ohm resistor.  
CLAMP  
PULSE  
DV  
SS  
30  
OE  
Data is output when OE = Low. Pins D0 to D7  
are at high impedance when OE = High.  
DV  
DD  
30  
DV  
SS  
32  
NC  
No Connect pin.  
4-1233  
HI2300  
o
Absolute Maximum Ratings  
T
= 25 C  
Thermal Information  
A
o
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V  
Thermal Resistance (Typical, Note 1)  
θJA ( C/W)  
DD  
Reference Voltage (V , V ). . . . . . . . . .V  
RT RB  
+0.5V to V - 0.5V  
SS  
DD  
DD  
DD  
DD  
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
122  
o
Input Voltage, Analog (V ) . . . . . . . . . . . .V  
+0.5V to V - 0.5V  
IN  
SS  
o
o
Input Voltage, Digital (V , V ) . . . . . . . . .V  
IH IL  
+0.5V to V - 0.5V  
SS  
o
Output Voltage, Digital (V , V ) . . . . . .V  
+0.5V to V - 0.5V  
OH OL  
SS  
(MQFP - Lead Tips Only)  
Recommended Operating Conditions  
o
o
Temperature Range (t  
) . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
Analog Input (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V  
RT  
OPR  
RB  
) . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min)  
Supply Voltage (IDV - AV I). . . . . . . . . . . . . . . . . . . 0 to 100mV  
Power Supply (DV , DV )(AV , AV ). . . . . . . . .3.14V to 4.0V  
DD SS DD SS  
Clock Pulse width (t  
SS SS  
PW1  
PW0  
(t  
). . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min)  
Reference Input Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . . 0.4V  
RB  
(V ) . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V  
RT  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications When using a single power supply; f = 18 MSPS, V = 3.3V, V = 0V, V = 1.5V,  
C
DD  
RB  
RT  
o
T = 25 C  
A
PARAMETER  
Maximum Conversion Rate  
Minimum Conversion Rate  
Supply Current  
SYMBOL  
TEST CONDITIONS  
= 0 to 1.5V  
MIN  
18  
-
TYP  
32  
32  
5.5  
4.6  
-.9  
8
MAX  
-
UNITS  
MSPS  
MSPS  
mA  
mA  
dB  
f
Max  
Min  
V
C
IN  
= 1kHz Ramp  
f
f
0.5  
10  
6.6  
-
C
I
IN  
= 18 MSPS, NTSC Ramp Wave Input  
C
f
-
DD  
Reference Pin Current  
Analog Input Band Width  
Analog Input Capacitance  
I
3.3  
-
REF  
BW  
V
= 1.4V , 17.9MHz  
P-P  
IN  
IN  
C
V
= 0.75V + 0.07 V  
RMS  
-
-
pF  
IN  
Reference Resistance (V to V  
RT  
)
R
V
230  
0.33  
1.30  
-45  
40  
2.5  
-
330  
0.36  
1.39  
-25  
60  
-
440  
0.39  
1.48  
-5  
RB  
REF  
RB1  
Self Bias I  
Shorts V  
and V  
V
RB  
Shorts V and V  
RBS  
V
- V  
V
RT1  
RB1  
RT  
RTS  
Offset Voltage  
E
mV  
mV  
V
OT  
E
80  
-
OB  
Digital Input Voltage  
Digital Input Current  
Digital Output Current  
Digital Output Current  
Output Data Delay  
V
IH  
V
-
0.5  
5
V
IL  
I
V
= Max  
V
V
V
V
V
V
= V  
DD  
-
-
µA  
IH  
DD  
IH  
I
= 0V  
-
-
-
µA  
IL  
IL  
I
OE = V  
= V  
DD  
- 0.5V  
-1.0  
3.3  
-
-
-
mA  
mA  
µA  
OH  
SS  
= Min  
OH  
OL  
OH  
OL  
V
DD  
OE = V  
I
= 0.4V  
-
-
OL  
I
= V  
-
16  
16  
30  
OZH  
DD  
= Max  
DD  
= 0V  
V
DD  
I
-
-
µA  
OZL  
t
With TTL 1 Gate and 10pF Load  
8
18  
ns  
DL  
Three-State Output Enable Time  
t
t
R
= 1k, C = 20pF, OE = 3V0V  
L
PZH  
L
t
PZL  
PHZ  
Three-State Output Disable Time  
R
= 1k, C = 20pF, OE = 0V3V  
L
L
t
PLZ  
Integral Nonlinearity Error  
E
f
V
= 18 MSPS  
-
-
+0.5  
±1.3  
±0.5  
LSB  
LSB  
L
C
= 0 to 1.5V  
IN  
Differential Nonlinearity Error  
E
f
= 18 MSPS  
±0.3  
D
C
V
= 0 to 1.5V  
IN  
Aperture Jitter  
t
-
-
30  
4
-
-
ps  
ns  
AJ  
Sampling Delay  
Clamp Offset Voltage  
t
SD  
E
V
= DC  
V
V
= 0.5V  
= 1.5V  
-20  
-30  
-
0
+20  
+10  
-
mV  
mV  
ns  
OC  
IN  
REF  
REF  
PWS = 3µs  
-10  
25  
Clamp Pulse Delay  
t
CPD  
4-1234  
HI2300  
Digital Output  
The following table shows the relationship between analog  
input voltage and digital output code.  
DIGITAL OUTPUT CODE  
INPUT SIGNAL  
VOLTAGE  
STEP  
MSB  
LSG  
V
0
1
1
1
1
1
1
1
1
RT  
127  
128  
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
255  
0
0
0
0
0
0
0
0
RB  
Timing Chart  
t
t
PW0  
PW1  
CLOCK  
ANALOG INPUT  
N
N + 1  
N + 2  
N - 1  
N +3  
N + 4  
N - 1  
N - 3  
N - 2  
N
DATA OUTPUT  
t
D
t
= 18ns  
D
: Analog Sampling Point  
4-1235  
HI2300  
Typical Application Circuits  
+3.3V (DIGITAL)  
HC04  
CLOCK IN  
0.1µ  
CK  
Q
LATCH  
(NOTE 2)  
CLAMP PULSE IN  
OPEN  
9
16 15 14 13 12 11 10  
0.01µ  
+3.3V (ANALOG)  
17  
18  
19  
20  
21  
22  
23  
24  
8
7
6
5
4
3
2
1
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
VIDEO IN  
10µ  
75Ω  
+
0.1µ  
10p  
0.01µ  
+3.3V  
(ANALOG)  
25 26 27 28 29 30 31 32  
V
REF  
0.01µ  
20K  
GND (DIGITAL)  
GND (ANALOG)  
NOTE:  
1. The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operaiotn. However, slight small beat  
may be generated as Vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such  
time, the latch circuit is efective in this case.  
FIGURE 1. WHEN CLAMP IS USED (SELF BIAS)  
+3.3V (DIGITAL)  
HC04  
0.1µ  
CLOCK IN  
OPEN  
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0.01µ  
+3.3V (ANALOG)  
17  
18  
19  
20  
21  
22  
23  
24  
CLAMP LEVEL  
SETTING DATA  
SUBTRACTER,  
COMPARATOR,  
ETC.  
VIDEO IN  
10µ  
75Ω  
+
0.1µ  
10p  
0.01µ  
25 26 27 28 29 30 31 32  
DAC,  
PWM,  
ETC.  
0.01µ  
GND (DIGITAL)  
INFORMATION OTHER THAN  
CLAMP INTERVAL IS AT  
HIGH IMPEDANCE.  
GND (ANALOG)  
NOTES:  
2. The relationship between the changes in CCP voltage (Pin 27) and in V voltage is positive phase.  
IN  
3. V /V  
IN CCP  
= 3.0 (f = 20 MSPS).  
S
FIGURE 2. DIGITAL CLAMP (SELF BIAS)  
4-1236  
HI2300  
Typical Application Circuits (Continued)  
+3.3V (DIGITAL)  
HCO4  
0.1µ  
CLOCK IN  
OPEN  
9
16 15 14 13 12 11 10  
17  
8
7
6
5
4
3
2
1
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0.01µ  
+3.3V  
(ANALOG)  
18  
19  
20  
21  
22  
23  
24  
VIDEO IN  
75  
0.1µ  
10p  
0.01µ  
25 26 27 28 29 30 31 32  
+3.3V (DIGITAL)  
GND (ANALOG)  
GND (DIGITAL)  
FIGURE 3. WHEN CLAMP IS NOT USED (SELF BIAS)  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate  
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which  
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
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4-1237  
配单直通车
HI2220V801R-00产品参数
型号:HI2220V801R-00
生命周期:Obsolete
包装说明:2220
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8504.50.80.00
风险等级:5.42
外壳代码:2220
构造:Chip Bead
最大直流电阻:0.01 Ω
滤波器类型:FERRITE CHIP
最大频率:1000 MHz
最小频率:100 MHz
高度:3.45 mm
长度:5.59 mm
制造商序列号:HI
材料:Ferrite
安装类型:SURFACE MOUNT
功能数量:1
最高工作温度:125 °C
最低工作温度:-55 °C
输出阻抗:800 OHM Ω
包装方法:TAPE AND REEL
物理尺寸:L5.59XB5.08XH3.45 (mm)/L0.22XB0.2XH0.136 (inch)
额定电流:8 A
额定电压:75 V
系列:HI SERIES
子类别:Other Filters
宽度:5.08 mm
Base Number Matches:1
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