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产品型号HI5731BIB的概述

芯片HI5731BIB的概述 HI5731BIB是一款由华大半导体（HuaDa Semiconductor）生产的高精度、低功耗的模拟前端芯片，专为各种数据采集与转换应用而设计。其主要应用领域包括但不限于医疗设备、工业控制、消费电子和自动化系统等。该芯片采用优化的架构设计，提供高达16位的分辨率，能够在多种工作条件下保持稳定的性能，满足现代电子设备对高精度和高速度的要求。芯片HI5731BIB的详细参数 HI5731BIB是一款高性能的模数转换器（ADC），其主要技术参数包括： - 分辨率：16位 - 采样率：最高可达1 MSPS - 输入范围：支持单端和差分输入 - 功耗：典型功耗为5 mW，处于待机状态时可降至1 µW - 供电电压：支持3.0V至5.0V的宽范围供电 - 接口：支持SPI和I2C两种通信协议，便于与微控制器或处理器的连接 - 温度范围：工作温度范围为-40°C至...

产品型号HI5731BIB的Datasheet PDF文件预览

HI5731

Data Sheet

May 2000

File Number 4070.6

12-Bit, 100 MSPS, High Speed D/A

Converter

Features

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 100 MSPS

• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW

• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB

• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s

• TTL/CMOS Compatible Inputs

The HI5731 is a 12-bit, 100 MSPS, D/A converter which is

implemented in the Intersil BiCMOS 10V (HBC-10) process.

Operating from +5V and -5.2V, the converter provides

-20.48mA of full scale output current and includes an input

data register and bandgap voltage reference. Low glitch

energy and excellent frequency domain performance are

achieved using a segmented architecture. The digital inputs

are TTL/CMOS compatible and translated internally to ECL.

All internal logic is implemented in ECL to achieve high

switching speed with low noise. The addition of laser

trimming assures 12-bit linearity is maintained along the

entire transfer curve.

• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns

• Excellent Spurious Free Dynamic Range

Applications

• Cellular Base Stations

• GSM Base Stations

Ordering Information

• Wireless Communications

• Direct Digital Frequency Synthesis

• Signal Reconstruction

TEMP.

PART NUMBER RANGE ( C)

PACKAGE

28 Ld PDIP

28 Ld SOIC

PKG. NO.

E28.6

HI5731BIP

HI5731BIB

HI5731-EVS

-40 to 85

M28.3

• Test Equipment

Evaluation Board (SOIC)

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

Pinout

HI5731

(PDIP, SOIC)

TOP VIEW

D11 (MSB)

DGND

D10

27 AGND

26 REF OUT

25 CTRL OUT

24 CTRL IN

23 R

SET

22 AV

OUT

21 I

OUT

19 ARTN

18 DV

D2 10

D1 11

17 DGND

16 DV

D0 (LSB) 12

NC 13

15 CLOCK

NC 14

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-1

HI5731

Typical Application Circuit

+5V

HI5731

0.01µF

(16)

D11 (MSB) (1)

D10 (2)

D9 (3)

D11

0.1µF

D10

(24) CTRL IN

(25) CTRL OUT

D8 (4)

-5.2V (AV

)

D7 (5)

(26) REF OUT

D6 (6)

D5 (7)

D/A OUT

(21) I

OUT

64Ω

D4 (8)

D3 (9)

64Ω

D2 (10)

(20) I

OUT

D1 (11)

(23) R

SET

D0 (LSB) (12)

976Ω

(19) ARTN

(27) AGND

CLK (15)

50Ω

DGND (17, 28)

(22) AV

DV (18)

0.01µF

0.1µF

0.01µF

0.1µF

- 5.2V (AV

)

- 5.2V (DV

)

Functional Block Diagram

(LSB) D0

8 LSBs

CURRENT

CELLS

R2R

NETWORK

DATA

BUFFER/

LEVEL

12-BIT

MASTER

ARTN

SLAVE

SHIFTER

227Ω

D10

UPPER

4-BIT

DECODER

SWITCHED

CURRENT

CELLS

OUT

(MSB) D11

OUT

REF CELL

CTRL

CLK

25Ω

OVERDRIVEABLE

VOLTAGE

CTRL

OUT

REFERENCE

AGND DV

DGND DV

REF OUT

SET

3-2

HI5731

Absolute Maximum Ratings

Thermal Information

Digital Supply Voltage V

to DGND . . . . . . . . . . . . . . . . . . . +5.5V

Thermal Resistance (Typical, Note 1)

( C/W)

Negative Digital Supply Voltage DV to DGND . . . . . . . . . . -5.5V

Negative Analog Supply Voltage AV to AGND, ARTN . . . . . -5.5V

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DV

to -0.5V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA

Voltage from CTRL IN to AV . . . . . . . . . . . . . . . . . . . . 2.5V to 0V

Control Ampliﬁer Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA

Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AV

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

(SOIC - Lead Tips Only)

) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

Analog Output Current (I

OUT

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal

REF

T = 25 C for All Typical Values

HI5731BI

= -40 C TO 85 C

PARAMETER

SYSTEM PERFORMANCE

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Resolution

0.75

0.5

1.5

1.0

0.05

Bits

LSB

µA

Integral Linearity Error, INL

Differential Linearity Error, DNL

(Note 4) (“Best Fit” Straight Line)

(Note 4)

Offset Error, I

(Note 4)

Full Scale Gain Error, FSE

Offset Drift Coefficient

(Notes 2, 4)

(Note 3)

µA/ C

Full Scale Output Current, I

20.48

Output Voltage Compliance Range

DYNAMIC CHARACTERISTICS

Throughput Rate

(Note 3)

-1.25

100

MSPS

Output Voltage Full Scale Step

To ±0.5 LSB Error Band R = 50Ω

Settling Time, t

SETT

, Full Scale

(Note 3)

Singlet Glitch Area, GE (Peak)

Doublet Glitch Area, (Net)

Output Slew Rate

= 50Ω (Note 3)

pV-s

V/µs

R = 50Ω, DAC Operating in Latched Mode (Note 3)

1,000

675

470

Output Rise Time

R = 50Ω, DAC Operating in Latched Mode (Note 3)

Output Fall Time

R = 50Ω, DAC Operating in Latched Mode (Note 3)

Spurious Free Dynamic Range within a Window

(Note 3)

= 10 MSPS, f

= 20 MSPS, f

= 40 MSPS, f

= 50 MSPS, f

= 80 MSPS, f

= 1.23MHz, 2MHz Span

= 5.055MHz, 2MHz Span

= 16MHz, 10MHz Span

= 10.1MHz, 2MHz Span

= 5.1MHz, 2MHz Span

dBc

CLK

OUT

= 100 MSPS, f

= 10.1MHz, 2MHz Span

OUT

Spurious Free Dynamic Range to Nyquist

(Note 3)

= 40 MSPS, f

= 80 MSPS, f

= 2.02MHz, 20MHz Span

= 2.02MHz, 40MHz Span

OUT

= 100 MSPS, f

OUT

= 2.02MHz, 50MHz Span

REFERENCE/CONTROL AMPLIFIER

Internal Reference Voltage, V

REF

(Note 4)

(Note 3)

-1.27

-1.23

175

-1.17

Internal Reference Voltage Drift

µV/ C

Internal Reference Output Current Sink/Source

Capability

-125

+50

µA

3-3

HI5731

Electrical Speciﬁcations AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal

REF

T = 25 C for All Typical Values (Continued)

HI5731BI

= -40 C TO 85 C

PARAMETER

Internal Reference Load Regulation

Input Impedance at REF OUT pin

Amplifier Large Signal Bandwidth (0.6V

Amplifier Small Signal Bandwidth (0.1V

Reference Input Impedance

TEST CONDITIONS

= -125µA

MIN

TYP

MAX

UNITS

µV

= 0 to I

REF

(Note 3)

1.4

kΩ

)

Sine Wave Input, to Slew Rate Limited (Note 3)

Sine Wave Input, to -3dB Loss (Note 3)

(Note 3)

MHz

kΩ

P-P

)

P-P

Reference Input Multiplying Bandwidth (CTL IN)

= 50Ω, 100mV Sine Wave, to -3dB Loss at I

200

MHz

OUT

(Note 3)

DIGITAL INPUTS (D9-D0, CLK, INVERT)

Input Logic High Voltage, V

(Note 4)

(Note 3)

2.0

Input Logic Low Voltage, V

0.8

400

700

Input Logic Current, I

µA

Digital Input Capacitance, C

3.0

TIMING CHARACTERISTICS

Data Setup Time, t

See Figure 1 (Note 3)

3.0

0.5

2.0

0.25

4.5

Data Hold Time, t

HLD

Propagation Delay Time, t

CLK Pulse Width, t , t

POWER SUPPLY CHARACTERISTICS

3.0

PW1 PW2

(Note 4)

650

EEA

EED

CCD

Power Dissipation

Power Supply Rejection Ratio

NOTES:

µA/V

±5%, V ±5%

2. Gain Error measured as the error in the ratio between the full scale output current and the current through R

ratio should be 16.

(typically 1.28mA). Ideally the

SET

3. Parameter guaranteed by design or characterization and not production tested.

4. All devices are 100% tested at 25 C. 100% production tested at temperature extremes for military temperature devices, sample tested for

industrial temperature devices.

5. Dynamic Range must be limited to a 1V swing within the compliance range.

Timing Diagrams

50%

CLK

GLITCH AREA =

/ (H x W)

D11-D0

HEIGHT (H)

± / LSB ERROR BAND

OUT

t(ps)

WIDTH (W)

SETT

FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM

FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT

METHOD

3-4

HI5731

Timing Diagrams (Continued)

PW2

PW1

50%

CLK

HLD

D11-D0

OUT

FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

Typical Performance Curves

-1.21

680

CLOCK FREQUENCY DOES NOT

ALTER POWER DISSIPATION

-1.23

-1.25

-1.27

640

600

560

-1.29

-50

-30

-10

-50

-30

-10

TEMPERATURE

FIGURE 4. TYPICAL POWER DISSIPATION OVER

TEMPERATURE

FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER

TEMPERATURE

3-5

HI5731

Typical Performance Curves (Continued)

1.5

0.8

0.4

0.5

-0.5

1.5

0.0

-0.4

-0.8

400

1000

1600

2200

2800

3400

4000

600

1200

1800

2400

3000

3600

4200

CODE

FIGURE 6. TYPICAL INL

FIGURE 7. TYPICAL DNL

ATTEN 20dB

RL -10.0dBm

∆MKR -87.33dB

-73kHz

10dB/

= 10 MSPS

CENTER 1.237MHz

SPAN 2.000MHz

-40

-20

-0

100

TEMPERATURE

FIGURE 8. OFFSET CURRENT OVER TEMPERATURE

FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc

ATTEN 20dB

RL -10.0dBm

∆MKR -76.16dB

ATTEN 20dB

RL -10.0dBm

∆MKR -75.17dB

-53kHz

10dB/

-70kHz

= 20 MSPS

= 40 MSPS

CENTER 5.055MHz

SPAN 2.000MHz

CENTER 16.00MHz

SPAN 10.00MHz

FIGURE 10. SPURIOUS FREE DYNAMIC RANGE = 76.16dBc

FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc

3-6

HI5731

Typical Performance Curves (Continued)

ATTEN 20dB

RL -10.0dBm

∆MKR -81.67dB

-953kHz

ATTEN 20dB

RL -10.0dBm

∆MKR -77.00dB

-93kHz

10dB/

= 50 MSPS

= 80 MSPS

CENTER 10.100MHz

SPAN 2.000MHz

CENTER 5.097MHz

SPAN 2.000MHz

FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc

FIGURE 13. SPURIOUS FREE DYNAMIC RANGE = 77dBc

ATTEN 20dB

RL -10.0dBm

∆MKR -85.60dB

ATTEN 20dB

RL -10.0dBm

∆MKR -85.50dB

-33kHz

10dB/

73kHz

10dB/

= 100 MSPS

CENTER 2.027MHz

SPAN 2.000MHz

CENTER 5.000MHz

SPAN 2.000MHz

FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc

FIGURE 15. SPURIOUS FREE DYNAMIC RANGE = 85.5dBc

ATTEN 20dB

RL -10.0dBm

∆MKR -80.50dB

ATTEN 20dB

RL -10.0dBm

∆MKR -72.17dB

-807kHz

-467kHz

10dB/

= 100 MSPS

CENTER 10.133MHz

SPAN 2.000MHz

CENTER 26.637MHz

SPAN 2.000MHz

FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc

FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc

3-7

HI5731

Typical Performance Curves (Continued)

ATTEN 20dB

RL -10.0dBm

∆MKR -71.16dB

2.99MHz

ATTEN 20dB

RL -10.0dBm

∆MKR -70.50dB

1.98MHz

10dB/

= 40 MSPS

= 80 MSPS

= 2.02MHz

START FREQUENCY 500kHz

STOP FREQUENCY 20MHz

START FREQUENCY 500kHz

STOP FREQUENCY 40MHz

FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc

FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc

ATTEN 20dB

RL -10.0dBm

∆MKR -70.00dB

4.13MHz

10dB/

= 100 MSPS

= 2.02MHz

START FREQUENCY 500kHz

STOP FREQUENCY 50MHz

FIGURE 20. SPURIOUS FREE DYNAMIC RANGE = 70dBc

Pin Descriptions

PIN NUMBER

PIN NAME

PIN DESCRIPTION

1-12

D11 (MSB) thru Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.

D0 (LSB)

13, 14

CLK

Data Clock Pin DC to 100 MSPS.

No Connect.

Digital Logic Supply +5V.

Digital Ground.

DGND

17, 28

-5.2V Logic supply.

External resistor to set the full scale output current. I = 16 x (V

/ R

REF OUT

). Typically 976Ω.

SET

AGND

ARTN

Analog Ground supply current return pin.

Analog Signal Return for the R/2R ladder.

Current Output Pin.

OUT

Complementary Current Output Pin.

-5.2V Analog Supply.

CTRL IN

CTRL OUT

REF OUT

Input to the current source base rail. Typically connected to CTRL OUT and a 0.1µF capacitor to AV . Allows

external control of the current sources.

Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that

= 16 x (V

/ R ).

SET

REF OUT

-1.23V (Typ) bandgap reference voltage output. Can sink up to 125µA or be overdriven by an external

reference capable of delivering up to 2mA.

3-8

HI5731

Detailed Description

The HI5731 is a 12-bit, current out D/A converter. The DAC can

convert at 100 MSPS and runs on +5V and -5.2V supplies. The

architecture is an R/2R and segmented switching current cell

arrangement to reduce glitch. Laser trimming is employed to

tune linearity to true 12-bit levels. The HI5731 achieves its low

power and high speed performance from an advanced

HI5731

DAC

= 50Ω

CLK

= 50Ω

FIGURE 21. CLOCK LINE TERMINATION

BiCMOS process. The HI5731 consumes 650mW (typical) and

has an improved hold time of only 0.25ns (typical). The HI5731

is an excellent converter for use in communications

Rise and Fall times and propagation delay of the line will be

affected by the Shunt Terminator. The terminator should be

connected to DGND.

applications and high performance instrumentation systems.

Digital Inputs

Noise Reduction

The HI5731 is a TTL/CMOS compatible D/A. Data is latched

by a Master register. Once latched, data inputs D0 (LSB)

thru D11 (MSB) are internally translated from TTL to ECL.

The internal latch and switching current source controls are

implemented in ECL technology to maintain high switching

speeds and low noise characteristics.

To reduce power supply noise, separate analog and digital

power supplies should be used with 0.1µF and 0.01µF

ceramic capacitors placed as close to the body of the

HI5731 as possible on the analog (AV ) and digital (DV

supplies. The analog and digital ground returns should be

connected together back at the device to ensure proper

)

EE EE

Decoder/Driver

operation on power up. The V

power pin should also be

decoupled with a 0.1µF capacitor.

The architecture employs a split R/2R ladder and

Segmented Current source arrangement. Bits D0 (LSB) thru

D7 directly drive a typical R/2R network to create the binary

weighted current sources. Bits D8 thru D11 (MSB) pass thru

a “thermometer” decoder that converts the incoming data

into 15 individual segmented current source enables. This

split architecture helps to improve glitch, thus resulting in a

more constant glitch characteristic across the entire output

transfer function.

Reference

The internal reference of the HI5731 is a -1.23V (typical)

bandgap voltage reference with 175µV/ C of temperature

drift (typical). The internal reference is connected to the

Control Ampliﬁer which in turn drives the segmented current

cells. Reference Out (REF OUT) is internally connected to

the Control Ampliﬁer. The Control Ampliﬁer Output (CTRL

OUT) should be used to drive the Control Ampliﬁer Input

Clocks and Termination

(CTRL IN) and a 0.1µF capacitor to analog V . This

improves settling time by providing an AC ground at the

current source base node. The Full Scale Output Current is

The internal 12-bit register is updated on the rising edge of

the clock. Since the HI5731 clock rate can run to 100 MSPS,

to minimize reﬂections and clock noise into the part proper

termination should be used. In PCB layout clock runs should

be kept short and have a minimum of loads. To guarantee

consistent results from board to board controlled impedance

PCBs should be used with a characteristic line impedance

controlled by the REF OUT pin and the set resistor (R

SET

The ratio is:

(Full Scale) = (V

/R ) x 16,

REF OUT SET

OUT

The internal reference (REF OUT) can be overdriven with a

more precise external reference to provide better

performance over temperature. Figure 22 illustrates a typical

external reference conﬁguration.

of 50Ω.

To terminate the clock line, a shunt terminator to ground is

the most effective type at a 100 MSPS clock rate. A typical

value for termination can be determined by the equation:

HI5731

R = Z ,

-1.25V

(26) REF OUT

for the termination resistor. For a controlled impedance

board with a Z of 50Ω, the R = 50Ω. Shunt termination is

best used at the receiving end of the transmission line or as

close to the HI5731 CLK pin as possible.

-5.2V

FIGURE 22. EXTERNAL REFERENCE CONFIGURATION

3-9

HI5731

Multiplying Capability

TABLE 1. CAPACITOR SELECTION

The HI5731 can operate in two different multiplying

conﬁgurations. For frequencies from DC to 100kHz, a signal

of up to 0.6V

as shown in Figure 23.

can be applied directly to the REF OUT pin

P-P

100kHz

>1MHz

0.01µF

1µF

0.001µF

0.1µF

HI5731

Also, the input signal must be limited to 1V

P-P

distortion in the DAC output current caused by excessive

modulation of the internal current sources.

to avoid

CTRL OUT

CTRL IN

0.01µF

Outputs

REF OUT

RSET

The outputs I

OUT

and I

are complementary current

OUT

(OPTIONAL)

outputs. Current is steered to either I

or I

OUT

proportion to the digital input code. The sum of the two

currents is always equal to the full scale current minus one

LSB. The current output can be converted to a voltage by

using a load resistor. Both current outputs should have the

same load resistor (64Ω typically). By using a 64Ω load on

FIGURE 23. LOW FREQUENCY MULTIPLYING BANDWIDTH

CIRCUIT

The signal must have a DC value such that the peak

negative voltage equals -1.25V. Alternately, a capacitor can

be placed in series with REF OUT if DC multiplying is not

required. The lower input bandwidth can be calculated using

the following formula:

the output, a 50Ω effective output resistance (R

) is

OUT

achieved due to the 227Ω (±15%) parallel resistance seen

looking back into the output. This is the nominal value of the

R2R ladder of the DAC. The 50Ω output is needed for

matching the output with a 50Ω line. The load resistor should

be chosen so that the effective output resistance (R

matches the line resistance. The output voltage is:

)

OUT

-------------------------------------------

(2π)(1400)(f

)

= I

OUT

x R .

OUT

For multiplying frequencies above 100kHz, the CTRL IN pin

can be driven directly as seen in Figure 24.

OUT

is deﬁned in the reference section. I

is not trimmed

OUT

to 12 bits, so it is not recommended that it be used in

conjunction with I in a differential-to-single-ended

HI5731

CTRL OUT

OUT

application. The compliance range of the output is from -

200Ω

1.25V to 0V, with a 1V

range.

voltage swing allowed within this

P-P

CTRL IN

TABLE 2. INPUT CODING vs CURRENT OUTPUT

50Ω

INPUT CODE (D11-D0)

1111 1111 1111

(mA)

OUT

-20.48

FIGURE 24. HIGH FREQUENCY MULTIPLYING BANDWIDTH

CIRCUIT

1000 0000 0000

-10.24

-20.48

0000 0000 0000

The nominal input/output relationship is deﬁned as:

∆V

Settling Time

-------------

∆I

OUT

80Ω

The settling time of the HI5731 is measured as the time it

takes for the output of the DAC to settle to within a / LSB

In order to prevent the full scale output current from

exceeding 20.48mA, the R resistor must be adjusted

according to the following equation:

error band of its ﬁnal value during a full scale (code 0000...

to 1111.... or 1111... to 0000...) transition. All claims made by

Intersil with respect to the settling time performance of the

HI5731 have been fully veriﬁed by the National Institute of

Standards and Technology (NIST) and are fully traceable.

SET

16V

REF

-----------------------------------------------------------------------------------------------

SET

IN(PEAK)

80Ω

-----------------------------

(FULL SCALE) –

OUT

Glitch

The circuit in Figure 24 can be tuned to adjust the lower

cutoff frequency by adjusting capacitor values. Table 1 below

illustrates the relationship.

The output glitch of the HI5731 is measured by summing the

area under the switching transients after an update of the

DAC. Glitch is caused by the time skew between bits of the

incoming digital data. Typically, the switching time of digital

inputs are asymmetrical meaning that the turn off time is

3-10

HI5731

faster than the turn on time (TTL designs). Unequal delay

paths through the device can also cause one current source

to change before another. In order to minimize this, the

Intersil HI5731 employes an internal register, just prior to the

current sources, which is updated on the clock edge. Lastly,

the worst case glitch on traditional D/A converters usually

occurs at the major transition (i.e., code 2047 to 2048).

However, due to the split architecture of the HI5731, the

glitch is moved to the 255 to 256 transition (and every

subsequent 256 code transitions thereafter). This split R/2R

segmented current source architecture, which decreases the

amount of current switching at any one time, makes the

glitch practically constant over the entire output range. By

making the glitch a constant size over the entire output

range this effectively integrates this error out of the end

application.

buffered to create the bipolar offset current needed to

generate the -2V output with all bits ‘off’. The output current

must be converted to a voltage and then gained up and

offset to produce the proper swing. Care must be taken to

compensate for the voltage swing and error.

5kΩ

REF OUT

(26)

5kΩ

60Ω

CA2904

0.1µF

240Ω

HI5731

50Ω

OUT

(21)

In measuring the output glitch of the HI5731 the output is

terminated into a 64Ω load. The glitch is measured at any

one of the current cell carry (code 255 to 256 transition or

any multiple thereof) throughout the DACs output range.

HFA1100

FIGURE 27. BIPOLAR OUTPUT CONFIGURATION

Interfacing to the HSP45106 NCO-16

The glitch energy is calculated by measuring the area under

the voltage-time curve. Figure 26 shows the area considered

as glitch when changing the DAC output. Units are typically

speciﬁed in picoVolt-seconds (pV-s).

The HSP45106 is a 16-bit, Numerically Controlled Oscillator

(NCO). The HSP45106 can be used to generate various

modulation schemes for Direct Digital Synthesis (DDS)

applications. Figure 28 shows how to interface an HI5731 to

the HSP45106.

HI5731

Interfacing to the HSP45102 NCO-12

100MHz

SCOPE

The HSP45102 is a 12-bit, Numerically Controlled Oscillator

(NCO). The HSP45102 can be used to generate various

modulation schemes for Direct Digital Synthesis (DDS)

applications. Figure 29 shows how to interface an HI5731 to

the HSP45102.

LOW PASS

FILTER

(21) I

OUT

64Ω

50Ω

FIGURE 25. GLITCH TEST CIRCUIT

This high level block diagram is that of a basic PSK

modulator. In this example the encoder generates the PSK

waveform by driving the Phase Modulation Inputs (P1, P0) of

the HSP45102. The P1-0 inputs impart a phase shift to the

carrier wave as deﬁned in Table 2.

TABLE 3. PHASE MODULATION INPUT CODING

PHASE SHIFT (DEGREES)

a (mV)

GLITCH ENERGY = (a x t)/2

270

180

t (ns)

The data port of the HSP45102 drives the 12-bit HI5731

DAC which converts the NCO output into an analog

waveform. The output ﬁlter connected to the DAC can be

tailored to remove unwanted spurs for the desired carrier

frequency. The controller is used to load the desired center

frequency and control the HSP45102. The HI5731 coupled

with the HSP45102 make an inexpensive PSK modulator

with Spurious Free performance down to -76dBc.

FIGURE 26. MEASURING GLITCH ENERGY

Applications

Bipolar Applications

To convert the output of the HI5731 to a bipolar 4V swing,

the following applications circuit is recommended. The

reference can only provide 125µA of drive, so it must be

3-11

HI5731

Deﬁnition of Speciﬁcations

Integral Linearity Error, INL, is the measure of the worst

case point that deviates from a best ﬁt straight line of data

values along the transfer curve.

Differential Linearity Error, DNL, is the measure of the

error in step size between adjacent codes along the

converter’s transfer curve. Ideally, the step size is 1 LSB

from one code to the next, and the deviation from 1 LSB is

known as DNL. A DNL speciﬁcation of greater than -1 LSB

guarantees monotonicity.

Feedthru, is the measure of the undesirable switching noise

coupled to the output.

Output Voltage Full Scale Settling Time, is the time

required from the 50% point on the clock input for a full scale

step to settle within an ± / LSB error band.

Output Voltage Small Scale Settling Time, is the time

required from the 50% point on the clock input for a 100mV

step to settle within an / LSB error band. This is used by

applications reconstructing highly correlated signals such as

sine waves with more than 5 points per cycle.

Glitch Area, GE, is the switching transient appearing on the

output during a code transition. It is measured as the area

under the curve and expressed as a picoVolt-time

speciﬁcation (typically pV-s).

Differential Gain, ∆A , is the gain error from an ideal sine

wave with a normalized amplitude.

Differential Phase, ∆Φ, is the phase error from an ideal

sine wave.

Signal to Noise Ratio, SNR, is the ratio of a fundamental to

the noise ﬂoor of the analog output. The ﬁrst 5 harmonics

are ignored, and an output ﬁlter of / the clock frequency is

used to eliminate alias products.

Total Harmonic Distortion, THD, is the ratio of the DAC

output fundamental to the RMS sum of the harmonics. The

ﬁrst 5 harmonics are included, and an output ﬁlter of / the

clock frequency is used to eliminate alias products.

Spurious Free Dynamic Range, SFDR, is the amplitude

difference from a fundamental to the largest harmonically or

non-harmonically related spur. A sine wave is loaded into the

D/A and the output ﬁltered at / the clock frequency to

eliminate noise from clocking alias terms.

Intermodulation Distortion, IMD, is the measure of the

sum and difference products produced when a two tone

input is driven into the D/A. The distortion products created

will arise at sum and difference frequencies of the two tones.

IMD can be calculated using the following equation:

20Log (RMS of Sum and Difference Distortion Products)

IMD =

------------------------------------------------------------------------------------------------------------------------------------------------------

(RMS Amplitude of the Fundamental)

3-12

HI5731

33 MSPS

CLK

C11

B11

C10

MOD2

MOD1

BASEBAND

BIT

STREAM

TO RF

UP-CONVERT

STAGE

FILTER

ENCODER

MOD0

A11

OUT

PMSEL

DACSTRB

F10

F11

H11

G11

L10

SIN15

SIN14

SIN13

SIN12

SIN11

SIN10

SIN9

SIN8

SIN7

SIN6

SIN5

SIN4

SIN3

SIN2

SIN1

SIN0

D11 (MSB)

D10

ENPOREG

ENOFREG

ENCFREG

ENPHAC

ENTIREG

INHOFR

CNTRL IN

-5.2V_A

C2 0.1µF

J11

G10

INITPAC

INITTAC

CNTRL OUT

C1 0.01µF

D10

J10

TEST

PARSER

BINFMT

D0 (LSB)

REF OUT

CONTROLLER

K11

CLK

SET

C15_MSB

DGND

976

C13

C12

C11

C10

ARET

COS15

COS14

COS13

COS12

COS11

COS10

COS9

COS8

COS7

COS6

COS5

COS4

COS3

COS2

COS1

COS0

-5.2V_A

-5.2V_D

HI5731

-5.2V_D

-5.2V_A

10µH

B10

A10

E11

10µH

H10

PACI

TICO

OES

OEC

HSP45106

FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO

3-13

HI5731

TO RF

UP-CONVERT

STAGE

FILTER

OUT

40 MSPS

CLK

OUT11

D11 (MSB)

D10

BASEBAND

BIT

STREAM

OUT10

OUT9

OUT8

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

ENCODER

LOAD#

CNTRL IN

-5.2V_A

C2 0.1µF

TXFR#

CNTRL OUT

C1 0.01µF

ENPHAC#

SEL_L/M#

CONTROL

BUS

D0 (LSB)

CONTROLLER

REF OUT

CLK

SCLK

RSET

DGND

976

SFTEN#

MSB/LSB#

ARET

HSP45102

-5.2V_A

-5.2V_D

HI5731

10µH

-5.2V_D

-5.2V_A

10µH

FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO

3-14

HI5731

Die Characteristics

DIE DIMENSIONS:

PASSIVATION:

161.5 mils x 160.7 mils x 19 mils

Type: Sandwich Passivation

Undoped Silicon Glass (USG) + Nitride

Thickness: USG - 8kÅ, Nitride - 4.2kÅ

Total 12.2kÅ + 2kÅ

METALLIZATION:

Type: AlSiCu

Thickness: M1 - 8kÅ, M2 - 17kÅ

SUBSTRATE POTENTIAL (POWERED UP):

EED

Metallization Mask Layout

HI5731

D10

D11

DGND

CTRL OUT

CTRL IN

SET

OUT

ARTN

CLK

DGND

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

3-15

HI5731BIB相关文章

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HI5731BIB产品参数

型号:	HI5731BIB
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTERSIL CORP
零件包装代码：	SOIC
包装说明：	PLASTIC, MS-013-AE, SOIC-28
针数：	28
Reach Compliance Code：	not_compliant
Factory Lead Time：	1 week
风险等级：	5.58
Is Samacsys：	N
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	PARALLEL, WORD
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0
最大线性误差 (EL)：	0.0366%
标称负供电电压：	-5.2 V
位数：	12
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP28,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-5.2 V
认证状态：	Not Qualified
标称安定时间 (tstl)：	0.02 µs
子类别：	Other Converters
标称供电电压：	5 V
表面贴装：	YES
技术：	BICMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

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