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    产品型号HM62W4100H的Datasheet PDF文件预览

    HM62W4100H Series  
    4M High Speed SRAM (1-Mword × 4-bit)  
    ADE-203-774D (Z)  
    Rev. 1.0  
    Sep. 15, 1998  
    Description  
    The HM62W4100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high  
    speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed  
    circuit designing technology. It is most appropriate for the application which requires high speed and high  
    density memory, such as cache and buffer memory in system. The HM62W4100H is packaged in 400-mil  
    32-pin SOJ for high density surface mounting.  
    Features  
    •
    •
    •
    Single supply : 3.3 V ± 0.3 V  
    Access time 12/15 ns (max)  
    Completely static memory  
    No clock or timing strobe required  
    Equal access and cycle times  
    Directly TTL compatible  
    •
    •
    All inputs and outputs  
    •
    •
    •
    Operating current : 180/160 mA (max)  
    TTL standby current : 60/50 mA (max)  
    CMOS standby current : 5 mA (max)  
    : 1 mA (max) (L-version)  
    •
    •
    •
    Data retension current : 0.6 mA (max) (L-version)  
    Data retension voltage: 2 V (min) (L-version)  
    Center VCC and VSS type pinout  
    HM62W4100H Series  
    Ordering Information  
    Type No.  
    Access time  
    Package  
    HM62W4100HJP-12  
    HM62W4100HJP-15  
    12 ns  
    15 ns  
    400-mil 32-pin plastic SOJ (CP-32DB)  
    HM62W4100HLJP-12  
    HM62W4100HLJP-15  
    12 ns  
    15 ns  
    Pin Arrangement  
    HM62W4100HJP/HLJP Series  
    1
    A0  
    A1  
    32  
    31  
    30  
    29  
    28  
    27  
    26  
    25  
    24  
    23  
    22  
    21  
    20  
    19  
    18  
    17  
    A19  
    A18  
    A17  
    A16  
    A15  
    OE  
    I/O4  
    VSS  
    VCC  
    I/O3  
    A14  
    A13  
    A12  
    A11  
    A10  
    NC  
    2
    3
    A2  
    4
    A3  
    5
    A4  
    6
    CS  
    I/O1  
    VCC  
    VSS  
    I/O2  
    WE  
    A5  
    7
    8
    9
    10  
    11  
    12  
    13  
    14  
    15  
    16  
    A6  
    A7  
    A8  
    A9  
    (Top view)  
    2
    HM62W4100H Series  
    Pin Description  
    Pin name  
    A0 to A19  
    I/O1 to I/O4  
    CS  
    Function  
    Address input  
    Data input/output  
    Chip select  
    OE  
    Output enable  
    Write enable  
    Power supply  
    Ground  
    WE  
    VCC  
    VSS  
    NC  
    No connection  
    Block Diagram  
    (LSB)  
    A1  
    VCC  
    VSS  
    A17  
    A7  
    A11  
    A16  
    A2  
    Memory matrix  
    256 rows × 16 columns ×  
    256 blocks × 4 bit  
    Row  
    decoder  
    (4,194,304 bits)  
    A6  
    A5  
    (MSB)  
    CS  
    Column I/O  
    I/O1  
    .
    Input  
    data  
    control  
    Column decoder  
    CS  
    .
    .
    I/O4  
    A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4  
    (LSB)  
    (MSB)  
    WE  
    CS  
    OE  
    CS  
    3
    HM62W4100H Series  
    Operation Table  
    CS  
    H
    L
    OE  
    ×
    WE  
    ×
    Mode  
    VCC current  
    I/O  
    Ref. cycle  
    —
    Standby  
    Output disable  
    Read  
    ISB, ISB1  
    ICC  
    High-Z  
    High-Z  
    Dout  
    Din  
    H
    L
    H
    H
    L
    —
    L
    ICC  
    Read cycle (1) to (3)  
    Write cycle (1)  
    Write cycle (2)  
    L
    H
    L
    Write  
    ICC  
    L
    L
    Write  
    ICC  
    Din  
    Note: ×: H or L  
    Absolute Maximum Ratings  
    Parameter  
    Symbol  
    Value  
    Unit  
    Supply voltage relative to VSS  
    Voltage on any pin relative to VSS  
    Power dissipation  
    VCC  
    –0.5 to +4.6  
    –0.5*1 to VCC+0.5*2  
    V
    VT  
    V
    PT  
    1.0  
    W
    °C  
    °C  
    °C  
    Operating temperature  
    Storage temperature  
    Topr  
    Tstg  
    Tbias  
    0 to +70  
    –55 to +125  
    –10 to +85  
    Storage temperature under bias  
    Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns  
    2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns  
    Recommended DC Operating Conditions (Ta = 0 to +70°C)  
    Parameter  
    Symbol  
    VCC*3  
    VSS*4  
    VIH  
    Min  
    3.0  
    Typ  
    3.3  
    0
    Max  
    Unit  
    V
    Supply voltage  
    3.6  
    0
    0
    V
    Input voltage  
    2.2  
    —
    VCC + 0.5*2  
    V
    VIL  
    –0.5*1  
    —
    0.8  
    V
    Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns  
    2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns  
    3. The supply voltage with all VCC pins must be on the same level.  
    4. The supply voltage with all VSS pins must be on the same level.  
    4
    HM62W4100H Series  
    DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)  
    Parameter  
    Symbol Min  
    Typ*1  
    —
    Max  
    2
    Unit  
    µA  
    Test conditions  
    Vin = VSS to VCC  
    Vin = VSS to VCC  
    Input leakage current  
    Output leakage current  
    IILII  
    —
    —
    —
    IILOI  
    —
    2
    µA  
    Operation power  
    supply current  
    12 ns cycle ICC  
    —
    180  
    mA  
    Min cycle  
    CS = VIL, lout = 0 mA  
    Other inputs = VIH/VIL  
    15 ns cycle ICC  
    —
    —
    —
    —
    160  
    60  
    Standby power supply 12 ns cycle ISB  
    current  
    mA  
    mA  
    Min cycle, CS = VIH,  
    Other inputs = VIH/VIL  
    15 ns cycle ISB  
    ISB1  
    —
    —
    —
    50  
    5
    0.05  
    f = 0 MHz  
    V
    CC ≥ CS ≥ VCC - 0.2 V,  
    (1) 0 V ≤ Vin ≤ 0.2 V or  
    (2) VCC ≥ Vin ≥ VCC - 0.2 V  
    —*2  
    —
    0.05*2  
    —
    1*2  
    0.4  
    —
    Output voltage  
    VOL  
    VOH  
    V
    V
    IOL = 8 mA  
    2.4  
    —
    IOH = –4 mA  
    Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.  
    2. This characteristics is guaranteed only for L-version.  
    Capacitance (Ta = +25°C, f = 1.0 MHz)  
    Parameter  
    Symbol Min  
    Typ  
    —
    Max  
    6
    Unit  
    pF  
    Test conditions  
    Vin = 0 V  
    Input capacitance*1  
    Input/output capacitance*1  
    Cin  
    CI/O  
    —
    —
    —
    8
    pF  
    VI/O = 0 V  
    Note: 1. This parameter is sampled and not 100% tested.  
    5
    HM62W4100H Series  
    AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)  
    Test Conditions  
    •
    •
    •
    •
    Input pulse levels: 3.0 V/0.0 V  
    Input rise and fall time: 3 ns  
    Input and output timing reference levels: 1.5 V  
    Output load: See figures (Including scope and jig)  
    3.3 V  
    319Ω  
    Dout  
    Zo=50 Ω  
    Dout  
    353Ω  
    RL=50 Ω  
    5 pF  
    1.5 V  
    Output load (A)  
    Output load (B)  
    (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW  
    )
    Read Cycle  
    HM62W4100H  
    -12  
    Min  
    12  
    —
    —
    —
    3
    -15  
    Min  
    15  
    —
    —
    —
    3
    Parameter  
    Symbol  
    tRC  
    Max  
    —
    12  
    12  
    6
    Max  
    —
    15  
    15  
    7
    Unit  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    Notes  
    Read cycle time  
    Address access time  
    tAA  
    Chip select access time  
    tACS  
    tOE  
    Output enable to outpput valid  
    Output hold from address change  
    Chip select to output in low-Z  
    Output enable to output in low-Z  
    Chip deselect to output in high-Z  
    Output disable to output in high-Z  
    tOH  
    —
    —
    —
    6
    —
    —
    —
    7
    tCLZ  
    3
    3
    1
    1
    1
    1
    tOLZ  
    tCHZ  
    tOHZ  
    0
    0
    —
    —
    —
    —
    6
    7
    6
    HM62W4100H Series  
    Write Cycle  
    HM62W4100H  
    -12  
    -15  
    Parameter  
    Symbol  
    tWC  
    Min  
    12  
    8
    Max  
    —
    —
    —
    —
    —
    —
    —
    —
    —
    6
    Min  
    15  
    10  
    10  
    10  
    0
    Max  
    —
    —
    —
    —
    —
    —
    —
    —
    —
    7
    Unit  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    Notes  
    Write cycle time  
    Address valid to end of write  
    Chip select to end of write  
    Write pulse width  
    tAW  
    tCW  
    8
    9
    8
    6
    7
    tWP  
    8
    Address setup time  
    tAS  
    0
    Write recovery time  
    tWR  
    0
    0
    Data to write time overlap  
    Data hold from write time  
    Write disable to output in low-Z  
    Output disable to output in high-Z  
    Write enable to output in high-Z  
    tDW  
    6
    7
    tDH  
    0
    0
    tOW  
    3
    3
    1
    1
    1
    tOHZ  
    tWHZ  
    —
    —
    —
    —
    6
    7
    Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled  
    and not 100% tested.  
    2. Address should be valid prior to or coincident with CS transition low.  
    3. WE and/or CS must be high during address transition time.  
    4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input  
    signals of opposite phase to the outputs must not be applied to them.  
    5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,  
    output remains a high impedance state.  
    6. tAS is measured from the latest address transition to the later of CS or WE going low.  
    7. tWR is measured from the earlier of CS or WE going high to the first address transition.  
    8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition  
    among CS going low and WE going low. A write ends at the earliest transition among CS going  
    high and WE going high. tWP is measured from the beginnig of write to the end of write.  
    9. tCW is measured from the later of CS going low to the the end of write.  
    7
    HM62W4100H Series  
    Timing Waveforms  
    Read Timing Waveform (1) (WE = VIH)  
    tRC  
    Address  
    Valid address  
    tAA  
    tOH  
    tCHZ  
    tACS  
    CS  
    OE  
    tOE  
    tOHZ  
    tOLZ  
    tCLZ  
    High Impedance  
    Dout  
    Valid data  
    Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)  
    tRC  
    Address  
    Dout  
    Valid address  
    tAA  
    tOH  
    tOH  
    Valid data  
    8
    HM62W4100H Series  
    Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*2  
    tRC  
    CS  
    tACS  
    tCHZ  
    tCLZ  
    High  
    Dout  
    High  
    Impedance  
    Valid data  
    Impedance  
    Write Timing Waveform (1) (WE Controlled)  
    tWC  
    Valid address  
    tAW  
    Address  
    tWR  
    OE  
    tCW  
    CS*3  
    tAS  
    tWP  
    WE*3  
    Dout  
    Din  
    tOHZ  
    High impedance*5  
    tDW  
    tDH  
    4
    4
    *
    *
    Valid data  
    9
    HM62W4100H Series  
    Write Timing Waveform (2) (CS Controlled)  
    tWC  
    Valid address  
    tCW  
    Address  
    tWR  
    CS *3  
    tAW  
    tWP  
    WE *3  
    tAS  
    tWHZ  
    tOW  
    High impedance*5  
    Dout  
    Din  
    tDW  
    tDH  
    4
    4
    *
    *
    Valid data  
    10  
    HM62W4100H Series  
    Low VCC Data Retention Characteristics (Ta = 0 to +70°C)  
    This characteristics is guaranteed only for L-version.  
    Parameter  
    Symbol  
    Min  
    Typ*1  
    Max  
    Unit Test conditions  
    VCC for data retention  
    VDR  
    2.0  
    —
    —
    V
    VCC ≥ CS ≥ VCC – 0.2 V  
    (1) 0 V ≤ Vin ≤ 0.2 V or  
    (2) VCC ≥ Vin ≥ VCC – 0.2 V  
    Data retention current  
    ICCDR  
    —
    40  
    600  
    µA  
    VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V  
    (1) 0 V ≤ Vin ≤ 0.2 V or  
    (2) VCC ≥ Vin ≥ VCC – 0.2 V  
    Chip deselect to data  
    retention time  
    tCDR  
    tR  
    0
    5
    —
    —
    —
    —
    ns  
    See retention waveform  
    Operation recovery time  
    ms  
    Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.  
    Low VCC Data Retention Timing Waveform  
    Data retention mode  
    tCDR  
    tR  
    VCC  
    3.0 V  
    VDR  
    2.2 V  
    CS  
    0 V  
    V
    CC ≥ CS ≥ VCC – 0.2 V  
    11  
    HM62W4100H Series  
    Package Dimensions  
    HM62W4100HJP/HLJP Series (CP-32DB)  
    Unit: mm  
    20.71  
    21.08 Max  
    32  
    17  
    16  
    1
    0.74  
    1.30 Max  
    9.40 ± 0.25  
    1.27  
    0.43 ± 0.10  
    0.41 ± 0.08  
    0.10  
    Hitachi Code  
    JEDEC  
    EIAJ  
    CP-32DB  
    Conforms  
    Conforms  
    Dimension including the plating thickness  
    Base material dimension  
    Weight (reference value) 1.2 g  
    12  
    HM62W4100H Series  
    Cautions  
    1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,  
    copyright, trademark, or other intellectual property rights for information contained in this document.  
    Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual  
    property rights, in connection with use of the information contained in this document.  
    2. Products and product specifications may be subject to change without notice. Confirm that you have  
    received the latest product standards or specifications before final design, purchase or use.  
    3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,  
    contact Hitachi’s sales office before using the product in an application that demands especially high  
    quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of  
    bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,  
    safety equipment or medical equipment for life support.  
    4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for  
    maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and  
    other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the  
    guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or  
    failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the  
    equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage  
    due to operation of the Hitachi product.  
    5. This product is not designed to be radiation resistant.  
    6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without  
    written approval from Hitachi.  
    7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor  
    products.  
    Hitachi, Ltd.  
    Semiconductor & IC Div.  
    Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
    Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109  
    URL  
    NorthAmerica  
    Europe  
    : http:semiconductor.hitachi.com/  
    : http://www.hitachi-eu.com/hel/ecg  
    Asia (Singapore)  
    Asia (Taiwan)  
    : http://www.has.hitachi.com.sg/grp3/sicd/index.htm  
    : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm  
    Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm  
    Japan  
    : http://www.hitachi.co.jp/Sicd/indx.htm  
    For further information write to:  
    Hitachi Semiconductor  
    (America) Inc.  
    Hitachi Europe GmbH  
    Electronic components Group  
    Hitachi Asia (Hong Kong) Ltd.  
    Group III (Electronic Components)  
    7/F., North Tower, World Finance Centre,  
    Harbour City, Canton Road, Tsim Sha Tsui,  
    Kowloon, Hong Kong  
    Tel: <852> (2) 735 9218  
    Fax: <852> (2) 730 0281  
    Hitachi Asia Pte. Ltd.  
    16 Collyer Quay #20-00  
    Hitachi Tower  
    Singapore 049318  
    Tel: 535-2100  
    2000 Sierra Point Parkway Dornacher Straße 3  
    Brisbane, CA 94005-1897 D-85622 Feldkirchen, Munich  
    Tel: <1> (800) 285-1601  
    Fax: <1> (303) 297-0447  
    Germany  
    Tel: <49> (89) 9 9180-0  
    Fax: <49> (89) 9 29 30 00  
    Fax: 535-1533  
    Hitachi Asia Ltd.  
    Taipei Branch Office  
    3F, Hung Kuo Building. No.167,  
    Tun-Hwa North Road, Taipei (105)  
    Tel: <886> (2) 2718-3666  
    Fax: <886> (2) 2718-8180  
    Telex: 40815 HITEC HX  
    Hitachi Europe Ltd.  
    Electronic Components Group.  
    Whitebrook Park  
    Lower Cookham Road  
    Maidenhead  
    Berkshire SL6 8YA, United Kingdom  
    Tel: <44> (1628) 585000  
    Fax: <44> (1628) 778322  
    Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.  
    13  
    配单直通车
    HM62W4100HCJP-10产品参数
    型号:HM62W4100HCJP-10
    生命周期：Obsolete
    IHS 制造商：RENESAS TECHNOLOGY CORP
    零件包装代码：SOJ
    包装说明：SOJ, SOJ32,.44
    针数：32
    Reach Compliance Code：unknown
    ECCN代码：3A991.B.2.A
    HTS代码：8542.32.00.41
    风险等级：5.64
    最长访问时间：10 ns
    I/O 类型：COMMON
    JESD-30 代码：R-PDSO-J32
    长度：20.71 mm
    内存密度：4194304 bit
    内存集成电路类型：CACHE SRAM
    内存宽度：4
    功能数量：1
    端子数量：32
    字数：1048576 words
    字数代码：1000000
    工作模式：ASYNCHRONOUS
    最高工作温度：70 °C
    最低工作温度：
    组织：1MX4
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：SOJ
    封装等效代码：SOJ32,.44
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE
    并行/串行：PARALLEL
    电源：3.3 V
    认证状态：Not Qualified
    座面最大高度：3.76 mm
    最小待机电流：3 V
    子类别：SRAMs
    最大压摆率：0.115 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子形式：J BEND
    端子节距：1.27 mm
    端子位置：DUAL
    宽度：10.16 mm
    Base Number Matches：1
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