HSP3824EVAL应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

S E M I C O N D U C T O R

HSP3824

Direct Sequence Spread Spectrum

Baseband Processor

PRELIMINARY

March 1996

TM

Features

Description

The Harris HSP3824 Direct

Sequence (DSSS) baseband pro-

cessor is part of the PRISM™

• Complete DSSS Baseband Processor

• High Data Rate. . . . . . . . . . . . . . . . . . . . .up to 4 MBPS

• Processing Gain . . . . . . . . . . . . . . . . . . . . . up to 12dB

• Programmable PN Code . . . . . . . . . . . . up to 16 Bits

• Ultra Small Package . . . . . . . . . . . . . . . . . 7 x 7 x 1mm

• Single Supply Operation (33MHz Max) . . 2.7V to 5.5V

• Single Supply Operation (44MHz Max) . . 3.3V to 5.0V

• Modulation Method . . . . . . . . . . . . .DBPSK or DQPSK

• Supports Full or Half Duplex Operations

2.4GHz radio chipset, and contains

all the functions necessary for a full or half duplex packet base-

band transceiver.

The HSP3824 has on-board ADC’s for analog I and Q inputs, for

which the HFA3724 IF QMODEM is recommended. Differential

phase shift keying modulation schemes DBPSK and DQPSK,

with optional data scrambling capability, are combined with a pro-

grammable PN sequence of up to 16 bits. Built-in ﬂexibility allows

the HSP3824 to be conﬁgured through a general purpose control

bus, for a wide range of applications. A Receive Signal Strength

Indicator (RSSI) monitoring function with on-board 6-bit 2 MSPS

ADC provides Clear Channel Assessment (CCA) to avoid data

collisions and optimize network throughput. The HSP3824 is

housed in a thin plastic quad ﬂat package (TQFP) suitable for

PCMCIA board applications.

• On-Chip A/D Converters for I/Q Data (3-Bit, 44 MSPS)

and RSSI (6-Bit, 2 MSPS)

Applications

• Systems Targeting IEEE802.11 Standard

• DSSS PCMCIA Wireless Transceiver

• Spread Spectrum WLAN RF Modems

• TDMA Packet Protocol Radios

• Part 15 Compliant Radio Links

• Portable Bar Code Scanners/POS Terminal

• Portable PDA/Notebook Computer

• Wireless Digital Audio

Ordering Information

PART NO.

TEMP. RANGE

PKG. TYPE

PKG. NO.

o

HSP3824VI

-40 C to +85 C

48 Lead TQFP

Q48.7x7

• Wireless Digital Video

• PCN/Wireless PBX

Simpliﬁed Block Diagram

Pinout

HSP3824 (TQFP)

3-BIT

I_IN

DPSK

DEMOD.

A/D

48 47 46 45 44 43 42 41 40 39 38 37

36

3-BIT

A/D

RXCLK

RXD

Q_IN

1

TEST_CK

35

34

33

32

31

30

29

28

27

26

25

TX_PE

TXD

2

3

MD_RDY

RX_PE

PRO-

CESSOR

INTER-

FACE

TXCLK

TX_RDY

GND

V_DD

4

5

6-BIT

A/D

RSSI

CCA

GND

CCA

CTRL

6

7

MCLK

V_DD

R/W

8

I_OUT

RESET

ANTSEL

A/D_CAL

SD

9

CS

10

V_DD

GND

I_IN

11

12

DPSK

MOD.

Q_OUT

13 14 15 16 17 18 19 20 21 22 23 24

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 4064.2

1

PRISM™ and the PRISM™ logo are Trademarks of Harris Corporation

HSP3824

List of Contents

Typical Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

External Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

TX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

RX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

I/Q ADC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

ADC Calibration Circuit and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

RSSI ADC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Test Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

External AGC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Power Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Header/Packet Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PN Generator Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Clear Channel Assessment (CCA) and Energy Detect (ED) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Two Antenna Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

One Antenna Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Acquisition Signal Quality Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Procedure to Set Acq. Signal Quality Parameters (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

PN Correlator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Data Demodulation and Tracking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Procedure to Set Signal Quality Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Demodulator Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Overall Eb/N0 Versus BER Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

I/Q Amplitude Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

A Default Register Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

HSP3824 33MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

HSP3824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

HSP3824 44MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Thin Plastic Quad Flatpack Packages (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2

HSP3824

Typical Application Diagram

HFA3724

(FILE# 4067)

HSP3824

(FILE# 4064)

TUNE/SELECT

RXI

HFA3424 (NOTE)

(FILE# 4131)

DPSK

DEMOD

A/D

DE-

SPREAD

RXQ

RSSI

I

HFA3624

RF/IF

A/D

802.11

MAC-PHY

INTERFACE

CONVERTER

(FILE# 4066)

÷ 2

M

U

X

M

U

X

0^o/90^o

CCA

TXI

SPREAD

DPSK

MOD.

RFPA

TXQ

VCO

Q

HFA3925

(FILE# 4132)

QUAD IF MODULATOR

DSSS BASEBAND PROCESSOR

PRISM™ CHIP SET FILE #4063

DUAL SYNTHESIZER

(FILE# 4062)

HFA3524

TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HSP3824

NOTE: Required for systems targeting 802.11 speciﬁcations.

For additional information on the PRISM™ chip set, call The four-digit ﬁle numbers are shown in Typical Application

(407) 724-7800 to access Harris’ AnswerFAX system. When Diagram, and correspond to the appropriate circuit.

prompted, key in the four-digit document number (File #) of

the datasheets you wish to receive.

3

HSP3824

Pin Description

NAME

TYPE I/O

DESCRIPTION

V

(Analog)

(Digital)

10, 18, 20

Power

DC power supply 2.7V - 5.5V

DD

V

7, 21, 29, 42

Power

DD

GND (Analog)

GND (Digital)

11, 15, 19

Ground

DC power supply 2.7V - 5.5V, ground.

6, 22, 31, 41

Ground

DC power supply 2.7V - 5.5V, ground.

V

17

16

12

13

14

26

I

“Negative” voltage reference for ADC’s (I and Q) [Relative to V

]

REFP

REFN

REFP

“Positive” voltage reference for ADC’s (I, Q and RSSI)

I

Analog input to the internal 3-bit A/D of the In-phase received data.

IN

Q

I

Analog input to the internal 3-bit A/D of the Quadrature received data.

Receive Signal Strength Indicator Analog input.

IN

RSSI

I

A/D_CAL

O

This signal is used internally as part of the I and Q ADC calibration circuit. When the

ADC calibration circuit is active, the voltage references of the ADCs are adjusted to

maintain the outputs of the ADCs in their optimum range. A logic 1 on this pin indicates

that one or both of the ADC outputs are at their full scale value. This signal can be

integrated externally as a control voltage for an external AGC.

TX_PE

2

I

When active, the transmitter is conﬁgured to be operational, otherwise the transmitter

is in standby mode. TX_PE is an input from the external Media Access Controller

(MAC) or network processor to the HSP3824. The rising edge of TX_PE will start the

internal transmit state machine and the falling edge will inhibit the state machine.

TX_PE envelopes the transmit data.

TXD

3

4

I

TXD is an input, used to transfer serial Data or Preamble/Header information bits from

the MAC or network processor to the HSP3824. The data is received serially with the

LSB ﬁrst. The data is clocked in the HSP3824 at the falling edge of TXCLK.

TXCLK

O

TXCLK is a clock output used to receive the data on the TXD from the MAC or network

processor to the HSP3824, synchronously. Transmit data on the TXD bus is clocked

into the HSP3824 on the falling edge. The clocking edge is also programmable to be

on either phase of the clock. The rate of the clock will be depending upon the

modulation type and data rate that is programmed in the signalling ﬁeld of the header.

TX_RDY

5

O

When the HSP3824 is conﬁgured to generate the preamble and Header information

internally, TX_RDY is an output to the external network processor indicating that

Preamble and Header information has been generated and that the HSP3824 is ready

to receive the data packet from the network processor over the TXD serial bus. The

TX_RDY returns to the inactive state when the TX_PE goes inactive indicating the end

of the data transmission. TX_RDY is an active high signal. This signal is meaningful

only when the HSP3824 generates its own preamble.

CCA

32

Clear Channel Assessment (CCA) is an output used to signal that the channel is clear

to transmit. The CCA algorithm is user programmable and makes its decision as a

function of RSSI, Energy detect (ED), Carrier Sense (CRS) and the CCA watch dog

timer. The CCA algorithm and its programmable features are described in the data

sheet.

Logic 0 = Channel is clear to transmit.

Logic 1 = Channel is NOT clear to transmit (busy).

NOTE: This polarity is programmable and can be inverted.

RXD

35

36

O

RXD is an output to the external network processor transferring demodulated Header

information and data in a serial format. The data is sent serially with the LSB ﬁrst. The

data is frame aligned with MD_RDY.

RXCLK

RXCLK is the clock output bit clock. This clock is used to transfer Header information

and data through the RXD serial bus to the network processor. This clock reﬂects the

bit rate in use.RXCLK will be held to a logic “0” state during the acquisition process.

RXCLK becomes active when the HSP3824 enters in the data mode. This occurs once

bit sync is declared and a valid signal quality estimate is made, when comparing the

programmed signal quality thresholds.

4

HSP3824

Pin Description (Continued)

NAME

TYPE I/O

DESCRIPTION

MD_RDY

34

O

MD_RDY is an output signal to the network processor, indicating a data packet is

ready to be transferred to the processor. MD_RDY is an active high signal and it

envelopes the data transfer over the RXD serial bus. MD_RDY returns to its inactive

state when there is no more receiver data, when the programmable data length

counter reaches its value or when the link has been interrupted. MD_RDY remains

inactive during preamble synchronization.

RX_PE

ANTSEL

SD

33

27

25

I

When active, receiver is conﬁgured to be operational, otherwise receiver is in standby

mode. This is an active high input signal.

O

The antenna select signal changes state as the receiver switches from antenna to

antenna during the acquisition process in the antenna diversity mode.

I/O

SD is a serial bi-directional data bus which is used to transfer address and data to/from

the internal registers. The bit ordering of an 8-bit word is MSB ﬁrst. The ﬁrst 8 bits

during transfers indicate the register address immediately followed by 8 more bits

representing the data that needs to be written or read at that register.

SCLK

24

I

SCLK is the clock for the SD serial bus.The data on SD is clocked at the rising edge.

SCLK is an input clock and it is asynchronous to the internal master clock (MCLK)The

maximum rate of this clock is 10MHz or the master clock frequency, whichever is

lower.

AS

R/W

CS

23

8

I

AS is an address strobe used to envelope the Address or the data on SD.

Logic 1 = envelopes the address bits.

Logic 0 = envelopes the data bits.

R/W is an input to the HSP3824 used to change the direction of the SD bus when

reading or writing data on the SD bus. R/W must be set up prior to the rising edge of

SCLK. A high level indicates read while a low level is a write.

9

CS is a Chip select for the device to activate the serial control port.The CS doesn’t

impact any of the other interface ports and signals, i.e. the TX or RX ports and

interface signals. This is an active low signal. When inactive SD, SCLK, AS and R/W

become “don’t care” signals.

TEST 0-7

37, 38, 39,

40, 43, 44,

45, 46

O

This is a data port that can be programmed to bring out internal signals or data for

monitoring. This data includes: Correlator phase and magnitude, NCO frequency

offset estimate, and signal quality estimates. Some of the discrete signals available

include: Carrier Sense (CRS), which becomes active when initial PN acquisition has

been declared. Energy Detect (ED) which becomes active when the integrated RSSI

value exceeds the programmable threshold. Both ED and CRS are active high

signals.These bits are primarily reserved by the manufacturer for testing. A further

description of the test port is given at the appropriate section of this data sheet.

TEST_CK

RESET

1

O

I

This is the clock that is used in conjunction with the data that is being output from the

test bus (TEST 0-7).

28

Master reset for device. When active TX and RX functions are disabled. If RESET is

kept low the HSP3824 goes into the power standby mode. RESET does not alter any

of the conﬁguration register values nor it presets any of the registers into default

values. Device requires programming upon power-up. RESET must be inactive during

programming of the device.

MCLK

30

I

Master Clock for device. The maximum frequency of this clock is 44MHz. This is used

internally to generate all other internal necessary clocks and is divided by 1, 2, 4, or 8

for the transceiver clocks.

I

48

47

O

TX Spread baseband I digital output data. Data is output at the programmed chip rate.

OUT

Q

TX Spread baseband Q digital output data. Data is output at the programmed chip

rate.

OUT

NOTE: Total of 48 pins; ALL pins are used.

5

HSP3824

V_DD(ANALOG)

(10, 18, 20)

GND (ANALOG)

(11, 15, 19)

V_DD(DIGITAL)

(7, 21, 29, 42)

GND (DIGITAL)

(6, 22, 31, 41)

PN CODE

11 TO 16-BIT

VR3+

DE-SPREADER/ACQUISITION

MF CORRELATOR

11 TO 16-BIT

BIT

SYNC

3-BIT

A/D

(36) RXCLK

8

I

_IN(12)

3

MAG. /

PHASE

AND

TIMING

DISTRIB.

MF CORRELATOR

11 TO 16-BIT

3-BIT

A/D

Q

_IN(13)

8

REF

2V

VR3-

V_REFP(16)

1.75V

A/D REFERENCE

(MAX)

AND

LEVEL ADJUST.

V_REFN(17)

0.25V

(MIN)

DIFF

DECODER

RSSI

REF

CLEAR CHANNEL

ASSESSMENT/

SIGNAL QUALITY

PHASE

ROTATE

PSK

DEMOD

(32) CCA

AGC (26)

PHASE

ERROR

d(t)

Z ^-1

SIGNAL

QUALITY

AND

6-BIT

A/D

RSSI (14)

RSSI

LEAD

d(t-1)

/LAG

NCO

FILTER

ANALOG

XOR

(33) RX_PE

(35) RXD

ANTSEL (27)

DPSK DEMOD

AND AFC

(34) MD_RDY

DPSK MODULATOR

RX_DATA

DESCRAMBLER

DIFFERENTIAL

ENCODER

CLK

I

CODE

b(t)

b(t-1)

Z ^-1

(5) TX_RDY

(4) TXCLK

(3) TXD

I_OUT(48)

XOR

TX_DATA

SCRAMBLER

XOR

(2) TX_PE

Q_OUT(47)

Q

MUX CLK

FOR DQPSK

I CH ONLY FOR DBPSK

PN CODE

11 TO 16-BIT

PN GENERATOR

CHIP RATE

(25) SD

(24) SCLK

(23) AS

(8) R/W

(9) CS

SPREADER

TIMING

GENERATOR

MCLK

TEST PORT

(28)

(30)

(1)

(37) (38) (39) (40) (43) (44) (45) (46)

RESET

MCLK

TEST_CK

FIGURE 1. DSSS BASEBAND PROCESSOR

6

HSP3824

Control Port

External Interfaces

There are three primary digital interface ports for the The serial control port is used to serially write and read data to/

HSP3824 that are used for conﬁguration and during normal from the device. This serial port can operate up to a 10MHz

operation of the device. These ports are:

rate or the maximum master clock rate of the device, MCLK

(whichever is lower). MCLK must be running and RESET inac-

tive during programming. This port is used to program and to

read all internal registers. The ﬁrst 8 bits always represent

the address followed immediately by the 8 data bits for that

register. The two LSBs of address are don’t care. The serial

transfers are accomplished through the serial data pin (SD).

SD is a bidirectional serial data bus. An Address Strobe (AS),

Chip Select (CS), and Read/Write (R/W) are also required as

handshake signals for this port. The clock used in conjunction

with the address and data on SD is SCLK. This clock is pro-

vided by the external source and it is an input to the

HSP3824. The timing relationships of these signals are illus-

trated on Figure 3 and 4. AS is active high during the clock-

ing of the address bits. R/W is high when data is to be read,

and low when it is to be written. CS must be active (low) dur-

ing the entire data transfer cycle. CS selects the device. The

serial control port operates asynchronously from the TX and

RX ports and it can accomplish data transfers independent

of the activity at the other digital or analog ports. CS does

not effect the TX or RX operation of the device; impacting

only the operation of the Control port. The HSP3824 has 57

internal registers that can be conﬁgured through the control

port. These registers are listed in the Conﬁguration and Con-

trol Internal Register table. Table 1 lists the conﬁguration reg-

ister number, a brief name describing the register, and the

HEX address to access each of the registers. The type indi-

cates whether the corresponding register is Read only (R) or

Read/Write (R/W). Some registers are two bytes wide as

indicated on the table (high and low bytes).

• The TX Port, which is used to accept the data that needs

to be transmitted from the network processor.

• The RX Port, which is used to output the received demod-

ulated data to the network processor.

• The Control Port, which is used to conﬁgure, write and/or

read the status of the internal HSP3824 registers.

In addition to these primary digital interfaces the device

includes a byte wide parallel Test Port which can be conﬁgured

to output various internal signals and/or data (i.e. PN acquisi-

tion indicator, Correlator magnitude output etc.). The device can

also be set into various power consumption modes by external

control. The HSP3824 contains three Analog to Digital (A/D)

converters. The analog interfaces to the HSP3824 include, the

In phase (I) and quadrature (Q) data component inputs, and the

RF signal strength indicator input. A reference voltage divider is

also required external to the device.

HSP3824

I (ANALOG)

ANALOG

Q (ANALOG)

TXD

INPUTS

RSSI (ANALOG) TXCLK

TX_PORT

RX_PORT

TX_RDY

V_REFN

RXD

A/D

REFERENCE

V_REFP

RXC

MD_RDY

CS

TX_PE

RX_PE

RESET

POWER

DOWN

SIGNALS

SD

SCLK

R/W

CONTROL_PORT

8

TEST

PORT

TEST

AS

FIGURE 2. EXTERNAL INTERFACES

FIRST ADDRESS BIT IN

FIRST DATABIT OUT

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

SCLK

SD

7

6

5

4

3

2

1

7

6

5

4

3

2

1

0

MSB

ADDRESS IN

MSB

DATA OUT

LSB

AS

R/W

CS

NOTE: Using falling edge SCLK to generate address/control and capture read data.

FIGURE 3. CONTROL PORT READ TIMING

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

SCLK

SD

AS

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

ADDRESS IN

MSB

DATA IN

LSB

R/W

CS

NOTE: Using falling edge SCLK to generate address/control and data.

FIGURE 4. CONTROL PORT WRITE TIMING

7

HSP3824

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST

CONFIGURATION

REGISTER

ADDRESS HEX

NAME

Modem Config. Register A

Modem Config. Register B

Modem Config. Register C

Modem Config. Register D

Internal Test Register A

TYPE

R/W

R

CR0

CR1

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

64

68

6C

70

74

78

7C

80

CR2

CR3

CR4

CR5

Internal Test Register B

CR6

Internal Test Register C

Modem Status Register A

Modem Status Register B

I/O Definition Register

CR7

R

CR8

R

CR9

R/W

R

CR10

CR11

CR12

CR13

CR14

CR15

CR16

CR17

CR18

CR19

CR20

CR21

CR22

CR23

CR24

CR25

CR26

CR27

CR28

CR29

CR30

CR31

CR32

RSSI Value Register

ADC_CAL_POS Register

ADC_CAL_NEG Register

TX_Spread Sequence (High)

TX_Spread Sequence (Low)

Scramble_Seed

R/W

R

Scramble_Tap (RX and TX)

CCA_Timer_TH

CCA_Cycle_TH

RSSI_TH

RX_Spread Sequence (High)

RX_Spread Sequence (Low)

RX_SQ1_ ACQ (High) Threshold

RX-SQ1_ ACQ (Low) Threshold

RX-SQ1_ ACQ (High) Read

RX-SQ1_ ACQ (Low) Read

RX-SQ1_ Data (High) Threshold

RX-SQ1-SQ1_ Data (Low) Threshold

RX-SQ1_ Data (High) Read

RX-SQ1_ Data (Low) Read

RX-SQ2_ ACQ (High) Threshold

RX-SQ2- ACQ (Low) Threshold

RX-SQ2_ ACQ (High) Read

R

R/W

R

R/W

R

8

HSP3824

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (Continued)

CONFIGURATION

REGISTER

CR33

CR34

CR35

CR36

CR37

CR38

CR39

CR40

CR41

CR42

CR43

CR44

CR45

CR46

CR47

CR48

CR49

CR50

CR51

CR52

CR53

CR54

CR55

CR56

NAME

RX-SQ2_ ACQ (Low) Read

RX-SQ2_Data (High) Threshold

RX-SQ2_Data (Low) Threshold

RX-SQ2_Data (High) Read

RX-SQ2_Data (Low) Read

RX_SQ_Read; Full Protocol

Reserved (must load 00h)

UW_Time Out_Length

SIG_DBPSK Field

TYPE

R

ADDRESS HEX

84

88

R/W

R

8C

90

R

94

R

98

W

9C

A0

A4

A8

AC

B0

B4

B8

BC

C0

C4

C8

CC

D0

D4

D8

DC

E0

W

R/W

R

SIG_DQPSK Field

RX_SER_Field

RX_LEN Field (High)

RX_LEN Field (Low)

RX_CRC16 (High)

R

RX_CRC16 (Low)

R

UW (High)

R/W

R

UW (Low)

TX_SER_F

TX_LEN (High)

TX_LEN (LOW)

TX_CRC16 (HIGH)

TX_CRC16 (LOW)

R

TX_PREM_LEN

R/W

9

HSP3824

The second transmit scenario supported by the HSP3824 is

TX Port

when the preamble and header information are provided by

the external data source. During this mode TX_RDY is not

required as part of the TX handshake. The HSP3824 will

immediately start transmitting the data available on TXD

upon assertion of TX_PE. The timing diagram of this TX sce-

nario, where the preamble and header are generated exter-

nal to the HSP3824, is illustrated on Figure 5.

The transmit data port accepts the data that needs to be

transmitted serially from an external data source. The data is

modulated and transmitted as soon as it is received from the

external data source. The serial data is input to the

HSP3824 through TXD using the falling edge of TXCLK to

clock it in the HSP3824. TXCLK is an output from the

HSP3824. A timing scenario of the transmit signal hand-

shakes and sequence is shown on timing diagram Figures 5

and 6.

One other signal that can be used for certain applications as

part of the TX interface is the Clear Channel Assessment

(CCA) signal which is an output from the HSP3824. The

CCA is programmable and it is described with more detail in

the Transmitter section of this document. CCA provides the

indication that the channel is clear of energy and the trans-

mission will not be subject to collisions. CCA can be moni-

tored by the external processor to assist in deciding when to

initiate transmissions. The CCA indication can bypassed or

ignored by the external processor. The state of the CCA

does not effect the transmit operation of the HSP3824.

TX_PE alone will always initiate the transmit state indepen-

dent of the state of CCA. Signals TX_RDY, TX_PE and

TXCLK can be set individually, by programming Conﬁgura-

tion Register (CR) 9, as either active high or active low sig-

nals.

The external processor initiates the transmit sequence by

asserting TX_PE. TX_PE envelopes the transmit data

packet on TXD. The HSP3824 responds by generating

TXCLK to input the serial data on TXD. TXCLK will run until

TX_PE goes back to its inactive state indicating the end of

the data packet. There are two possible transmit scenarios.

One scenario is when the HSP3824 internally generates the

preamble and header information. During this mode the

external source needs to provide only the data portion of the

packet. The timing diagram of this mode is illustrated on Fig-

ure 6. When the HSP3824 generates the preamble inter-

nally, assertion of TX_PE will initialize the generation of the

preamble and header. TX_RDY, which is an output from the

HSP3824, is used to indicate to the external processor that

the preamble has been generated and the device is ready to

receive the data packet to be transmitted from the external

processor. The TX_RDY timing is programmable in case the

external processor needs several clocks of advanced notice

before actual data transmission is to begin.

The transmit port is completely independent from the opera-

tion of the other interface ports including the RX port, there-

fore supporting a full duplex mode.

TXCLK

TX_PE

TXD

LSB

DATA PACKET

MSB

DUMMY BITS TO CLEAR MOD PATH

PREAMBLE - HEADER

MSB OF LAST HEADER FIELD

NOTE: Preamble/Header and Data is transmitted LSB ﬁrst TX_RDY is inactive Logic 0 when generated externally. TXD shown generated

from rising edge TXCLK.

FIGURE 5. TX PORT TIMING (EXTERNAL PREAMBLE)

TXCLK

TX_PE

TXD

PREAMBLE - HEADER

LSB

DATA PACKET

MSB

DUMMY BITS TO CLEAR MOD PATH

MSB OF LAST HEADER FIELD

TX_RDY

NOTE: Preamble/Header and Data is transmitted LSB ﬁrst. TXD shown generated from rising edge TXCLK. TX_RDY generated from falling edge.

FIGURE 6. TX PORT TIMING (INTERNAL PREAMBLE)

10

HSP3824

I/Q ADC Interface

RX Port

The timing diagram Figure 7 illustrates the relationships The PRISM baseband processor chip (HSP3824) includes

between the various signals of the RX port. The receive data two 3-bit Analog to Digital converters (ADCs) that sample

port serially outputs the demodulated data from RXD. The the analog input from the IF down converter. The I/Q ADC

data is output as soon as it is demodulated by the HSP3824. clock, MCLK, samples at twice the chip rate. The maximum

RX_PE must be at its active state throughout the receive sampling rate is 44MHz (power supply: 3.3V to 5.0V) or

operation. When RX_PE is inactive the device's receive 33MHz (power supply 2.7V to 5.5V).

functions, including acquisition, will be in a stand by mode.

The interface speciﬁcations for the I and Q ADCs are listed

on Table 2 below.

RXCLK is an output from the HSP3824 and is the clock for

the serial demodulated data on RXD. MD_RDY is an output

from the HSP3824 and it envelopes the valid data on RXD.

The HSP3824 can be also programmed to ignore error

detections during the CCITT - CRC 16 check of the header

ﬁelds. If programmed to ignore errors the device continues to

output the demodulated data in its entirety regardless of the

CCITT - CRC 16 check result. This option is programmed

through CR 2, bit 5.

TABLE 2. I, Q, ADC SPECIFICATIONS

PARAMETER

MIN

TYP

MAX

Full Scale Input Voltage (V

Input Bandwidth (-0.5dB)

Input Capacitance (pF)

Input Impedance (DC)

)

0.25

0.50

1.0

P-P

-

20MHz

-

5kΩ

-

5

-

FS (Sampling Frequency)

-

44MHz

Note that RXCLK becomes active after acquisition, well

before valid data begins to appear on RXD and MD_RDY is

asserted. MD_RDY returns to its inactive state under the fol-

lowing conditions:

The voltages applied to pin 16,V_REFPand pin 17, V_REFNset

the references for the internal I and Q ADC converters. In

addition, V_REFPis also used to set the RSSI ADC converter

reference. For a nominal 500mV_P-P, the suggested V_REFP

voltage is 1.75V, and the suggested V_REFNis 0.93V. V_REFN

should never be less than 0.25V. Since these ADCs are

intended to sample AC voltages, their inputs are biased

internally and they should be capacitively coupled.

• The number of data symbols, as deﬁned by the length ﬁeld

in the protocol, has been received and output through

RXD in its entirety (normal condition).

• PN tracking is lost during demodulation.

• RX_PE is deactivated by the external controller.

The ADC section includes a compensation (calibration) cir-

cuit that automatically adjusts for temperature and compo-

nent variations of the RF and IF strips. The variations in gain

of limiters, AGC circuits, ﬁlters etc. can be compensated for

up to ±4dB. Without the compensation circuit, the ADCs

could see a loss of up to 1.5 bits of the 3 bits of quantization.

The ADC calibration circuit adjusts the ADC reference volt-

ages to maintain optimum quantization of the IF input over

this variation range. It works on the principle of setting the

reference to insure that the signal is at full scale (saturation)

a certain percentage of the time. Note that this is not an

AGC and it will compensate only for slow variations in signal

levels (several seconds).

MD_RDY can be conﬁgured through CR 9, bit 6 to be active

low, or active high. Energy Detect (ED) pin 45 (Test port),

and Carrier Sense (CRS) pin 46 (Test port), are available

outputs from the HSP3824 and can be useful signals for an

effective RX interface design. Use of these signals is

optional. CRS and ED are further described within this docu-

ment. The receive port is completely independent from the

operation of the other interface ports including the TX port,

supporting therefore a full duplex mode.

RXCLK

RX_PE

CRS (TEST 7)

PROCESSING

PREAMBLE/HEADER

MD_RDY

RXD

LSB

DATA

MSB

NOTE: MD_RDY active after CRC16.

FIGURE 7. RX PORT TIMING

11

HSP3824

TABLE 3. ADC CALIBRATION

CR 1 ADC CALIBRATION CIRCUIT

The procedure for setting the ADC references to accommo-

date various input signal voltage levels is to set the reference

voltages so that the ADC calibration circuit is operating at

half scale. This leaves the maximum amount of adjustment

room for circuit tolerances.

CR 1

BIT 0

BIT 1

CONFIGURATION

Automatic real time adjustment of reference.

Reference set at mid scale.

0

1

0

1

0

1

Figure 8 illustrates the suggested interface conﬁguration for

the ADCs and the reference circuits.

Reference held at most recent value.

Reference set at mid scale.

I

I_IN

0.01µF

RSSI ADC Interface

Q

Q_IN

The Receive Signal Strength Indication (RSSI) analog signal is

input to a 6-bit ADC, indicating 64 discrete levels of received

signal strength. This ADC measures a DC voltage, so its input

must be DC coupled. Pin 16 (V_REFP) sets the reference for the

RSSI ADC converter. V_REFPis common for the I and Q and

RSSI ADCs. The RSSI signal is used as an input to the pro-

grammable Clear Channel Assessment algorithm of the

HSP3824. The RSSI ADC output is stored in an 8-bit register

(CR10) and it is updated at the symbol rate for access by the

external processor to assist in network management.

3.9K

2V

V_REFP

0.01µF

8.2K

9.1K

V_REFN

HSP3824

FIGURE 8. INTERFACES

The interface speciﬁcations for the RSSI ADC are listed on

Table 4 below (V_REFP= 1.75V).

ADC Calibration Circuit and Registers

The ADC compensation or calibration circuit is designed to

optimize ADC performance for the I and Q inputs by main-

taining the full 3-bit resolution of the outputs. There are two

registers (CR 11 AD_CAL_POS and CR 12 AD_CAL_NEG)

that set the parameters for the internal I and Q ADC calibra-

tion circuit.

TABLE 4. RSSI ADC SPECIFICATIONS

PARAMETER

Full Scale Input Voltage

Input Bandwidth (0.5dB)

Input Capacitance

MIN

TYP

MAX

-

1MHz

-

1.15

-

7pF

-

Input Impedance (DC)

1M

Both I and Q ADC outputs are monitored by the ADC calibra-

tion circuit and if either has a full scale value, a 24-bit accu-

mulator is incremented as deﬁned by parameter

AD_CAL_POS. If neither has a full scale value, the accumu-

lator is decremented as deﬁned by parameter

AD_CAL_NEG.

Test Port

The HSP3824 provides the capability to access a number of

internal signals and/or data through the Test port, pins TEST

0-7. In addition pin 1 (TEST_CK) is an output clock that can

be used in conjunction with the data coming from the test

port outputs. The test port is programmable through conﬁgu-

ration register (CR5).

A loop gain reduction is accomplished by using only the 5

MSBs out of the 24 bits to drive a D/A converter that adjusts

the ADCs reference. The compensation adjustment is

updated at 2kHz rate for a 2 MBPS operation. The ADC cali-

bration circuit is only intended to remove slow component

variations.

There are 9 test modes assigned to the PRISM test port

listed in the Test Modes Table 5.

TABLE 5. TEST MODES

The ratio of the values from the two registers CR11 and

CR12 set the probability that either the I or Q ADC converter

will be at the saturation. The probability is set by

(AD_CAL_POS)/(AD_CAL_NEG).

MODE DESCRIPTION TEST_CLK

TEST (7:0)

0

1

2

3

Normal

Operation

TXCLK

CRS, ED, “000”, Initial

Detect, Reserved (1:0)

Correlator Test

Mode

TXCLK

Mag (7:0)

This also sets the levels so that operation with either NOISE

or DPSK is approximately the same. It is assumed that the

RF and IF sections of the receiver have enough gain to

cause limiting on thermal noise. This will keep the levels at

the ADC approximately same regardless of whether signal is

present or not.

Frequency Test DCLK

Mode

Frq Reg (7:0)

Phase Test

Mode

DCLK

Phase (7:0)

4

5

NCO Test Mode DCLK

NCO Phase Accum Reg

SQ Test Mode

LoadSQ

SQ2 (15:8) Phase

Variance

The ADC calibration voltage is automatically held during

transmit in half duplex operation.

6

7

Bit Sync Test

Mode 1

RXCLK

Bit Sync Accum (7:0)

The ADC calibration circuit operation can be deﬁned through

CR 1, bits 1 and 0. Table 3 illustrates the possible

conﬁgurations.

Bit Sync Test

Mode 2

LoadSQ

SQ (14:7) Bit Sync Ref-

Data

12

HSP3824

TABLE 5. TEST MODES (Continued)

MODE DESCRIPTION TEST_CLK TEST (7:0)

CRS, ED, “0”, ADCal (4:0)

SQ1 - Signal Quality measure #1. Contents of the bit sync

accumulator 8 MSBs of most recent 16-bit stored value.

A/D_Cal_ck - Clock for applying A/D calibration corrections.

8

A/D Cal Test

Mode

A/D

CAL_CK

ADCal - 5-bit value that drives the D/A adjusting the A/D ref-

erence.

9

Reserved

10

(0Ah)

External AGC Control

11

12

13

14

15

Reserved

The ADC cal output (pin 26) is a binary signal that ﬂuctuates

between logic levels as the signals in the I and Q channels

are either at full scale or not. If the input level is too high, this

output will have a higher duty cycle, and visa versa. Thus,

this signal could be integrated with an R-C ﬁlter to develop

an AGC control voltage. The AGC feedback should be

designed to drive it to 50% duty cycle. In the case that an

external AGC is in use then the ADC calibration circuit must

not be programmed for automatic level adjustment.

Deﬁnitions

Normal - Device in the full protocol mode (Mode 3).

TXCLK - Transmit clock (PN rate).

Initial Detect - Indicates that Signal Quality 1 and 2 (SQ1

and SQ2) exceed their programmed thresholds. Signal qual-

ities are a function of phase error and correlator magnitude

outputs.

Power Down Modes

The power consumption modes of the HSP3824 are con-

trolled by the following control signals.

Receiver Power Enable (RX_PE,pin 33), which disables the

receiver when inactive.

ED - energy detect indicates that the RSSI value exceeds its

programmed threshold.

CRS - indicates that a signal has been acquired (PN acquisi-

tion).

Transmitter Power Enable (TX_PE, pin 2), which disables the

transmitter when inactive.

Mag - Magnitude output from the correlator.

DCLK - Data symbol clock.

Reset (RESET, pin 28), which puts the receiver in a sleep

mode when it is asserted at least 2 MCLKs after RX_PE is

set at its inactive state. The power down mode where, both

RESET and RX_PE are used is the lowest possible power

consumption mode for the receiver. Exiting this mode

requires a maximum of 10µs before the device is back at its

operational mode.

FrqReg - Contents of the NCO frequency register.

Phase - phase of signal after carrier loop correction.

NCO PhaseAccumReg - Contents of the NCO phase accu-

mulation register.

LoadSQ - Strobe that samples and updates Signal Quality,

SQ1 and SQ2 values.

The contents of the Conﬁguration Registers is not effected

by any of the power down modes. The external processor

does not have access and cannot modify any of the CRs

during the power down modes. No reconﬁguration is

required when returning to operational modes.

SQ2 - Signal Quality measure #2. Signal phase variance

after removal of data, 8 MSBs of most recent 16-bit stored

value.

Table 6 describes the power down modes available for the

HSP3824 (V_CC= 5.0V). The table values assume that all

other inputs to the part (MCLK, SCLK, etc.) continue to run.

RXCLK - Receive clock (RX sample clock). Nominally 22MHz.

BitSyncAccum - Real time monitor of the bit synchroniza-

tion accumulator contents, mantissa only.

TABLE 6. POWER DOWN MODES

POWER

(22MHz)

POWER

(44MHz)

RX_PE

TX_PE

RESET

DEVICE STATE

Inactive

Active

40mW

100mW

Both transmit and receive functions disabled. Device in sleep

mode. Control Interface is still active. Register values are main-

tained. Device will return to its active state within 10µs.

Inactive

Active

Inactive

Active

Inactive

Active

325mW

335mW

340mW

475mW

500mW

525mW

Both transmit and receive operations disabled. Device will become

in its active state within 1µs.

Receiver operations disabled. Receiver will return in its active state

within 1µs.

Inactive

Active

Transmitter operations disabled. Transmitter will return to its active

state within 2 MCLKs.

Active

13

HSP3824

Reset

The RESET signal is used during the power down mode as The transmitter accepts data from the external source,

described in the Power Down Mode section. The RESET scrambles it, differentially encodes it as either DBPSK or

does not impact any of the internal conﬁguration registers DQPSK, and mixes it with the BPSK PN spreading. The

when asserted. Reset does not set the device in a default baseband digital signals are then output to the external IF

conﬁguration, the HSP3824 must always be programmed on modulator.

power up. The HSP3824 must be programmed with RESET

The transmitter includes a programmable PN generator that

inactive.

can provide 11, 13, 15 or 16 chip sequences. The transmitter

also contains a programmable clock divider circuit that

allows for various data rates. The master clock (MCLK) can

Transmitter Description

be a maximum of 44MHz.

The HSP3824 transmitter is designed as a Direct Sequence

Spread Spectrum DBPSK/DQPSK modulator. It can handle

data rates of up to 4 MBPS (refer to AC and DC speciﬁca-

tions). The major functional blocks of the transmitter include

a network processor interface, DBPSK/DQPSK modulator, a

data scrambler and a PN generator, as shown on Figure 9.

The chip rates are programmed through CR3 for TX and

CR2 for RX. In addition the data rate is a function of the

sample clock rate (MCLK) and the number of PN bits per

symbol.

The following equations show the Symbol rate for both TX

and RX as a function of MCLK, Chips per symbol and N.

The transmitter has the capability to either generate its own

synchronization preamble and header or accept the pream-

ble and header information from an external source. In the

ﬁrst case, the transmitter knows when to make the DBPSK

to DQPSK switchover, as required.

N is a programmable parameter through conﬁguration regis-

ters CR 2and CR 3. The value of N is 2, 4, 8 or 16. N is used

internally to divide the MCLK to generate other required

clocks for proper operation of the device.

The preamble and header are always transmitted as DBPSK

waveforms while the data packets can be conﬁgured to be

either DBPSK or DQPSK. The preamble is used by the

receiver to achieve initial PN synchronization while the

header includes the necessary data ﬁelds of the communi-

cations protocol to establish the physical layer link. There is

a choice of four potential preamble/header formats that the

HSP3824 can generate internally. These formats are

referred to as mode 0, 1, 2 and 3. Mode 0 uses the minimum

number of available header ﬁelds while mode 3 is a full pro-

tocol mode utilizing all available header ﬁelds. The number

of the synchronization preamble bits is programmable.

Symbol Rate = MCLK/(N x Chips per Symbol).

The bit rate Table 7 shows examples of the relationships

expressed on the symbol rate equation.

The modulator is capable of switching rate automatically in

the case where the preamble and header information are

DBPSK modulated, and the data is DQPSK modulated.

The modulator is completely independent from the demodu-

lator, allowing the PRISM baseband processor to be used in

full duplex operation.

PROCESSOR

INTERFACE

CONTROL PORT

TX_I_OUT

I_OUT

DBPSK/DQPSK

DIFFERENTIAL ENCODER

TX_Q_OUT

SPREADER

Q_OUT

PACKET

FORMAT/

CRC-16

TX PORT

TX_SCRAM_SEED

7

TX_DATA

SHIFT REG

7

TX_SPREAD_STQ

TX_BIT_CK

16

SCRAM_TAPS

TX_CHIP_CK

7

SHIFT REG

SCRAMBLER

PN GENERATOR

FIGURE 9. MODULATOR DIAGRAM

14

HSP3824

TABLE 7. BIT RATE TABLE EXAMPLES

DATA RATE

FOR 11

CHIPS/BIT

(MBPS)

DATA RATE

FOR 13

CHIPS/BIT

(MBPS)

DATA RATE

FOR 15

CHIPS/BIT

(MBPS)

DATA RATE

FOR 16

CHIPS/BIT

(MBPS)

SAMPLE

CLOCK MCLK TX SETUP CR 3

DATA

MODULATION

RX SET UP

CR 2 BITS 4, 3

(MHz)

BITS 4, 3

00 (N = 2)

01 (N = 4)

10 (N = 8)

11 (N = 16)

00 (N = 2)

01 (N = 4)

10 (N = 8)

11 (N = 16)

DQPSK

DBPSK

44

00

01

10

11

00

01

10

11

4

2

3.385

1.692

0.846

0.423

1.692

0.846

0.423

0.212

2.933

1.467

0.733

0.367

1.467

0.733

0.367

0.183

2.75

22

1.375

0.688

0.344

1.375

0.688

0.344

0.171

11

1

5.5

44

0. 5

2

22

1

11

0.5

0.25

5.5

into consideration the noise and interference requirements in

conjunction with the desired probability of detection vs prob-

ability of false alarm for signal acquisition.

Header/Packet Description

The HSP3824 is designed to handle continuous or pack-

etized Direct Sequence Spread Spectrum (DSSS) data

transmissions. The HSP3824 can generate its own preamble

and header information or it can accept them from an exter-

nal source.

The ﬁve available ﬁelds for the header are:

SFD Field (16 Bits) - This ﬁeld carries the ID to establish

the link. This is a mandatory ﬁeld for the HSP3824 to estab-

lish communications. The HSP3824 will not declare a valid

data packet, even if it PN acquires, unless it detects the spe-

ciﬁc SFD. The SFD ﬁeld is required for both Internal pream-

ble/header generation and External preamble/header

generation. The HSP3824 receiver can be programmed to

time out searching for the SFD. The timer starts counting the

moment that initial PN synchronization has been established

from the preamble.

When preamble and header are internally generated the

device supports a synchronization preamble up to 256 sym-

bols, and a header that can include up to ﬁve ﬁelds. The pre-

amble size and all of the ﬁelds are programmable. When

internally generated the preamble is all 1's (before entering

the scrambler). The actual transmitted pattern of the pream-

ble will be randomized by the scrambler if the user chooses

to utilize the data scrambling option.

Signal Field (8 Bits) - This ﬁeld indicates whether the data

packet that follows the header is modulated as DBPSK or

DQPSK. In mode 3 the HSP3824 receiver looks at the signal

ﬁeld to determine whether it needs to switch from DBPSK

demodulation into DQPSK demodulation at the end of the

always DBPSK preamble and header ﬁelds.

When the preamble is externally generated the user can

choose any desirable bit pattern. Note though, that if the pre-

amble bits will be processed by the scrambler which will alter

the original pattern unless it is disabled.

The preamble is always transmitted as a DBPSK waveform

with a programmable length of up to 256 symbols long. The

HSP3824 requires at least 126 preamble symbols to acquire

in a dual antenna conﬁguration (diversity), or a minimum of

78 preamble symbols to acquire under a single antenna con-

ﬁguration. The exact number of necessary preamble sym-

bols should be determined by the system designer, taking

Service Field (8 Bits) - This ﬁeld can be utilized as required

by the user.

Length Field (16 Bits) - This ﬁeld indicates the number of

data symbols contained in the data packet. The receiver can

be programmed to check the length ﬁeld in determining

CR #0 BITS

HEADER

COUNT

BIT 4 BIT 3

N (Preamble) +

16 (Header) Bits

0

1

0

1

0

1

Preamble (SYNC) SFD

N Bits Up to 256) 16 Bits

N (Preamble) +

32 (Header) Bits

Preamble (SYNC) SFD

N Bits Up to 256) 16 Bits

CRC16

16 Bits

N (Preamble) +

48 (Header) Bits

Preamble (SYNC) SFD

N Bits Up to 256) 16 Bits

Length Field CRC16

16 Bits

N (Preamble) +

64 (Header) Bits

Preamble (SYNC) SFD

N Bits Up to 256) 16 Bits

Signal Field

8 Bits

Service Field Length Field CRC16

8 Bits

16 Bits

HEADER

PREAMBLE

FIGURE 10. PREAMBLE/HEADEAR MODES

15

HSP3824

when it needs to de-assert the MD_RDY interface signal. The following Conﬁguration Registers (CR)are used to program

MD_RDY envelopes the received data packet as it is being the preamble/header functions, more programming details

output to the external processor.

about these registers can be found in the Control Registers

section of this document:

CCITT - CRC 16 Field (16 Bits) - This ﬁeld includes the 16-

bit CCITT - CRC 16 calculation of the ﬁve header ﬁelds. This

value is compared with the CCITT - CRC 16 code calculated

at the receiver. The HSP3824 receiver can be programmed

to drop the link upon a CCITT - CRC 16 error or it can be

programmed to ignore the error and to continue with data

demodulation.

CR 0 - Deﬁnes one of the four modes (bits 4, 3) for the TX.

Deﬁnes whether the SFD timer is active (bit 2). Deﬁnes whether

the receiver should stop demodulating after the number of sym-

bols indicated in the Length ﬁeld has been met.

CR 2 - Deﬁnes to the receiver one of the four protocol modes

(bits 1, 0). Indicates whether any detected CCITT - CRC 16

errors need to reset the receiver (return to acquisition) or to

ignore them and continue with demodulation (bit 5). Speciﬁes a

128-bit preamble or an 80-bit preamble (bit 2).

The CRC or cyclic Redundancy Check is a CCITT CRC-16

FCS (frame check sequence). It is the ones compliment of

the remainder generated by the modulo 2 division of the pro-

tected bits by the polynominal:

CR 3 - Deﬁnes internal or external preamble generation (bit 2).

Indicates to the receiver the data packet modulation (bit 0), note

that in mode 3 the contents of this register are overwritten by

the information in the received signal ﬁeld of the header. CR 3

speciﬁes the data modulation type used to the transmitter (bit

1). Bit 1 deﬁnes the contents of the signaling ﬁeld in the header

to indicate either DBPSK or DQPSK modulation.

X¹⁶+ x¹²+ x⁵+ 1

The protected bits are processed in transmit order. All CRC

calculations are made prior to data scrambling. A shift regis-

ter with two taps is used for the calculation. It is preset to all

ones and then the protected ﬁelds are shifted through the

register. The output is then complimented and the residual

shifted out MSB ﬁrst.

CR 41 - Deﬁnes the length of time that the demodulator

searches for the SFD before returning to acquisition.

CR 42 - The contents of this register indicate that the transmit-

ted data is DBPSK. If CR 4-bit 1 is set to indicate DBPSK mod-

ulation then the contents of this register are transmitted in the

signal ﬁeld of the header.

When the HSP3824 generates the preamble and header inter-

nally it can be conﬁgured into one of four link protocol modes.

Mode 0 - In this mode the preamble is programmable up to 256

bits (all 1's) and the SFD ﬁeld is the only ﬁeld utilized for the

header. This mode only supports DBPSK transmissions for the

entire packet (preamble/header and data).

CR 43 - The contents of this register indicates that the transmit-

ted data is DQPSK. If CR 4-bit 1 is set to indicate DQPSK mod-

ulation then the contents of this register are transmitted in the

signal ﬁeld of the header.

Mode 1 - In this mode the preamble is programmable up to 256

bits (all 1's) and the SFD and CCITT - CRC 16 ﬁelds are used

for the header. The data that follows the header can be either

DBPSK or DQPSK. The receiver and transmitter must be pro-

grammed to the proper modulation type.

CR 44, 45, 46, 47, 48 - Status, read only, registers that indicate

the service ﬁeld, data length ﬁeld and CCITT - CRC 16 ﬁeld val-

ues of the received header.

CR 49, 50 - Deﬁnes the transmit SFD ﬁeld value of the header.

The receiver will always search to detect this value before it

declares a valid data packet.

Mode 2 - In this mode the preamble is programmable up to 256

bits (all 1's) and the SFD, Length Field, and CCITT - CRC 16

ﬁelds are used for the header. The data that follows the header

can be either DBPSK or DQPSK. The receiver and transmitter

must be programmed to the proper modulation type.

CR 51 - Deﬁnes the contents of the transmit service ﬁeld.

CR 52, 53 - Deﬁnes the value of the transmit data length ﬁeld.

This value includes all symbols following the last header ﬁeld

symbol.

Mode 3 - In this mode the preamble is programmable up to

256 bits (all 1's). The header in this mode is using all available

ﬁelds. In mode 3 the signal ﬁeld deﬁnes the modulation type of

the data packet (DBPSK or DQPSK) so the receiver does not

need to be preprogrammed to anticipate one or the other. In

this mode the device checks the Signal ﬁeld for the data

packet modulation and it switches to DQPSK if it is deﬁned as

such in the signal ﬁeld. Note that the preamble and header

are always DBPSK the modulation deﬁnition applies only for

the data packet. This mode is called the full protocol mode in

this document.

CR 54,55 - Status, read only, registers indicating the calculated

CCITT - CRC 16 value of the most recently transmitted header.

CR 56 - Deﬁnes the number of preamble synchronization bits

that need to be transmitted when the preamble is internally

generated. These symbols are used by the receiver for initial

PN acquisition and they are followed by the header ﬁelds.

The full protocol requires a setting of 128d = 80h. For other

applications, in general increasing the preamble length will

improve low signal to noise acquisition performance at the cost

of greater link overhead. For dual receive antenna operation,

the minimum suggested value is 128d = 80h. For single receive

antenna operation, the minimum suggested value is 80d = 50h.

These suggested values include a 2 symbol TX power ampliﬁer

ramp up. If an AGC is used, its worst case settling time in sym-

bols should be added to these values.

Figure 10 summarizes the four preamble/head or modes. In the

case that the device is conﬁgured to accept the preamble and

header from an external source it still needs to be conﬁgured in

one of the four modes (0:3). Even though the HSP3824 trans-

mitter does not generate the preamble and header information

the receiver needs to know the mode in use so it can proceed

with the proper protocol and demodulation decisions.

16

HSP3824

spectrum to be concentrated at the discrete lines deﬁned by

PN Generator Description

the spreading code and potentially cause interference with

other narrow band users at these frequencies. Additionally,

the DS system itself would be moderately more susceptible

to interference at these frequencies. With scrambling, the

spectrum is more uniform and these negative effects are

reduced, in proportion with the scrambling code length.

The spread function for this radio uses short sequences. The

same sequence is applied to every bit. All transmitted symbols,

preamble/header and data are always spread by the PN

sequence at the chip rate. The PN sequence sets the Process-

ing Gain (PG) of the Direct Sequence receiver. The HSP3824

can be programmed to utilize 11,13,15 and 16 bit sequences.

Given the length of these programmable sequences the PG

range of the HSP3824 is:

Figure 11 illustrates an example of a non scrambled trans-

mission using an 11-bit code with DBPSK modulation with

alternate 1's and 0's as data. The data rate is 2 MBPS while

the spread rate or chip rate is at 11 MCPS. The 11 spectral

lines resulting from the PN code can be clearly seen in Fig-

ure 11. In Figure 12, the same signal is transmitted but with

the scrambler being on. In this case the spectral lines have

been smeared.

From 10.41dB (10 LOG(11)) to 12.04dB (10 LOG(16))

The transmitter and receiver PN sequences can are pro-

grammed independently. This provides additional ﬂexibility to

the network designer.

The TX sequence is set through CR 13 and CR 14 while the

RX PN sequence is set through CR 20 and CR 21. A maximum

of 16 bits can be programmed between the pairs of these con-

ﬁguration registers. For TX Registers CR13 and CR14 contain

the high and low bytes of the sequence for the transmitter. In

addition Bits 5 and 6 of CR 4 deﬁne the sequence length in

chips per bit. CR 13, CR 14 and CR 4 must all be programmed

for proper functionality of the PN generator. The sequence is

transmitted MSB ﬁrst. When fewer than 16 bits are in the

sequence, the MSBs are truncated.

REF -24dBm

ATTEN 10dB

Scrambler and Data Encoder Description

The data coder the implements the desired DQPSK coding as

shown in the DQPSK Data Encoder table. This coding scheme

results from differential coding of the dibits. When used in the

DBPSK modes, only the 00 and 11 dibits are used. Vector rota-

tion is counterclockwise.

CENTER 280MHz

RES BW 300kHz

SPAN 50MHz

SWP 20ms

VBW 100kHz

FIGURE 11. UNSCRAMBLED DBPSK DATA OF ALTERNATE

1’s/0’s SPREAD WITH AN 11-BIT SEQUENCE

TABLE 8. DQPSK DATA ENCODER

REF -25dBm

ATTEN 10dB

PHASE SHIFT

DIBITS

00

0

+90

+180

-90

01

11

10

The data scrambler is a self synchronizing circuit. It consist

of a 7-bit shift register with feedback from speciﬁed taps of

the register, as programmed through CR 16. Both transmitter

and receiver use the same scrambling algorithm. All of the

bits transmitted are scrambled, including data header and

preamble. The scrambler can be disabled.

CENTER 280MHz

RES BW 300kHz

SPAN 50MHz

SWP 20ms

VBW 100kHz

Scrambling provides additional spreading to each of the

spectral lines of the spread DS signal. The additional

spreading due to the scrambling will have the same null to

null bandwidth, but it will further smear the discrete spectral

lines from the PN code sequence. Scrambling might be nec-

essary for certain allocated frequencies to meet transmis-

sion waveform requirements as deﬁned by various

regulatory agencies.

FIGURE 12. SCRAMBLED DBPSK DATA OF ALTERNATE

1’s/0’s SPREAD WITH AN 11-BIT SEQUENCE

Another reason to scramble is to gain a small measure of pri-

vacy. The DS nature of the signal is easily demodulated with a

correlating receiver. Indeed, the data modulation can be

recovered from one of the discrete spectral lines with a narrow

band receiver (with a 10dB loss in sensitivity). This means

that the signal gets little security from the DS spreading code

alone. Scrambling adds a privacy feature to the waveform that

would require the listener to know the scrambling parameters

in order to listen in. When the data is scrambled it cannot be

In the absence of scrambling, the data patterns could con-

tain long strings of ones or zeros. This is deﬁnitely the case

with the a DS preamble which has a stream of up to 256

continuous ones. The continuous ones would cause the

17

HSP3824

defeated by listening to one of the scrambling spectral lines

Clear Channel Assessment (CCA) and

Energy Detect (ED) Description

since the unintentional receiver in this case is too narrow band

to recover the data modulation. This assumes though that

each user can set up different scrambling patterns There are

9 maximal length codes that can be utilized with a generator

of length 7. The different codes can be used to implement a

basic privacy scheme. It needs to be clear though that this

scrambling code length and the actual properties of such

codes are not a major challenge for a sophisticated intentional

interceptor to be listening in. This is why we refer to this

scrambling advantage as a communications privacy feature

as opposed to a secure communications feature.

The clear channel assessment (CCA) circuit implements the

carrier sense portion of a carrier sense multiple access

(CSMA) networking scheme. The Clear Channel Assess-

ment (CCA) monitors the environment to determine when it

is feasible to transmit. The result of the CCA algorithm is

available in real time through output pin 32 of the device. The

CCA state machine in the HSP3824 can be programmed as

a function of RSSI, energy detected on the channel, carrier

detection, and a number of on board watchdog timers to

time-out under certain conditions. The CCA can be also

completely by-passed allowing transmissions independent of

any channel conditions. The programmable CCA in combi-

nation with the visibility of the various internal parameters

(i.e. Energy Detection measurement results), can assist an

external processor in executing algorithms that can adapt to

the environment. These algorithms can increase network

throughput by minimizing collisions and reducing transmis-

sions liable to errors.

Scrambling is done by a polynomial division using a pre-

scribed polynomial. A shift register holds the last quotient

and the output is the exclusive-or of the data and the sum

of taps in the shift register. The taps and seed are program-

mable. The transmit scrambler seed is programmed by CR

15 and the taps are set with CR 16. Setting the seed is

optional, since the scrambler is self-synchronizing and it

will eventually synchronize with the incoming data after

ﬂashing the 7 bits stored from the previous transmission.

There are two measures that are used in the CCA assess-

ment. The receive signal strength (RSSI) which measures

the energy at the antenna and the carrier sense (CS), which

is triggered upon valid PN correlation of the baseband pro-

cessor (HSP3824). Both indicators are used since interfer-

ence can trigger the signal strength indication, but it will not

trigger the carrier sense. The carrier sense, however, is

slower to respond than the signal strength and it becomes

active only when a spread signal with identical PN code has

been detected, so it is not adequate in itself. Note that the

CS is also vulnerable to false alarms. The CCA looks for

changes in these measurements and decides its state based

on these measures and the time that has elapsed since the

Modulator Description

The modulator is designed to support both DBPSK and

DQPSK signals. The modulator is capable of automatically

switching its rate in the case where the preamble and header

are DBPSK modulated, and the data is DQPSK modulated.

The modulator can support date rates up to 4 MBPS. The pro-

gramming details of the modulator are given at the introduc-

tory paragraph of this section. The HSP3824 can support data

rates of up to 4 MBPS (DQPSK) with power supply voltages

between 3.3V and 5.0V and data rates of up to 3 MBPS with

supply voltages between 2.7V and 5.5V.

CONTINUOUS

CCA TO MAC

WATCHDOG TIMER

RESET ON CCA = CLEAR

RESET ON M ms TIMEOUT

RESET

WAIT FOR CHANGE

IN ED OR CS STATUS

OR TIMER TIMEOUT

ED

CS

ED >THRESH

CS < THRESH

ED >THRESH

ED < THRESH

CS > THRESH

ED > THRESH

CS< THRESH

ED < THRESH

CNT = CNT + 1

CLEAR

CS > THRESH

ED < THRESH

CCA

LATCH

HOLDS

LAST

RESET CNT

BUSY

DECISION

BUSY

CNT < N

CNT = N

CLEAR

RESET CNT

FIGURE 13. CCA FUNCTIONAL FLOW DIAGRAM

18

HSP3824

channel was last clear. If a source of interference makes it machine has four basic states. The ﬁrst state clears the CCA

look like the channel is occupied, the circuit will detect a sig- when both the CS and ED are inactive. This indicates that

nal without carrier and will wait a proscribed time before the channel is truly clear.

deciding to transmit over the interference.

The second state sets the CCA to BUSY when the CS is

The receive signal strength indication (RSSI) measurement active and the ED is inactive. This corresponds to a channel

is an analog input to the HSP3824 from the successive IF where the signal just went away or dropped below threshold

stage of the radio. The RSSI ADC converts it within the but the carrier is still being sensed. The third state sets the

baseband processor and it compares it to a programmable CCA to BUSY and resets the cycle counter when the ED and

threshold. This threshold is normally set to between -70 and CS are both active. This is an obviously busy channel.

-80dBm. This measure is used in the acquisition decision

The fourth state increments the cycle counter if the CS is

and is also passed to the clear channel assessment logic.

inactive and the ED is active, and sets the CCA to BUSY if

The state diagram in Figure 13 shows the operation of the

the count is less than N. This is where the channel has just

clear channel assessment state machine.

had a new signal come up and the carrier has not yet been

The energy detection (ED) signal is the digitized RSSI signal. acquired or where an interferer turns on.

The carrier sense (CS) input is derived from a combination of

If the cycle counter reaches N, the counter is reset and the

the Signal Quality 2 (SQ2) based on phase error and the Sig-

CCA is set to CLEAR. This happens on interference that per-

nal Quality 1(SQ1) based on PN correlator magnitude out-

sists. If the channel has interference, it may be low enough

puts. Both Signal Quality measures and the ED input are

to allow communications. The CCA state machine does

differentiated to sense when they change. These change

not inﬂuence any of the receive or transmit operations

detectors and the watchdog timer TIME OUT output are com-

within the HSP3824. The CCA algorithm output is an

bined to initiate a clear channel assessment decision.

indication to the network processor. The processor can

The CCA algorithm will always declare the channel busy if ignore this indicator and decide to have the HSP3824

CS is active. If only ED is active the state machine will ini- transmit regardless of the state of CCA.

tially declare a busy channel and at the same time it will start

The Conﬁguration registers effecting the CCA algorithm

timing ED until it meets the programmed time out count.

operation are summarized below (more programming details

When the time out expires the state machine will declare the

on these registers can be found under the Control Registers

channel as being clear even if the ED is still active. This will

section of this document).

prevent the transmitter locking out permanently on some

persisting interference. This time out period is programmable

by 2 parameters that deﬁne an inner count M and an outer

count N. The total time out period is determined by the time

corresponding to the product of MxN. The value of the inner

counter M is programmable through CR 17 while the value of

the outer counter N is programmable through CR 18. The

state machine cycles M times the N count before it asserts

CCA, declaring the channel as clear for transmission. Note

that the counters are automatically reset to restart the count

when CS is detected to be active. In summary the CCA state

The CCA output from pin 32 of the device can be deﬁned as

active high or active low through CR 9 (bit 5). The RSSI

threshold is set through CR19. If the actual RSSI value from

the ADC exceeds this threshold then ED becomes active.

The instantaneous RSSI value can be monitored by the exter-

nal network processor by reading CR 10. The programmable

thresholds on the two signal quality measurements are set

through CR22, 23, 30, and 31. Signal Quality 1 and 2 thresh-

olds derive the state of the Carrier Sense. More details on SQ

are included under the receiver section of this document.

A/D

SECTION

CORRELATOR

16TAP

I

SIGNAL QUALITY 1

MAGNITUDE AND

SYMBOL

TIMING

PHASE DISTRIBUTION

A/D

SECTION

CORRELATOR

16TAP

Q

SYMBOL TIMING

PHASE

ROTATE

PSK

DEMOD

DIF

DEC

DATA

DESCRAM

TIMING

CONTROL

RXD

PHASE

ERROR

AVG

PHASE

ERROR

SIGNAL QUALITY 2

ABS

AVG

PHASE

FREQ.

LEAD

/LAG

NCO

FILTER

FIGURE 14. DEMODULATOR BLOCK DIAGRAM

19

HSP3824

Finally, CR 17 and CR 18 are used to set the time out the resulting signals. These operations are illustrated in Fig-

parameters before the CCA algorithm declares permission ure 14 which is an overall block diagram of the receiver pro-

for transmission.

cessor. Input samples from the I and Q ADC converters are

correlated to remove the spreading sequence. The magni-

tude of the correlation pulse is used to determine the symbol

timing. The sample stream is decimated to the symbol rate

and the phase is corrected for frequency offset prior to PSK

demodulation. Phase errors from the demodulator are fed to

the NCO through a lead/lag ﬁlter to achieve phase lock. The

variance of the phase errors is used to determine signal

quality for acquisition and lock detection.

Receiver Description

The receiver portion of the baseband processor, performs

ADC conversion and demodulation of the spread spectrum

signal. It correlates the PN spread symbols, then demodu-

lates the DBPSK or DQPSK symbols. The demodulator

includes a frequency loop that tracks and removes the car-

rier frequency offset. In addition it tracks the symbol timing,

and differentially decodes and descrambles the data. The

data is output through the RX Port to the external processor.

Acquisition Description

The PRISM baseband processor uses either a dual antenna

mode of operation for compensation against multipath inter-

ference losses or a single antenna mode of operation with

faster acquisition times.

A common practice for burst mode communications systems

is to differentially modulate the signal, so that a DPSK

demodulator can be used for data recovery. This form of

demodulator uses each symbol as a phase reference for the

next one. It offers rapid acquisition and tolerance to rapid Two Antenna Acquisition

phase ﬂuctuations at the expense of lower bit error rate

(BER) performance.

During the 2 antenna (diversity) mode the two antennas are

scanned in order to ﬁnd the one with the best representation

The PRISM baseband processor, HSP3824 uses differential of the signal. This scanning is stopped once a suitable signal

demodulation for the initial acquisition portion of the pro- is found and the best antenna is selected.

cessing and then switches to coherent demodulation for the

A projected worst case time line for the acquisition of a signal

rest of the acquisition and data demodulation. The HSP3824

in the two antenna case is shown in Figure 15. The synchroni-

is designed to achieve rapid settling of the carrier tracking

zation part of the preamble is 128 symbols long followed by a

loop during acquisition. Coherent processing substantially

16-bit SFD. The receiver must scan the two antennas to deter-

improves the BER performance margin. Rapid phase ﬂuctu-

mine if a signal is present on either one and, if so, which has

ations are handled with a relatively wide loop bandwidth.

the better signal. The timeline is broken into 16 symbol blocks

The baseband processor uses time invariant correlation to (dwells) for the scanning process. This length of time is neces-

strip the PN spreading and polar processing to demodulate sary to allow enough integration of the signal to make a good

TX

POWER

RAMP

SFD

126 SYMBOL SYNC

16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 7S 7S

16 SYMBOLS

A1

2

A1

A2

A1

A2

A1

A2

A1

A1 A1

JUST

MISSED

DET

NO

SIG

FOUND

ANT2

DETECT

ANT1

VERIFY

ANT1

CHECK

ANT2

CHECK

ANT2

SYMB

TIMING

DETECT

ANT1

SFD DET

START DATA

SEED

ANT1

DESCRAMBLER

INTERNAL

SET UP TIME

NOTES:

1. Worst Case Timing; antenna dwell starts before signal is full strength.

2. Time line shown assumes that antenna 2 gets insufficient signal.

FIGURE 15. DUAL ANTENNA ACQUISITION TIMELINE

TX

POWER

RAMP

SFD

78 SYMBOL SYNC

16 SYMBOLS

7 SYM

16 SYMBOLS

2

JUST

MISSED

DET

SYMB

TIMING

DETECT

SFD DET

START DATA

VERIFY

SEED

DESCRAMBLER

INTERNAL

SET UP TIME

FIGURE 16. SINGLE ANTENNA ACQUISITION TIMELINE

20

HSP3824

acquisition decision. This worst case time line example uses a 78 symbol sequence with 2 more for power ramping

assumes that the signal is present on antenna A1 only (A2 is of the RF front of the radio. This scheme deletes the second

blocked). It further assumes that the signal arrives part way antenna dwells but performs the same otherwise. It veriﬁes

into the ﬁrst A1 dwell such as to just barely miss detection. the signal after initial detection for lower false alarm proba-

The signal and the scanning process are asynchronous and bility.

the signal could start anywhere. In this timeline, it is assumed

that all 16 symbols are present, but they were missed due to

Acquisition Signal Quality Parameters

power ampliﬁer ramp up. Since A2 has insufﬁcient signal, the

ﬁrst A2 dwell after the start of the preamble also fails detec-

tion. The second A1 dwell after signal start is successful and a

symbol timing measurement is achieved.

Two measures of signal quality are used to determine acqui-

sition and drop lock decisions. The ﬁrst method of determin-

ing signal presence is to measure the correlator output (or

bit sync) amplitude. This measure, however, ﬂattens out in

the range of high BER and is sensitive to signal amplitude.

The second measure is phase noise and in most BER sce-

narios it is a better indication of good signals plus it is insen-

sitive to signal amplitude. The bit sync amplitude and phase

noise are integrated over each block of 16 symbols used in

acquisition or over blocks of 128 symbols in the data demod-

ulation mode. The bit sync amplitude measurement repre-

sents the peak of the correlation out of the PN correlator.

Figure 17 shows the correlation process. The signal is sam-

Meanwhile signal quality and signal frequency measure-

ments are made simultaneous with symbol timing measure-

ments. When the bit sync level, SQ1, and Phase variance

SQ2 are above their user programmable thresholds, the sig-

nal is declared present for the antenna with the best signal.

More details on the Signal Quality estimates and their pro-

grammability are given in the Acquisition Signal Quality

Parameters section of this document.

At the end of each dwell, a decision is made based on the rel- pled at twice the chip rate (i.e. 22 MSPS). The one sample

ative values of the signal qualities of the signals on the two that falls closest to the peak is used for a bit sync amplitude

antennas. In the example, antenna A1 is the one selected, so sample for each symbol. This sample is called the on-time

the recorded symbol timing and carrier frequency for A1 are sample. High bit sync amplitude means a good signal. The

used thereafter for the symbol timing and the PLL of the NCO early and late samples are the two adjacent samples and

to begin carrier de-rotation and demodulation.

are used for tracking.

Prior to initial acquisition the NCO was inactive and DPSK The other signal quality measurement is based on phase

demodulation processing was used. Carrier phase measure- noise and that is taken by sampling the correlator output at the

ment are done on a symbol by symbol basis afterward and correlator peaks. The phase changes due to scrambling are

coherent DPSK demodulation is in effect. After a brief setup removed by differential demodulation during initial acquisition.

time as illustrated on the timeline of Figure 15, the signal Then the phase, the phase rate and the phase variance are

begins to emerge from the demodulator.

measured and integrated for 16 symbols. The phase variance

is used for the phase noise signal quality measure. Low phase

noise means a stronger received signal.

If the descrambler is used it takes 7 more symbols to seed

the descrambler before valid data is available. This occurs in

time for the SFD to be received. At this time the demodulator Procedure to Set Acq. Signal Quality

is tracking and in the coherent PSK demodulation mode it Parameters (Example)

will no longer scan antennas.

There are four registers that set the acquisition signal quality

One Antenna Acquisition

thresholds, they are: CR 22, 23, 30, and 31

(RX_SQX_IN_ACQ). Each threshold consists of two bytes,

high and low that hold a 16-bit number.

When only one antenna is being used, the user can delete

the antenna switch and shorten the acquisition sequence.

Figure 16 shows the single antenna acquisition timeline. It

SAMPLES

AT 2X CHIP

RATE

CORRELATION

PEAK

CORRELATION TIME

T0

T0 + 1µs

CORRELATOR

OUTPUT

T0 + 2µs

CORRELATOR OUTPUT IS

THE RESULT OF CORRELATING

THE PN SEQUENCE WITH THE

RECEIVED SIGNAL

EARLY

ON-TIME

LATE

REPEATS

FIGURE 17. CORRELATION PROCESS

21

HSP3824

These two thresholds, bit sync amplitude CR (22 and 23)

Data Demodulation and Tracking

Description

and phase error CR (30 and 31) are used to determine if the

desired signal is present. If the thresholds are set too “low”,

there is the probability of missing a high signal to noise

detection due to processing a false alarm. If they are set too

“high”, there is the probability of missing a low signal to noise

detection. For the bit sync amplitude, “high” actually means

high amplitude while for phase noise “high” means high SNR

or low noise.

The signal is demodulated from the correlation peaks

tracked by the symbol timing loop (bit sync). The frequency

and phase of the signal is corrected from the NCO that is

driven by the phase locked loop. Demodulation of the DPSK

data in the early stages of acquisition is done by delay and

subtraction of the phase samples. Once phase locked loop

tracking of the carrier is established, coherent demodulation

is enabled for better performance. Averaging the phase

errors over 16 symbols gives the necessary frequency infor-

mation for proper NCO operation. The signal quality is taken

as the variance in this estimate.

A recommended procedure is to set these thresholds individu-

ally optimizing each one of them to the same false alarm rate

with no desired signal present. Only the background environ-

ment should be present, usually additive gaussian white noise

(AGWN). When programming each threshold, the other

threshold is set so that it always indicates that the signal is

present. Set register CR22 to 00h while trying to determine

the value of the phase error signal quality threshold for regis-

ters CR 30 and 31. Set register CR30 to FFh while trying to

determine the value of the Bit sync. amplitude signal quality

threshold for registers 22 and 23. Monitor the Carrier Sense

(CRS) output (TEST 7, pin 46) and adjust the threshold to pro-

duce the desired rate of false detections. CRS indicates valid

initial PN acquisition. After both thresholds are programmed in

the device the CRS rate is a logic “and” of both signal qualities

rate of occurrence over their respective thresholds and will

therefore be much lower than either.

There are two signal quality measurements that are per-

formed in real time by the device and they set the demodula-

tor performance. The thresholds for these signal quality

measurements are user programmable. The same two sig-

nal quality measures, phase error and bit sync. amplitude,

that are used in acquisition are also used for the data drop

lock decision. The data thresholds, though, are programmed

independently from the acquisition thresholds. If the radio

uses the network processor to determine when to drop the

signal, the thresholds for these decisions should be set to

their limits allowing data demodulation even with poor signal

reception. Under this conﬁguration the HSP3824 data moni-

tor mechanism is essentially bypassed and data monitoring

becomes the responsibility of the network processor.

PN Correlator Description

These signal quality measurements are integrated over 128

symbols as opposed to 16 symbol intervals for acquisition, so

the minimum time to drop lock based with these thresholds is

128 symbols or 128ms at 1 MSPS. Note that other than the

data thresholds, non-detection of the SFD can cause the

HSP3824 to drop lock and return its acquisition mode.

The PN correlator is designed to handle BPSK spreading

with carrier offsets up to ±50ppm and 11,13,15 or 16 chips

per symbol. Since the spreading is BPSK, the correlator is

implemented with two real correlators, one for the I and one

for the Q channel.The same sequence is always used for

both I an Q correlators. The TX sequence can be pro-

grammed as a different sequence from the RX sequence.

This allows a full duplex link with different spreading parame-

ters for each direction.

Conﬁguration Register 41 sets the search timer for the SFD.

This register sets this time-out length in symbols for the

receiver. If the time out is reached, and no SFD is found, the

receiver resets to the acquisition mode. The suggested value

is preamble symbols + 16 symbols. If several transmit pream-

ble lengths are used by various transmitters in a network, the

longest value should be used for the receiver settings.

The correlators are time invariant matched ﬁlters otherwise

known as parallel correlators. They use two samples per

chip. The correlator despreads the samples from the chip

rate back to the original data rate giving 10.4dB processing

gain for 11 chips per bit. While despreading the desired sig-

nal, the correlator spreads the energy of any non correlating

interfering signal.

Procedure to Set Signal Quality Registers

CR 26, 27, 34, AND 35 (RX_SQX_IN_DATA) are pro-

grammed to hold the threshold values that are used to drop

lock if the signal quality drops below their values. These can

be set to their limit values if the external network processor

is used for drop lock decisions instead of the HSP3824

demodulator. The signal quality values are averaged over

128 symbols and if the bit sync amplitude value drops below

its threshold or the phase noise rises over its threshold, the

link is dropped and the receiver returnes to the acquisition

mode. These values should typically be different for BPSK

and QPSK since the operating point in SNR differs by 3dB. If

the receiver is intended to receive both BPSK and QPSK

modulations, a compromise value must be used or the net-

work processor can control them as appropriate.

Based on the fact that correlator output pulse is used for bit

timing, the HSP3824 can not be used for any non spread

applications.

In programming the correlator functions, there are two sets

of conﬁguration registers that are used to program the

spread sequences of the transmitter and the receiver. They

are CR 13 and 14 for transmitter and CR 20 and 21 for the

receiver. In addition, CR2 and CR3 deﬁne the sequence

length or chips per symbol for the receiver and transmitter

respectively. These are carried in bits 6 and 7 of CR2 and

bits 5 and 6 of CR3. More programming details are given in

the Control Registers section of this document.

22

HSP3824

The suggested method of optimization is to set the transmit- Secondly, when the bits are processed by the descrambler,

ter in a continuous transmit mode. Then, measure the time these errors are further extended. The descrambler is a 7-bit

until the receiver drops lock at low signal to noise ratio. Each shift register with one or more taps exclusive ored with the

of the 2 thresholds should be set individually to the same bit stream. If for example the scrambler polynomial uses 2

drop lock time. While setting thresholds for one of the signal taps that are summed with the data, then each error is

qualities the other should be conﬁgured at its limit so it does extended by a factor of three. Since the DPSK errors are

not inﬂuence the drop lock decisions. Set CR 26 to 00h while close together, however, some of them can be canceled in

determining the value of CR 34 and 35 for phase error the descrambler. In this case, two wrongs do make a right,

threshold. Set CR 34 to FFh while determining the value of so the observed errors can be in groups of 4 instead of 6.

CR 26 and 27 for bit sync. amplitude threshold.

Descrambling is done by a polynomial division using a pre-

Assuming a 10e-6 BER operating point, it is suggested that scribed polynomial. A shift register holds the last quotient and

the drop lock thresholds are set at 10e-3 BER, with each the output is the exclusive-or of the data and the sum of taps in

threshold adjusted individually.

the shift register. The taps and seed are programmable. The

transmit scrambler seed is programmed by CR 15 and the taps

are set with CR 16. One reason for setting the seed is that it

can be used to make the SFD scrambling the same every

packet so that it can be recognized in its scrambled state.

Note that the bit sync amplitude is linearly proportional to the

signal amplitude at the ADC converters. If an AGC system is

being used instead of a limiter, the bit sync amplitude thresh-

old should be set at or below the minimum amplitude that the

radio will see at its sensitivity level.

Demodulator Performance

Data Decoder and Descrambler

Description

This section indicates the theoretical performance and typi-

cal performance measures for a radio design. The perfor-

mance data below should be used as a guide. The actual

performance depends on the application, interference envi-

ronment, RF/IF implementation and radio component selec-

tion in general.

The data decoder that implements the desired DQPSK cod-

ing/decoding as shown in DQPSK Data Decoder Table 9.

This coding scheme results from differential coding of the

dibits. When used in the DBPSK modes, only the 00 and 11

dibits are used. Vector rotation is counterclockwise.

Overall Eb/N0 Versus BER Performance

The PRISM chip set has been designed to be robust and

energy efﬁcient in packet mode communications. The

demodulator uses coherent processing for data demodula-

tion. Figure 18 below shows the performance of the base-

band processor when used in conjunction with the HSP3724

IF limiter and the PRISM recommended IF ﬁlters. Off the

shelf test equipment are used for the RF processing. The

curves should be used as a guide to assess performance in

a complete implementation.

TABLE 9. DQPSK DATA DECODER

PHASE SHIFT

DIBITS

00

0

+90

+180

-90

01

11

10

The data scrambler and de-scrambler are self synchronizing

circuits. They consist of a 7-bit shift register with feedback of

some of the taps of the register. The scrambler can be dis-

abled for measuring RF carrier suppression. The scrambler

is designed to insure smearing of the discrete spectrum lines

produced by the PN code.

Factors for carrier phase noise, multipath, and other degra-

dations will need to be considered on an implementation by

implementation basis in order to predict the overall perfor-

mance of each individual system.

Figure 18 shows the curve for theoretical DBPSK/DQPSK

demodulation with coherent demodulation as well as the

PRISM performance measured for DBPSK and DQPSK. The

losses include RF and IF radio losses; they do not reﬂect the

HSP3824 losses alone. These are more realistic measure-

ments. The HSP3824 baseband losses from theoretical by

themselves are a small percentage of the overall loss.

One thing to keep in mind is that both the differential decod-

ing and the descrambling when used cause error extension.

This causes the errors to occur in groups of 4 and 6. This is

due to two properties of the processing. First, the differential

decoding process causes errors to occur in pairs. When a

symbol error is made, it is usually a single bit error even in

QPSK mode. When a symbol is in error, the next symbol will

also be decoded wrong since the data is encoded in the

change from one symbol to the next. Thus, two errors are

made on two successive symbols. In QPSK mode, these

may be next to one another or separated by up to 2 bits.

The PRISM demodulator performs at less than 3dB from the-

oretical in a AWGN environment with low phase noise local

oscillators. The observed errors occurred in groups of 4 and 6

errors and rarely singly. This is because of the error extension

properties of differential decoding and descrambling.

23

HSP3824

Eb/N0 IN dB

FREQUENCY OFFSET (kHz)

1E-01

1E-3

1E-4

1E-5

1E-6

THEORY (DBPSK)

DBPSK

1E-02

1E-03

1E-04

1E-05

1E-06

1E-07

1E-08

1E-09

DQPSK

FIGURE 18. BER vs EB/N0 PERFORMANCE

Clock Offset Tracking Performance

FIGURE 20. BER vs CARRIER OFFSET

I/Q Amplitude Imbalance

The PRISM baseband processor is designed to accept data Imbalances in the signal cause differing effects depending

clock offsets of up to ±25ppm for each end of the link (TX on where they occur. In a system using a limiter, if the imbal-

and RX). This effects both the acquisition and the tracking ances are in the transmitter, that is, before the limiter, ampli-

performance of the demodulator. The budget for clock offset tude imbalances translate into phase imbalances between

error is 0.75dB at ±50ppm as shown in Figure 19.

the I and Q symbols. If they occur in the receiver after the

limiter, they are not converted to phase imbalances in the

symbols, but into vector phase imbalances on the composite

signal plus noise. The following curve shows data taken with

amplitude imbalances in the transmitter. Starting at the bal-

anced condition, I = 100% of Q, the bit error rate degrades

by two orders of magnitude for a 3dB drop in I (70%).

OFFSET IN ppm

-100

1E-3

-60

-20

20

60

100

PERCENT AMPLITUDE BALANCE

1E-01

1E-4

1E-02

1E-03

1E-04

1E-5

FIGURE 19. BER vs CLOCK OFFSET

Carrier Offset Frequency Performance

1E-05

The correlators in the baseband processor are time invariant

matched ﬁlter correlators otherwise known as parallel corre-

lators. They use two samples per chip and are tapped at

every other shift register stage. Their performance with car-

rier frequency offsets is determined by the phase roll rate

due to the offset. For an offset of +50ppm (combined for both

TX and RX) will cause the carrier to phase roll 22.5 degrees

over the length of the correlator. This causes a loss of

0.22dB in correlation magnitude which translates directly to

Eb/N0 performance loss. In the PRISM chip design, the corr-

elator is not included in the carrier phase locked loop correc-

tion, so this loss occurs for both acquisition and data. Figure

20 shows the loss versus carrier offset taken out to +350kHz

(120kHz is 50ppm at 2.4GHz).

FIGURE 21. I/Q IMBALANCE EFFECTS

A Default Register Conﬁguration

The registers in the HSP3824 are addressed with 14-bit num-

bers where the lower 2 bits of a 16-bit hexadecimal address

are left as unused. This results in the addresses being in

increments of 4 as shown in the table below. Table 10 shows

the register values for a default Full Protocol conﬁguration

(Mode 3) with a single antenna. The data is transmitted as

DQPSK. This is a recommended conﬁguration for initial test

and veriﬁcation of the device and /or the radio design. The

user can later modify the CR contents to reﬂect the system

and the required performance of each speciﬁc application.

24

HSP3824

TABLE 10. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION

REG ADDR

REGISTER

CR0

NAME

TYPE

R/W

R

IN HEX

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

64

68

6C

70

74

78

QPSK

3C

00

07

04

00

X

BPSK

64

00

24

07

00

X

MODEM CONFIG. REG A

CR1

MODEM CONFIG. REG B

CR2

MODEM CONFIG. REG C

CR3

MODEM CONFIG. REG D

CR4

INTERNAL TEST REGISTER A

INTERNAL TEST REGISTER B

INTERNAL TEST REGISTER C

MODEM STATUS REGISTER A

MODEM STATUS REGISTER B

I/O DEFINITION REGISTER

RSSI VALUESTATUS REGISTER

ADC_CAL_POS REGISTER

ADC_CAL_NEG REGISTER

TX_SPREAD SEQUENCE(HIGH)

TX_SPREAD SEQUENCE (LOW)

SCRAMBLE_SEED

CR5

CR6

CR7

R

X

CR8

R

X

CR9

R/W

R

00

X

00

X

CR10

CR11

CR12

CR13

CR14

CR15

CR16

CR17

CR18

CR19

CR20

CR21

CR22

CR23

CR24

CR25

CR26

CR27

CR28

CR29

CR30

R/W

R

01

FD

05

B8

7F

48

2C

03

1E

05

B8

01

E8

X

01

FD

05

B8

7F

48

2C

03

1E

05

B8

01

E8

X

SCRAMBLE_TAP (RX AND TX)

CCA_TIMER_TH

CCA_CYCLE_TH

RSSI_TH

RX_SPREAD SEQUENCE (HIGH)

RX_SREAD SEQUENCE (LOW)

RX_SQ1_ IN_ACQ (HIGH) THRESHOLD

RX-SQ1_ IN_ACQ (LOW) THRESHOLD

RX-SQ1_ OUT_ACQ (HIGH) READ

RX-SQ1_ OUT_ACQ (LOW) READ

RX-SQ1_ IN_DATA (HIGH) THRESHOLD

RX-SQ1-SQ1_ IN_DATA (LOW) THRESHOLD

RX-SQ1_ OUT_DATA (HIGH)READ

RX-SQ1_ OUT_DATA (LOW) READ

RX-SQ2_ IN_ACQ (HIGH) THRESHOLD

R

X

R/W

R

0F

FF

X

0F

FF

X

R

X

R/W

00

25

HSP3824

TABLE 10. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION (Continued)

REG ADDR

REGISTER

CR31

CR32

CR33

CR34

CR35

CR36

CR37

CR38

CR39

CR40

CR41

CR42

CR43

CR44

CR45

CR46

CR47

CR48

CR49

CR50

CR51

CR52

CR53

CR54

CR55

CR56

NAME

RX-SQ2- IN-ACQ (LOW) THRESHOLD

RX-SQ2_ OUT_ACQ (HIGH) READ

RX-SQ2_ OUT_ACQ (LOW) READ

RX-SQ2_IN_DATA (HIGH)THRESHOLD

RX-SQ2_ IN_DATA (LOW) THRESHOLD

RX-SQ2_ OUT_DATA (HIGH) READ

RX-SQ2_ OUT_DATA (LOW) READ

RX_SQ_READ; FULL PROTOCOL

RESERVED

TYPE

R/W

R

IN HEX

7C

80

QPSK

CA

X

BPSK

CA

X

R

84

X

R/W

R

88

09

80

X

09

80

X

8C

90

R

94

X

R

98

X

W

9C

A0

A4

A8

AC

B0

B4

B8

BC

C0

C4

C8

CC

D0

D4

D8

DC

E0

00

90

0A

14

X

00

90

0A

14

X

RESERVED

W

UW_Time Out_LENGTH

SIG_DBPSK Field

R/W

R

SIG_DQPSK Field

RX_SER_Field

RX_LEN Field (HIGH)

RX_LEN Field (LOW)

RX_CRC16 (HIGH)

R

X

R

X

R

X

RX_CRC16 (LOW)

R

X

UW -(HIGH)

R/W

R

F3

A0

00

FF

X

F3

A0

00

FF

X

UW _(LOW)

TX_SER_F

TX_LEN (HIGH)

TX_LEN(LOW)

TX_CRC16 (HIGH)

TX_CRC16 (LOW)

R

X

TX_PREM_LEN

R/W

80

26

HSP3824

Control Registers

The following tables describe the function of each control register along with the associated bits in each control register.

CONFIGURATION REGISTER 0 ADDRESS (0h) MODEM CONFIGURATION REGISTER A

Bit 7

Bit 6

Bit 5

This bit selects the transmit antenna, controlling the output ANT_SEL pin. It is only used in half duplex mode. (Bit 5 = 0)

Logic 1 = Antenna A.

Logic 0 = Antenna B.

In single antenna operation this bit is used as the output of the ANT_SEL pin. In dual antenna mode this bit is ignored.

Logic 1 = Antenna A.

Logic 0 = Antenna B.

This control bit is used to select between full duplex and half duplex operation. If set for full duplex operation, the

ANT_SEL pin reflects the setting of CR0 bit 7 when TX_PE is active and reflects the receiver’s choice when TX_PE is

inactive. In full duplex operation, the ANT_SEL pin always reflects the receiver’s choice antenna.

Logic 1 = full duplex.

Logic 0 = half duplex.

Bit 4, 3

These control bits are used to select one of the four input Preamble Header modes for transmitting data. The preamble

and header are DBPSK for all modes of operation. Mode 0 is followed by DBPSK data. For modes 1-3, the data can

be configured as either DBPSK or DQPSK. This is a “don’t care” if the header is generated externally.

MODE

BIT 4

BIT 3

MODE DESCRIPTION

Preamble with SFD Field.

0

1

2

3

0

1

0

1

0

1

Preamble with SFD, and CRC16.

Preamble with SFD, Length, and CRC16.

Full preamble and header.

Bit 2

Bit 1

This control bit is used to enable the SFD (Start Frame Delimiter) timer. If the time is set and expires before the SFD

has been detected, the HSP3824 will return to its acquisition mode.

Logic 1: Enables the SFD timer to start counting once the PN acquisition has been achieved.

Logic 0: Disables the SFD Timer.

This control bit enables counting the number of data bits per the length field embedded in the header. Only used in

header modes 2 and 3. Then according to the count it returns the processor into its acquisition mode at the end of the

count. If length field is 0000h, modem will reset at end of SFD regardless of this bit setting.

Logic 1 = Enable Length Time Out.

Logic 0 = Disabled.

Bit 0

Unused don’t care.

CONFIGURATION REGISTER 1 ADDRESS (04h) MODEM CONFIGURATION REGISTER B

Bit 7

When active this bit maintains the RXCLK and TXLK rates constant for preamble and data transfers even if the data

is modulated in DQPSK. This bit is used if the external processor can not accommodate rate changes. This is an active

high signal. The rate used is the QPSK rate and the BPSK header bits are double clocked.

Bit 6, 5, 4, 3, 2

These control bits are used to define a binary count (N) from 0 - 31. This count is used to assert TX_RDY N - clocks

(TXCLK) before the beginning of the first data bit. If this is set to zero, then the TX_RDY will be asserted immediately

after the last bit of the Preamble Header.

Bit 1

When active the internal A/D calibration circuit sets the reference to mid-scale. When inactive then the calibration cir-

cuit adjusts the reference voltage in real time to optimize I, Q levels.

Logic 1 = Reference set at mid-scale (fixed).

Logic 0 = Real time reference adjustment.

Bit 0

When active the A/D calibration circuit is held at its last value.

Logic 1 = Reference held at the most recent value.

Logic 0 = Real time reference level adjustment.

27

HSP3824

CONFIGURATION REGISTER 2 ADDRESS (08h) MODEM CONFIGURATION REGISTER C

Bit 7, 6

These control bits are used to select the number of chips per symbol used in the I and Q paths of the receiver matched

filter correlators (see table below).

CHIPS PER SYMBOL

BIT 7

BIT 6

11

13

15

16

0

1

0

1

0

1

Bit 5

This control bit is used to disable the CRC16 check. When this bit is set, the processor will accept the received packet

and any packet error checks have to be detected externally. The HSP3824 will remain in the receive mode until either

the carrier is lost or the network processor resets the device to the acquisition mode, or if, in modes 2 or 3, the length

times out.

Logic 1 = Disable receiver error checks.

Logic 0 = Enable receiver checks.

Bit 4, 3

These control bits are used to select the divide ratio for the demodulators receive chip clock timing.The value of N is

determined by the following equation:

Symbol Rate = MCLK/(N x Chips per symbol).

MASTER CLOCK/N

BIT 4

BIT 3

N = 2

N = 4

N = 8

N = 16

0

1

0

1

0

1

Bit 2

This control bit sets the receiver into single or dual antenna mode. The Preamble acquisition processing length and

whether the modem scans antennas is controlled by this bit. If in single antenna mode, the ANT_SEL pin reflects CR0

bit 6 otherwise it reflects the receiver’s choice of antenna.

Logic 0 = Acquisition processing is for dual antenna acquisition.

Logic 1 = Acquisition processing is for single antenna acquisition.

Bit 1, 0

These control bits are used to indicate one of the four Preamble Header modes for receiving data. Each of the modes

includes different combinations of Header fields. Users can choose the mode with the fields that are more appropriate

for their networking requirements. The Header fields that are combined to form the various modes are:

• SFD ﬁeld

• CRC16 ﬁeld

• Data length ﬁeld (indicates the number of data bits that follow the Header information)

• Full protocol Header

INPUT MODE

BIT 1

BIT 0

RECEIVE PREAMBLE - HEADER FIELDS

Preamble, with SFD Field

0

1

2

3

0

1

0

1

0

1

Preamble, with SFD, CRC16

Preamble, with SFD Length, CRC16

Preamble, with Full Protocol Header

CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D

Bit 7

Reserved (must set to “0”).

28

HSP3824

CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D (Continued)

Bit 6, 5

These control bits combined are used to select the number of chips per symbol used in the I and Q transmit paths (see

table below).

CHIPS PER

BIT 6

BIT 5

11

13

15

16

0

1

0

1

0

1

Bit 4, 3

These control bits are used to select the divide ratio for the transmit chip clock timing.

NOTE: The value of N is determined by the following equation: Symbol Rate = MCLK/(N x Chips per symbol)

MASTER

N = 2

BIT 4

BIT 3

0

1

0

1

0

1

N = 4

N = 8

N = 16

Bit 2

Bit 1

Bit 0

This control bit is used to select the origination of Preamble/Header information.

Logic 1: The HSP3824 generates the Preamble and Header internally by formatting the programmed header

information and generating a TX_RDY to indicate the beginning of the data packet.

Logic 0: Accepts the Preamble/Header information from an externally generated source.

This control bit is used to indicate the signal modulation type for the transmitted data packet. When configured for mode

0 header, or mode 3 and external header, this bit is ignored. See Register 0 bits 4 and 3.

Logic 1 = DBPSK modulation for data packet.

Logic 0 = DQPSK modulation for data packet.

This control bit is used to indicate the signal modulation type for the received data packet Used only with header modes

1 and 2. See register 2 bits 1 and 0.

Logic 1 = DBPSK.

Logic 0 = DQPSK.

CONFIGURATION REGISTER 4 ADDRESS (10h) INTERNAL TEST REGISTER A

Bit 7 - 0

These control bits are used to direct various internal signals to test port output pins. These internal signals are moni-

tored to fault isolate the device at manufacturing testing. During normal operation, the value 0h is recommended. This

will result to the following signals becoming available at the output test pins of the device:

Pin 46 (TEST7): Carrier Sense (CRS), a Logic 1 indicates PN lock.

Pin 45 (TEST6): Energy Detect (ED), a Logic 1 indicates that there is energy detected in the channel. The ED goes

active when the RSSI exceeds the threshold level programmed by the user.

Pin 1 (TEST_CK): PN clock.

CONFIGURATION REGISTER 5 ADDRESS (14h,18h) INTERNAL TEST REGISTER B

Bits 7 - 0

Bit 7

These bits need to be programmed to 0h. They are used for manufacturing test only.

CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A

This bit indicates the status of the TX_RDY output pin. TX_RDY is used only when the HSP3824 generates the Pre-

amble/Header data internally.

Logic 1: Indicates that the HSP3824 has completed transmitting Preamble header information and is ready to accept

data from the external source (i.e. MAC) to transmit.

Logic 0: Indicates that the HSP3824 is in the process of transmitting Preamble Header information.

Bit 6

This status bit indicates the antenna selected by the device.

Logic 0: Antenna A is selected.

Logic 1: Antenna B is selected.

29

HSP3824

CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A (Continued)

Bit 5

Bit 4

Bit 3

This status bit indicates the present state of clear channel assessment (CCA) which is output pin 32. The CCA is being

asserted as a result of a channel energy monitoring algorithm that is a function of RSSI, carrier sense, and time out

counters that monitor the channel activity.

This status bit, when active indicates Carrier Sense, or PN lock.

Logic 1: Carrier present.

Logic 0: No Carrier Sense.

This status bit indicates whether the RSSI signal is above or below the programmed RSSI 6-bit threshold setting. This

signal is referred as Energy Detect (ED).

Logic 1: RSSI is above the programmed threshold setting.

Logic 0: RSSI is below the programmed threshold setting.

Bit 2

Bit 1

Bit 0

This bit indicates the status of the output control pin MD_RDY (pin 34). It signals that a valid Preamble/Header has

been received and that the next available bit on the TXD bus will be the first data packet bit.

Logic 1: Envelopes the data packet as it becomes available on pin 3 (TXD).

Logic 0: No data packet on TXD serial bus.

This status bit indicates whether the external device has acknowledged that the channel is clear for transmission. This

is the same as the input signal TX_PE on pin 2.

Logic 1 = Acknowledgment that channel is clear to transmit.

Logic 0 = Channel is NOT clear to transmit.

This status bit indicates that a valid CRC16 has been calculated. The CRC16 is calculated on the Header information.

The CRC16 does not cover the preamble bits.

Logic 1 = Valid CRC16 check.

Logic 0 = Invalid CRC16 check.

CONFIGURATION REGISTER 8 ADDRESS (20h) MODEM STATUS REGISTER B

Bit 7

Bit 6

This status bit is meaningful only when the device operates under the full protocol mode. Errors imply CRC errors of

the header fields.

Logic 0 = Valid packet received.

Logic 1 = Errors in received packet.

This bit is used to indicate the status of the SFD search timer. The device monitors the incoming Header for the SFD.

If the timer, times out the HSP3824 returns to its signal acquisition mode looking to detect the next Preamble and

Header.

Logic 1 = SFD not found, return to signal acquisition mode.

Logic 0 = No time out during SFD search.

Bit 5

This status bit is used to indicate the modulation type for the data packet. This signal is generated by the header de-

tection circuitry in the receive interface.

Logic 0 = DBPSK.

Logic 1 = DQPSK.

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused, don’t care.

CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER

This register is used to define the phase of clocks and other interface signals.

Bit 7

Bit 6

This bit needs to always be set to logic 0.

This control bit selects the active level of the MD_RDY output pin 34.

Logic 1 = MD_RDY is active 0.

Logic 0 = MD_RDY is active 1.

30

HSP3824

CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER

Bit 5

Bit 4

Bit 3

This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.

Logic 1 = CCA active 1.

Logic 0 = CCA active 0.

This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 45.

Logic 1 = ED active 0.

Logic 0 = ED active 1.

This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin

46.

Logic 1 = CRS active 0.

Logic 0 = CRS active 1.

Bit 2

Bit 1

Bit 0

This control bit selects the active level of the transmit ready (TX_RDY) output pin 5.

Logic 1 = TX_RDY active 0.

Logic 0 = TX_RDY active 1.

This control bit selects the active level of the transmit enable (TX_PE) input pin 2.

Logic 1 = TX_PE active 0.

Logic 0 = TX_PE active 1.

This control bit selects the phase of the transmit output clock (TXCLK) pin 4.

Logic 1 = Inverted TXCLK.

Logic 0 = NON-Inverted TXCLK

CONFIGURATION REGISTER 10 ADDRESS (28h) RSSI VALUE REGISTER

Bits 0 - 7

This is a read only register reporting the value of the RSSI analog input signal from the on chip 6-bit ADC. This register

is updated at (chip rate/11). Bits 7 and 6 are not used and set to Logic 0.

Example:

BITS (0:7)

RANGE

RSSI_STAT

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1

00h (Min)

3Fh (Max)

CONFIGURATION REGISTER 11 ADDRESS (2ch) A/D CAL POS REGISTER

Bits 0 - 7

This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D

reference. The larger the step the faster the level reaches saturation.

CONFIGURATION REGISTER 12 ADDRESS (30h) A/D CAL NEG REGISTER

This 8-bit control register contains a binary value used for the negative increment for the level adjusting reference of

the A/D. The number is programmed as 256 - the value wanted since it is a negative number.

CONFIGURATION REGISTER 13 ADDRESS (34h) TX SPREAD SEQUENCE (HIGH)

This 8-bit register is programmed with the upper byte of the transmit spreading code. This code is used for both the I

and Q signalling paths of the transmitter. This register combined with the lower byte TX_SPREAD(LOW) generates a

transmit spreading code programmable up to 16 bits. Code lengths permitted are 11, 13, 15, and 16. Right justified

MSB first.

31

HSP3824

CONFIGURATION REGISTER 14 ADDRESS (38h) TX SPREAD SEQUENCE (LOW)

Bits 0 - 7

This 8-bit register is programmed with the lower byte of the transmit spreading code. This code is used for the I and Q

signalling paths of the transmitter. This register combined with the higher byte TX_SPREAD(HIGH) generates the

transmit spreading code programmable up to 16 bits.

The example below illustrates the bit positioning for one of the 11 bit Barker PN codes.

Example:

Transmit Spreading Code 11-Bit Barker Word Right Justified MSB First.

MSB

LSB

TX_SPREAD(HIGH)

TX_SPREAD(LOW)

11-bit Barker code

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

X

1 0 1 1 0 1 1 1 0 0 0

CONFIGURATION REGISTER 15 ADDRESS (3Ch) SCRAMBLER SEED

Bits 0 - 7

This register contains the 7-bit (seed) value for the transmit scrambler which is used to preset the transmit scrambler

to a known starting state. The MSB bit position (7) is unused and must be programmed to a Logic 0. The example

below illustrates the bit positioning of seed.

CONFIGURATION REGISTER 16 ADDRESS (40h) SCRAMBLER TAP

This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scram-

bler is a 7-bit shift register, with 7 configurable taps. A logic 1 is the respective bit position enables that particular tap.

The MSB bit 7 is not used and it is set to a Logic 0. The example below illustrates the register configuration for the

-4

-7

polynomial F(x) = 1 + X +X . Each clock is a shift left

LSB

Bits (0:7)

7 6 5 4 3 2 1 0

-7 -6 -5 −4 -3 -2 -1

XZ Z Z Z Z Z Z

0 1 0 0 1 0 0 0

-4

-7

Scrambler Taps

F(x) = 1 + X +X

CONFIGURATION REGISTER 17 ADDRESS (44h)CCA TIMER THRESHOLD

Bits 0 - 7

This 8-bit register is used to configure the period of the time-out threshold of the CCA watchdog timer. If the channel

is busy the timer counts until it reaches the programmed value and at that point it declares that the channel is clear

independent of the actual energy measured within the channel. This register is programmable up to 8 bits.

N • 5632

Chip Rate

--------------------------

Time (ms) = 1000 •

, where N is the programmable value of CR17.

For example, for a chip rate of 11 MCPS and a desired timeout of ~11ms, N = 2ch.

LSB

Bits (0:7)

7 6 5 4 3 2 1 0

0 0 0 0 0 0 1 0

1 1 1 1 1 1 1 1

02h (Min)

FFh (Max)

CCA_TIMER_TH

CONFIGURATION REGISTER 18 ADDRESS (48h) CCA CYCLE THRESHOLD

Bits 0 - 7

This 8-bit register is used to configure how many times the CCA timer is allowed to reach its maximum count before

the channel is declared clear for transmission independent of the actual energy in the channel. This is an outer counter

loop of the CCA timer. Each increment represents a time out of the CCA timer. Use a value of 03h for a time out of 2

CCA timer counts.

MSB

LSB

Bits (0:7)

7 6 5 4 3 2 1 0

0 0 0 0 0 0 1 0

1 1 1 1 1 1 1 1

2h; 1 CCA timer (Min)

CCA_TIMER_TH

FFh; 256 CCA timer (Max)

32

HSP3824

CONFIGURATION REGISTER 19 ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT

Bits 0 - 7

This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the

RSSI exceeds the threshold ED is declared. ED indicates the presence of energy in the channel. The threshold that

activates ED is programmable. Bits 7 an 6 of this register are not used and set to Logic 0.

MSB

LSB

Bits (0:7)

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1

00h (Min)

3Fh (Max)

RSSI_STAT

CONFIGURATION REGISTER 20 ADDRESS (50h) RX SPREAD SEQUENCE (HIGH)

Bits 0 - 7

This 8-bit register is programmed with the upper byte of the receive despreading code. This code is used for both the

I and Q signalling paths of the receiver. This register combined with the lower byte RX_SPRED(LOW) generates a

receive despreading code programmable up to 16 bits. Right justified MSB first. See address 13 and 14 for example.

CONFIGURATION REGISTER 21 ADDRESS (54h) RX SPREAD SEQUENCE (LOW)

This 8-bit register is programmed with the lower byte of the receiver despreading code. This code is used for both the

I and Q signalling paths of the receiver. This register combined with the upper byte RX_SPRED(HIGH) generates a

receive despreading code programmable up to 16 bits.

CONFIGURATION REGISTER 22 ADDRESS (58h) RX SIGNAL QUALITY 1 ACQ (HIGH) THRESHOLD

This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for

acquisition. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude

signal quality measurements made during acquisition at each antenna dwell. This threshold comparison is added with

the SQ2 threshold in registers 30 and 31 for acquisition. A lower value on this threshold will increase the probability of

detection and the probability of false alarm. Set the threshold according to instructions in the text.

CONFIGURATION REGISTER 23 ADDRESS (5Ch) RX SIGNAL QUALITY 1 ACQ THRESHOLD (LOW)

Bits 0 - 7

This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for ac-

quisition. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude sig-

nal quality measurement made during acquisition at each antenna dwell.

CONFIGURATION REGISTER 24 ADDRESS (60h) RX SIGNAL QUALITY 1 ACQ READ (HIGH)

This status register contains the upper byte bits (8 - 14) of the measured signal quality threshold for the bit sync am-

plitude used for acquisition. This register combined with the lower byte represents a 15-bit value, representing the mea-

sured bit sync amplitude. This measurement is made at each antenna dwell and is the result of the best antenna.

CONFIGURATION REGISTER 25 ADDRESS (64h) RX SIGNAL QUALITY 1 ACQ READ (LOW)

This register contains the lower byte bits (0 - 7) of the measured signal quality threshold for the bit sync amplitude used

for acquisition. This register combined with the higher byte represents a 15-bit value, of the measured bit sync ampli-

tude. This measurement is made at each antenna dwell and is the result of the best antenna.

CONFIGURATION REGISTER 26 ADDRESS (68h) RX SIGNAL QUALITY 1 DATA THRESHOLD (HIGH)

This control register contains the upper byte bits (8-14) of the bit sync amplitude signal quality threshold used for drop

lock decisions. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude

signal quality measurements, made every 128 symbols. These thresholds set the drop lock probability. A higher value

will increase the probability of dropping lock.

CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX SIGNAL QUALITY 1 DATA THRESHOLD (LOW)

Bits 0 - 7

This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for drop

lock decisions. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude

signal quality measurements, made every 128 symbols.

33

HSP3824

CONFIGURATION REGISTER 28 ADDRESS (70h) RX SIGNAL QUALITY 1 DATA (high) THRESHOLD READ (HIGH)

Bits 0 - 7

This status register contains the upper byte bits (8-14) of the measured signal quality of bit sync amplitude used for

drop lock decisions. This register combined with the lower byte represents a 15-bit value, representing the measured

signal quality for the bit sync amplitude. This measurement is made every 128 symbols.

CONFIGURATION REGISTER 29 ADDRESS (74h) RX SIGNAL QUALITY 1 DATA THRESHOLD READ (LOW)

Bits 0 - 7

This register contains the lower byte bits (0-7) of the measured signal quality of bit sync amplitude used for drop lock

decisions. This register combined with the lower byte represents a 16-bit value, representing the measured signal qual-

ity for the bit sync amplitude. This measurement is made every 128 symbols.

CONFIGURATION REGISTER 30 ADDRESS (78h) RX SIGNAL QUALITY 2 ACQ THRESHOLD (HIGH)

This control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition.

This register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement

made during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used

with the bit sync threshold in registers 22 and 23 to declare acquisition. A higher value in this threshold will increase

the probability of acquisition and false alarm.

CONFIGURATION REGISTER 31 ADDRESS (7Ch) RX SIGNAL QUALITY 2 ACQ THRESHOLD (LOW)

Bits 0 - 7

This control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition.

CONFIGURATION REGISTER 32 ADDRESS (80h) RX SIGNAL QUALITY 2 ACQ READ (HIGH)

This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance

used for acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured

signal quality of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and

is based on the selected best antenna.

CONFIGURATION REGISTER 33 ADDRESS (84h) RX SIGNAL QUALITY 2 ACQ READ (LOW)

Bits 0 - 7

This status register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance used

for acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured signal

quality of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and is based

on the selected best antenna

CONFIGURATION REGISTER 34 ADDRESS (88h) RX SIGNAL QUALITY 2 DATA THRESHOLD (HIGH)

Bits 0-7

Bits 0 - 7

This control register contains the upper byte bits (8-15) of the carrier phase variance threshold. This register combined

with the lower byte represents a 16-bit threshold value for the carrier phase variance signal quality measurements

made every 128 symbols.

CONFIGURATION REGISTER 35 ADDRESS (8Ch) RX SIGNAL QUALITY 2 DATA THRESHOLD (LOW)

This control register contains the lower byte bits (0-7) of the carrier phase variance threshold. This register combined

with the upper byte) represents a 16-bit threshold value for the carrier phase variance signal quality measurements

made every 128 symbols.

CONFIGURATION REGISTER 36 ADDRESS (90h) RX SIGNAL QUALITY 2 DATA READ (HIGH)

This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance.

This register combined with the lower byte represents a 16-bit value, of the measured carrier phase variance. This

measurement is made every 128 symbols.

CONFIGURATION REGISTER 37 ADDRESS (94h) RX SIGNAL QUALITY 2 DATA READ (LOW)

This register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance. This register

combined with the represents a 16-bit value, of the measured carrier phase variance. This measurement is made every

128 symbols.

CONFIGURATION REGISTER ADDRESS 38 (98h) RX SIGNAL QUALITY 8-BIT READ

This 8-bit register contains the bit sync amplitude signal quality measurement derived from the 16-bit Bit Sync signal

quality value stored in the CR28-29 registers. This value is the result of the signal quality measurement for the best

antenna dwell. The signal quality measurement provides 256 levels of signal to noise measurement.

34

HSP3824

CONFIGURATION REGISTER 39 ADDRESS RESERVED

Reserved

CONFIGURATION REGISTER 40 ADDRESS RESERVED

CONFIGURATION REGISTER 41 ADDRESS (A4h) SFD SEARCH TIME

Bits 0 - 7

This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for

a SFD in a receive Header. Each bit increment represents 1 symbol period.

CONFIGURATION REGISTER 42 ADDRESS (A8h) DSBPSK SIGNAL

This register contains an 8-bit value indicating the data packet modulation is DBPSK. This value will be a OAH for full

protocol operation at a data rate of 1 MBPS, and is used in the transmitted Signalling Field of the header. This value

will also be used for detecting the modulation type on the received Header.

CONFIGURATION REGISTER 43 ADDRESS (ACh) DQPSK SIGNAL

Bits 0 - 7

This register contains the 8-bit value indicating the data packet modulation is DQPSK. This value will be a 14h for full

protocol operation at a data rate of 2 MBPS and is used in the transmitted Signalling Field of the header. This value

will also be used for detecting the modulation type on the received header.

CONFIGURATION REGISTER 44 ADDRESS (B0h) RX SERVICE FIELD (RESERVED)

Bits 0 - 7

This register contains the detected received 8-bit value of the Service Field for the Header. This field is reserved for

the full protocol mode for future use and should be always a 00h.

CONFIGURATION REGISTER 45 ADDRESS (B4h) RX DATA LENGTH (HIGH)

This register contains the detected higher byte (bits 8-15) of the received Length Field contained in the Header. This

byte combined with the lower byte indicates the number of transmitted bits in the data packet.

CONFIGURATION REGISTER 46 ADDRESS (B8h) RX DATA LENGTH (LOW)

This register contains the detected lower byte of the received Length Field contained in the Header. This byte com-

bined with the upper byte indicates the number of transmitted bits in the data packet.

CONFIGURATION REGISTER 47 ADDRESS (BCh) RX CRC16 (HIGH)

Bits 0 - 7

This register contains the upper byte bits (8 -15) of the received CRC16 field Header. This register combined with the

lower byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con-

figuring the header control bits at configuration register 2.

CONFIGURATION REGISTER 48 ADDRESS (C0h) RX CRC16 (LOW)

This register contains the lower byte bits (0-7) of the received CRC16 field Header. This register combined with the

upper byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con-

figuring the header control bits at configuration register 2.

MSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

2 1 0

LSB

RX_CRC16

RX_CRC16(HIGH)

RX_CRC16(LOW)

7 6 5 4 3

7 6 5 4 3 2 1 0

NOTE: The receive CRC16 Field protects the following ﬁelds depending

upon the mode selection, as deﬁned in configuration register 2.

Mode 0 CRC16 not used

Mode 1 CRC16 protects SFD

Mode 2 CRC16 protects SFD, and Length Field

Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field

35

HSP3824

CONFIGURATION REGISTER 49 ADDRESS (C4h) SFD (HIGH)

Bits 0 - 7

This 8-bit register contains the upper byte bits (8-15) of the SFD used for both the Transmit and Receive header. This

register combined with the lower byte represents the 16-bit value for the SFD field.

CONFIGURATION REGISTER 50 ADDRESS (C8h) SFD (LOW)

This 8-bit register contains the upper byte bits (0-7) of the SFD used for both the Transmit and Receive header. This

register combined with the lower byte represents the 16-bit value for the SFD field.

CONFIGURATION REGISTER 51 ADDRESS (CCh) TX SERVICE FIELD

This 8-bit register is programmed with the 8-bit value of the Service Field to be transmitted in a Header. This field is

reserved for future use and should be always a 00h.

CONFIGURATION REGISTER 52 ADDRESS (D0h) TX DATA LENGTH FIELD (HIGH)

This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte

combined with the lower byte indicates the number of bits to be transmitted in the data packet. CR 52/53 should not

be set to 0000h. This value would cause the modem to reset after SFD.

CONFIGURATION REGISTER 53 ADDRESS (D4h) TX DATA LENGTH FIELD (LOW)

Bits 0 - 7

This 8-bit register contains the lower byte bits (0-7) of the transmit Length Field described in the Header. This byte

combined with the higher byte indicates the number of bits to be transmitted in the data packet, including the MAC

payload header. CR 52/53 should not be set to 0000h. This value would cause the modem to reset after SFD.

CONFIGURATION REGISTER 54 ADDRESS (D8h) TX CRC16 (HIGH)

This 8-bit register contains the upper byte (bits 8-15) of the transmitted CRC16 Field for the Header. This register

combined with the lower byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted

header. The fields protected are selected by configuring the header mode control bits at register address 02.

CONFIGURATION REGISTER 55 ADDRESS (DCh) TX CRC16 (LOW)

This 8-bit register contains the lower byte (bits 0-7) of the transmitted CRC16 Field for the Header. This register com-

bined with the higher byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted

header. The fields protected are selected by configuring the header mode control bits at register address 02.

configuration register 2

MSB

LSB

RX_CRC16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

RX_CRC16(HIGH)

RX_CRC16(LOW)

7 6 5 4 3 2 1 0

NOTE: The receive CRC16 Field protects the following ﬁelds depending

upon the mode selection. as deﬁned in register address 02.

Mode 0 CRC16 not used

Mode 1 CRC16 protects SFD

Mode 2 CRC16 protects SFD, and Length Field

Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field

CONFIGURATION REGISTER 56 ADDRESS (E0h) TX PREAMBLE LENGTH

Bits 0 - 7

This register contains the count for the Preamble length counter. This counter is programmable up to 8 bits and rep-

resents the number of preamble bits. This should be set at 50h for 1 antenna and 80h for dual antennas.

36

Speciﬁcations HSP3824 at 33MHz

Absolute Maximum Ratings

Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0V Thermal Resistance (Typical)

θ

JA

80 C/W

ο

Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V +0.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C

Lead Temperature (Soldering 10s) (Lead Tips Only) . . . . . . +300 C

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Power Dissipation at 85 C

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.81W

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25,000 Gates

CC

o

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

o

Operating Voltage Range . . . . . . . . . . . . . . . . . . . +2.70V to +5.50V

Operating Temperature Range . . . . . . . . . . . . . . . . .-40 C to +85 C

o

DC Electrical Speciﬁcations

V

= 3.0V to 5.0V ±10%, T = -40 to +85 C

CC

A

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply Current

I

V

= Max, CLK Frequency 22MHz

CC

-

69

77

mA

CCOP

(Notes 1, 2)

Standby Power Supply Current

Input Leakage Current

I

V

= Max, Outputs Not Loaded

-

1

2.5

10

-

mA

µA

V

CCSB

CC

I

= Max, Input = 0V or V

-10

I

CC

Output Leakage Current

Logical One Input Voltage

Logical Zero Input Voltage

Logical One Output Voltage

Logical Zero Output Voltage

Input Capacitance

I

= Max, Input = 0V or V

= Max, Min

O

V

0.7 V

-

IH

CC

V

= Min, Max

V

/3

V

IL

CC

V

I

= -1mA, V = Min

V

-0.4

V

-.2

-

V

OH

OL

CC

V

= 2mA, V = Min

-

.2

0.4

10

V

OL

CC

C

CLK Frequency 1MHz

All measurements referenced to GND.

-

5

pF

IN

Output Capacitance

C

OUT

o

T = +25 C, Note 2

A

NOTES:

1. Output load 30pF. I

= 5.5 + 4.7(V) + 3.7E - 7 (V)(f); V = Volts, f = Freq. Example: 5.5 + 4.7(5.5) + 3.7E - 7(5.5)(22E6) = 77

CCOP

2. Not tested, but characterized at initial design and at major process/design changes.

o

AC Electrical Speciﬁcations

V

= 3.0V to 5.0V ±10%, T = -40 to +85 , (Note 1)

CC A

33MHz

PARAMETER

CLK Period (MCLK)

SYMBOL

MIN

30

9

MAX

UNITS

t

-

ns

CP

CH

CLK High (MCLK)

t

ns

CLK Low (MCLK)

t

9

-

ns

CL

Setup Time to MCLK (TXD)

Hold Time from MCLK (TXD)

SCLK Clock Period

t

10

20

-

ns

S2

H2

t

-

ns

t

100ns or MCLK

-

ns

P

H

SCLK High

t

20

-

ns

SCLK Low

t

-

ns

L

Set up to SCLK (SD, AS, R/W, CS)

t

-

ns

S1

H1

D1

Hold Time from SCLK (SD, AS, R/W, CS)

SD from SCLK

t

-

ns

30

20

35

40

-

ns

OUT

Output Enable of Sd from R/W High

Output disable of SD after R/W Low

TXCLK, TXRDY, I, Q from MCLK

RXCLK, MD_RDY, RXD from MCLK

TEST 0-7, CCA, AGC, from MCLK

ANSTEL, TEST_CK

t

-

ns (Note 2)

E1

t

-

ns (Note2)

F1

D2

D3

t

-

ns

-

ns

-

ns

D4

-

OUTPUT Rise/Fall

-

10

ns (Note 2, 3)

NOTES:

1. AC tests performed with C = 40pF, I = 2mA, and I = -1mA. Input reference level all inputs 1.5V. Test V = V , V = 0V; V = V

L

OL

OH

IH

CC IL

OH

OL

= V /2.

CC

2. Not tested, but characterized at initial design and at major process/design changes.

3. Measured from V to V

.

IH

IL

37

Speciﬁcations HSP3824

I and Q A/D AC Electrical Speciﬁcations

PARAMETER

MIN

TYP

MAX

UNITS

V

Full Scale Input Voltage (V

Input Bandwidth (-0.5dB)

Input Capacitance

)

0.25

0.50

1.0

P-P

-

20

5

-

MHz

pF

Input Impedance (DC)

FS (Sampling Frequency)

5

-

kΩ

-

44

MHz

RSSI A/D Electrical Speciﬁcations

PARAMETER

MIN

TYP

MAX

UNITS

V

Full Scale Input Voltage (V

Input Bandwidth (0.5dB)

Input Capacitance (DC)

Input Impedance

)

-

1MHz

-

1.15

P-P

-

7pF

-

MHz

pF

1M

MΩ

38

Speciﬁcations HSP3824 at 44MHz

Absolute Maximum Ratings

Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0V Thermal Resistance (Typical)

θ

JA

80 C/W

o

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to V +0.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C

Lead Temperature (Soldering 10s) (Lead Tips Only) . . . . . . +300 C

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Power Dissipation at 85 C

TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.81W

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25,000 Gates

CC

o

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

o

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.3V to +5.0V

Operating Temperature Range . . . . . . . . . . . . . . . . .-40 C to +85 C

o

DC Electrical Speciﬁcations

V

= 3.3V to 5.0V T = -40 to +85 C

CC

A

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply Current

I

V

= Max, CLK Frequency 44MHz

CC

-

105

111

mA

CCOP

(Notes 1, 2)

See previous DC table for remaining DC specifications

NOTES:

4. Output load 30pF, I

= 5.5 + 4.7(V) + 3.7E - 7 (V)(f); V = Volts, f = Freq. Example: 5.5 + 4.7(5.0) + 3.7E - 7(5.0)(44E6) = 111

CCOP

5. Not tested, but characterized at initial design and major process/design changes.

o

AC Electrical Speciﬁcations

V

= 3.3V to 5.0V, T = -40 to +85 , (Note 1)

CC A

44MHz

PARAMETER

CLK Period (MCLK)

SYMBOL

MIN

MAX

UNITS

ns

t

22.5

-

CP

CH

CLK High (MCLK)

t

9

-

ns

CLK Low (MCLK)

t

-

ns

CL

D2

D3

TXCLK, TXRDY, I, Q from MCLK

RXCLK, MD_RDY, RXD from MCLK

TEST 0-7, CCA, AGC, from MCLK

ANSTEL, TEST_CK

25

27

-

ns

-

ns

-

ns

D4

-

See previous AC table for remaining AC specifications

NOTES:

1. AC tests performed with C = 40pF, I = 2mA, and I = -1mA. Input reference level all inputs 1.5V. Test V = Vcc, V = 0V; V = V

OL

L

OL

OH

IH

IL

OH

= V /2.

CC

Test Circuit

(NOTE 2)

S₁

DUT

C_L

(NOTE 1)

±

IOH

1.5V

IOL

EQUIVALENT CIRCUIT

NOTES:

1. Includes Stray and JIG Capacitance

2. Switch S1 Open for I and I

CCSB

CCOP

FIGURE 22. TEST LOAD CIRCUIT

39

HSP3824

Waveforms

t_P

t_L

t_H

SCLK

t_H1

t_S1

SD, AS, R/W, CS

t_D1

SD (AS OUTPUT)

R/W

SD

t_E1

t_F1

FIGURE 23. SERIAL CONTROL PORT SIGNAL TIMING

t_CP

t_CL

t_CH

MCLK

TXCLK

t_D2

TXRDY, I, Q

TXD

t_S2

t_H2

FIGURE 24. TX PORT SIGNAL TIMING

MCLK

RXCLK

MD_RDY

RXD

t_D3

NOTE: RXD is output one MCLK after RXCLK rising to provide data hold time.

FIGURE 25. RX PORT SIGNAL TIMING

MCLK

t_D4

TEST 0-7, AGC, CCA, ANTSEL, TEST_CK

FIGURE 26. MISCELLANEOUS SIGNAL TIMING

40

HSP3824

Thin Plastic Quad Flatpack Packages (TQFP)

1

Q48.7x7 (JEDEC MO-136AE ISSUE C)

D

48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE

D1

INCHES

MIN

MILLIMETERS

-D-

SYMBOL

MAX

0.047

0.005

0.041

0.010

0.009

0.362

0.283

0.362

0.283

0.029

MIN

-

MAX

1.20

0.15

1.05

0.27

0.23

9.20

7.20

9.20

7.20

0.75

NOTES

A

A1

A2

B

-

0.002

0.038

0.007

0.347

0.268

0.347

0.268

0.018

0.05

0.95

0.17

8.80

6.80

8.80

6.80

0.45

-

-B-

-A-

6

B1

D

-

E

E1

3

D1

E

4, 5

3

E1

L

4, 5

e

-

N

48

0.020 BSC

48

0.50 BSC

7

PIN 1

e

-

SEATING

PLANE

Rev. 0 4/95

-H-

A

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

0.08

0.003

-C-

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane -C- .

0.08

0.003

D

A-B

C

S

M

S

-H-

4. Dimensions D1 and E1 to be determined at datum plane

.

5. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25mm (0.010 inch) per side.

B

11^o-13^o

0.020

0.008

B1

MIN

6. Dimension B does not include dambar protrusion. Allowable

dambar protrusion shall not cause the lead width to exceed the

maximum B dimension by more than 0.08mm (0.003 inch).

0^oMIN

0.09/0.16

0.004/0.006

A2

A1

GAGE

PLANE

7. “N” is the number of terminal positions.

BASE METAL

WITH PLATING

L

0.09/0.20

11^o-13^o

0^o-7^o

0.25

0.010

0.004/0.008

41

型号:	HSP3824VI
是否Rohs认证：	不符合
生命周期：	Obsolete
包装说明：	7 X 7 MM, PLASTIC, MO-136AE, TQFP-48
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
风险等级：	5.8
JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e0
长度：	7 mm
功能数量：	1
端子数量：	48
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP
封装等效代码：	TQFP48,.35SQ
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Other Telecom ICs
最大压摆率：	0.05 mA
标称供电电压：	3 V
表面贴装：	YES
电信集成电路类型：	BASEBAND CIRCUIT
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm
Base Number Matches：	1

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