R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Switching Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E
devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
Speed Grade
2
Description
1
Propagation Delays
Symbol
Device
Min
3
-8
-7
-6
Units
Pad to I output, no delay
Pad to I output, with delay
Propagation Delays
T
IOPI
T
IOPID
All
XCV405E
XCV812E
0.43
0.51
0.55
0.8
1.0
1.1
0.8
1.0
1.1
0.8
1.0
1.1
ns, max
ns, max
ns, max
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
Clock CLK to output IQ
T
IOPLI
T
IOPLID
T
IOCKIQ
T
IOPICK
/
T
IOICKP
T
IOPICKD
/
T
IOICKPD
T
IOICECK
/
T
IOCKICE
T
IOSRCKI
T
IOSRIQ
T
GSRQ
All
XCV405E
XCV812E
All
0.75
1.55
1.55
0.18
1.4
3.5
3.5
0.4
1.5
3.6
3.6
0.7
1.6
3.7
3.7
0.7
ns, max
ns, max
ns, max
ns, max
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
All
XCV405E
XCV812E
All
All
0.69 / 0
1.49 / 0
1.49 / 0
0.28 /
0.0
0.38
1.3 / 0
3.4 / 0
3.4 / 0
0.55 /
0.01
0.8
1.4 / 0
3.5 / 0
3.5 / 0
0.7 /
0.01
0.9
1.5 / 0
3.5 / 0
3.5 / 0
0.7 /
0.01
1.0
ns, min
ns, min
ns, min
ns, min
ns, min
Pad, with delay
ICE input
SR input (IFF, synchronous)
Set/Reset Delays
SR input to IQ (asynchronous)
GSR to output IQ
All
All
0.54
3.88
1.1
7.6
1.2
8.5
1.4
9.7
ns, max
ns, max
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see
3. The numbers for Min are
Advance
product specification numbers.
DS025-3 (v2.1) February 1, 2002
1-800-255-7778
Module 3 of 4
5
ETC [ ETC ]
