TABLE OF CONTENTS
Section 1 ............. Basic Theory of Operation
2 ............. Specifications
3 ............. Pin Descriptions
4 ............. Timing Diagrams
5 ............. Discussion of Specifications
6 ............. Detailed Theory of Operation
7 ............. Applications Information
8 ............. Mechanical
SECTION 1
BASIC THEORY OF OPERATION
The basic function of the DDC101 is illustrated in the
Simplified Equivalent Circuit shown in Figure 1. The opera-
tion is equivalent to the functions performed by a very high
quality, low bias current switched integrator followed by a
precision floating point programmable gain amplifier and
ending with a high resolution A/D converter.
The second block diagram, Figure 2, shows the DDC101
circuit architecture which implements these functions
monolithically. During each conversion, the input signal
current is collected on the internal integration capacitance,
C
INT
, as charge for a user determined integration period, T
INT
.
As the integration capacitor collects input charge, the track-
ing logic updates the internal high resolution D/A converter
at a 2MHz rate to maintain the analog input node at virtual
ground.
The digital filter oversamples the tracking logic’s output at
the beginning and end of each integration period to produce
two oversampled data points. The DDC101 measures the
charge accumulated in the integration and performs corre-
lated double sampling (CDS) by subtracting these two data
points. CDS eliminates integration cycle dependent errors
such as charge injection, offset voltage, and reset noise since
these errors are measured with the signal at each of the two
data points. The number of oversamples, and thus the fre-
quency response of the digital filter, is user programmable.
The digital filter passes a low noise, high resolution digital
output to the serial I/O register. Since the timing control of
the serial I/O register is independent of the DDC101 conver-
sion process, the outputs of multiple DDC101 units can be
connected together in series or parallel to minimize intercon-
nections.
Reset
i Signal
C
INT
A/D Converter
and Control Logic
Data Out
Sensor
Switched Integrator
Programmable Gain
Amplifier
FIGURE 1. Simplified Equivalent Circuit of DDC101 to Illustrate Function.
Test In
+V
S
DDC101 Integrated Circuit
Test Current
Reset
CDAC
C
INT
DAC
18 Bits
Analog
Input
Ground
Comparator
Digital Integration,
Tracking and
Control Logic
Digital Filter and
Error Correction
Oversampled
Digital Out
20 Bits
Serial I/O
Register
Serial In
Serial Out
V
REF
Setup
FIGURE 2. DDC101 Block Diagram.
®
DDC101
2
ETC [ ETC ]
