allows the RM5271 to execute a store every processor
cycle and to perform back-to-back stores without penalty. In
the event of a store immediately followed by a load to the
same address, a combined merge and cache write occurs
such that no penalty is incurred.
internally for use as the replacement tag if a cache miss
occurs.
On a secondary miss, a refill is accomplished with a two
signal handshake between the data output enable signal,
, which is deasserted by the controller and the tag
ScDOE*
and data write enable signal,
by the processor. Figure 5 illustrates a hit followed by a
miss in the secondary cache.
, which is asserted
ScCWE*
Secondary Cache
The RM5271 provides direct support for an external sec-
ondary cache. The secondary cache is direct mapped and
block write-through with byte parity. The RM5271 second-
ary operates identically to that of the RM5270 and supports
the same 512K and 2 MByte cache sizes (assuming nKx18
RAM organization due to capacitive loading constraints).
Other capabilities of the secondary interface include block
write, tag invalidate, and tag probe. For details of these
transactions as well as detailed timing waveforms for all the
secondary transactions, see the RM5200 Family User Man-
ual. The secondary cache can be implemented with the
Motorola MCM69T618 or its equivalent.
The secondary interface uses the
bus for transfer-
SysAD
ring data and tags information. A separate bus,
, is
ScLine
The RM5271 cache attributes for the instruction, data, and
optional external secondary caches are summarized in
Table 3.
used for transferring address and certain secondary cache
specific control signals (for the complete set of signals, see
“Pin Descriptions” on page 13).
Write buffer
A secondary read looks nearly identical to a standard pro-
cessor read except that the tag chip enable signal,
, is asserted concurrently with
and
Writes to external memory, whether cache miss write-
backs or stores to uncached or write-through addresses,
use the on-chip write buffer. The write buffer holds up to
four 64-bit address and data pairs. The entire buffer is used
for a data cache write-back and allows the processor to
proceed in parallel with the memory update. For uncached
and write-through stores, the write buffer significantly
ScTCE*
ValidOut*
, initiating a tag probe and indicating to the exter-
Release*
nal controller that a secondary cache access is being per-
formed. As a result, the external controller monitors the
secondary hit signal,
. If a hit is indicated the con-
ScMatch
troller aborts the memory read and refrains from acquiring
control of the system interface. Along with , the pro-
ScTCE*
cessor also asserts the tag data enable signal,
,
increases performance by decoupling the
bus
ScTDE*
SysAD
which causes the tag RAM’s to latch the
address
transfers from the instruction execution stream.
SysAD
Master
System
Processor
Secondary(Hit)
Processor
Secondary(Miss)
SysClock
SysAD
Data0
Addr
Data0
Data0
Addr
Data1 Data2 Data3
Data1
Data1
ScLine[19:2]
Index
Index
I0
ScWord[1:0]
I0
I0
I1
I2
I3
I1
I2
I3
I1
ScTCE*
ScMatch
ScDCE*
ScCWE*
ScDOE*
Figure 5 Secondary Cache Hit and Miss
8
RM5271 Microprocessor, Document Rev. 1.3
Quantum Effect Devices
www.qedinc.com
ETC [ ETC ]
