System Control Co-processor (CP0)
Virtual to Physical Address Mapping
The system control co-processor, also called co-processor
0 or CP0 in the MIPS architecture, is responsible for the vir-
tual memory sub-system, the exception control system,
and the diagnostics capability of the processor. The
RM5271 CP0 is logically identical to the RM5200.
The RM5271 provides three modes of virtual addressing:
•
•
•
user mode
kernel mode
supervisor mode
The memory management unit controls the virtual memory
system page mapping. It consists of an instruction address
translation buffer, ITLB, a data address translation buffer,
DTLB, a Joint instruction and data address translation
buffer, JTLB, and coprocessor registers used by the virtual
memory mapping sub-system.
This mechanism is available to system software to provide
a secure environment for user processes. Bits in the CP0
Status register determine which virtual addressing mode is
used. In the user mode, the RM5271 provides a single, uni-
form virtual address space of 256GB (2GB in 32-bit mode).
When operating in the kernel mode, four distinct virtual
address spaces, totalling 1024GB (4GB in 32-bit mode),
are simultaneously available and are differentiated by the
high-order bits of the virtual address.
System Control Co-Processor Register
The RM5271 incorporates all system control coprocessor
(CP0) registers on-chip. These registers provide the path
through which the virtual memory system’s page mapping
is examined and modified, exceptions are handled, and
operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition,
the RM5271 includes registers to implement a real-time
cycle counting facility to aid in cache diagnostic testing and
to assist in data error detection.
The RM5271 processors also support a supervisor mode in
which the virtual address space is 256.5GB (2.5GB in 32-
bit mode), divided into three regions based on the high-
order bits of the virtual address.
Figure 4 shows the address space layout for 32-bit opera-
tions.
Figure 3 shows the CP0 registers.
Context
4*
BadVAddr
8*
PageMask
5*
EntryLo0
2*
EntryHi
10*
Count
9*
Compare
11*
EntryLo1
3*
47
Status
12*
Cause
13*
Index
0*
EPC
14*
TLB
Random
1*
XContext
20*
Wired
6*
ECC
26*
CacheErr
27*
(entries protected
from TLBWR)
PRId
15*
ErrorEPC
30*
0
LLAddr
17*
TagLo
28*
Ta gH i
29*
Config
16*
Used for memory
management
Used for exception
processing
* Register number
Figure 3 CP0 Registers
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
5
ETC [ ETC ]
