used pair of entries is filled. The operation of the DTLB is
completely transparent to the user.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. The cache is virtually
indexed and physically tagged to allow address translation
to occur in simultaneously with the data cache access.
Cache Memory
The most commonly used write policy is write-back, which
means that a store to a cache line does not immediately
cause memory to be updated. This increases system per-
formance by reducing bus traffic and eliminating the bottle-
neck of waiting for each store operation to finish before
issuing a subsequent memory operation. Software can,
however, select write-through on a per-page basis when
appropriate, such as for frame buffers. Cache protocols
supported for the data cache are:
In order to keep the pipeline full and operating efficiently,
the RM5271 incorporates on-chip instruction and data
caches that can be accessed in a single processor cycle.
Each cache has its own 64-bit data path and both caches
can be accessed simultaneously. The cache subsystem
provides the integer and floating-point units with an aggre-
gate bandwidth over 4.2GB per second at an internal clock
frequency of 266 MHz. For applications requiring even
higher performance, the RM5271 also has a direct interface
to a large external secondary cache.
1.
Reads to addresses in a memory area
Uncached.
identified as uncached do not access the cache. Writes
to such addresses are written directly to main memory
without updating the cache.
Instruction Cache
The RM5271 incorporates a two-way set associative on-
chip instruction cache. This virtually indexed, physically
tagged cache is 32KB in size and is protected with word
parity.
2.
Loads and instruction fetches first search
Write-back.
the cache, reading the next memory hierarchy level
only if the desired data is not cache resident. On data
store operations, the cache is first searched to deter-
mine if the target address is cache resident. If it is resi-
dent, the cache contents are updated and the cache
line is marked for later write-back. If the cache lookup
misses, the target line is first brought into the cache
and the write is performed as above.
Since the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache
access, further increasing performance by allowing these
two operations to occur simultaneously. The cache tag con-
tains a 24-bit physical address, a valid bit, and has a single
parity bit.
3.
Loads and instruc-
Write-through with write allocate.
tion fetches first search the cache, reading from mem-
ory only if the desired data is not cache resident. Note
that write-through data is never cached in the second-
ary cache. On data store operations, the cache is first
searched to determine if the target address is cache
resident. If it is resident, the cache contents are
updated and main memory is written, leaving the write-
back bit of the cache line unchanged. No secondary
cache write occurs. If the cache lookup misses, the tar-
get line is first brought into the cache and the write is
performed as above.
The instruction cache is 64-bits wide and can be accessed
each processor cycle. Accessing 64 bits per cycle allows
the instruction cache to supply two instructions per cycle to
the superscalar dispatch unit. For typical code sequences
where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop,
the entire bandwidth available from the instruction cache is
consumed.
A cache miss refill writes 64 bits per cycle to minimize the
cache miss penalty. The line size is eight instructions (32
bytes) to maximize the performance of communication
between the processor and the memory system.
4.
Loads and
Write-through without write allocate.
instruction fetches first search the cache, reading from
memory only if the desired data is not cache resident;
write-through data is never cached in the secondary
cache. On data store operations, the cache is first
searched to determine if the target address is cache
resident. If it is resident, the cache contents are
updated and main memory is written, leaving the write-
back bit of the cache line unchanged. No secondary
cache write occurs. If the cache lookup misses, only
main memory is written.
The RM5271 supports cache locking. The contents of set A
can be locked by setting a bit in the coprocessor 0 Status
register. Locking set A prevents its contents from being
overwritten by a subsequent cache miss. Refills occur only
into set B. This mechanism allows the programmer to lock
critical code into the cache, thereby guaranteeing determin-
istic behavior for the locked code sequence.
Associated with the data cache is the store buffer. When
the RM5271 executes a STORE instruction, this single-
entry buffer is written with the store data while the tag com-
parison is performed. If the tag matches, data is written into
the data cache in the next cycle that the data cache is not
being accessed (the next non-load cycle). The store buffer
Data Cache
For fast, single cycle data access, the RM5271 includes a
32KB on-chip data cache that is two-way set associative
with a fixed 32-byte (eight words) line size.
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
7
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