JM38510/05553BEA全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

CD4049UB, CD4050B

August 1998 - Revised May 2004

Data sheet acquired from Harris Semiconductor

SCHS046I

CMOS Hex Buffer/Converters

Applications

The CD4049UB and CD4050B devices are inverting and

non-inverting hex buffers, respectively, and feature logic-

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-To-Low Logic Level Converter

level conversion using only one supply voltage (V ). The

CC

supply

input-signal high level (V ) can exceed the V

IH

CC

voltage when these devices are used for logic-level

conversions. These devices are intended for use as CMOS

to DTL/TTL converters and can drive directly two DTL/TTL

[ /Title

(CD40

49UB,

CD405

0B)

/Sub-

ject

(CMO

S Hex

Buffer/

Con-

verters)

/Autho

r ()

/Key-

words

(Harris

Semi-

con-

ductor,

CD400

0,

metal

gate,

Ordering Information

TEMP.

o

loads. (V

= 5V, V ≤ 0.4V, and I

≥ 3.3mA.)

PART NUMBER

CD4049UBF3A

CD4050BF3A

CD4049UBD

RANGE ( C)

-55 to 125

PACKAGE

16 Ld CERDIP

16 Ld SOIC

16 Ld PDIP

16 Ld SOP

CC

OL

The CD4049UB and CD4050B are designated as

replacements for CD4009UB and CD4010B, respectively.

Because the CD4049UB and CD4050B require only one

power supply, they are preferred over the CD4009UB and

CD4010B and should be used in place of the CD4009UB

and CD4010B in all inverter, current driver, or logic-level

conversion applications. In these applications the

CD4049UB and CD4050B are pin compatible with the

CD4009UB and CD4010B respectively, and can be

substituted for these devices in existing as well as in new

designs. Terminal No. 16 is not connected internally on the

CD4049UB or CD4050B, therefore, connection to this

terminal is of no consequence to circuit operation. For

applications not requiring high sink-current or voltage

conversion, the CD4069UB Hex Inverter is recommended.

CD4049UBDR

CD4049UBDT

CD4049UBDW

CD4049UBDWR

CD4049UBE

CD4049UBNSR

CD4049UBPW

CD4049UBPWR

CD4050BD

16 Ld TSSOP

16 Ld SOIC

16 Ld PDIP

16 Ld SOP

Features

CD4050BDR

• CD4049UB Inverting

• CD4050B Non-Inverting

CD4050UBDT

CD4050BDW

CD4050BDWR

CD4050BE

• High Sink Current for Driving 2 TTL Loads

• High-To-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package

o

Temperature Range; 100nA at 18V and 25 C

CD4050NSR

•

5V, 10V and 15V Parametric Ratings

CD4050BPW

CD4050BPWR

16 Ld TSSOP

CMOS

NOTE: When ordering, use the entire part number. The sufﬁx R denotes tape

and reel. The sufﬁx T denotes a small-quantity reel of 250.

Pinouts

CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)

CD4050B (PDIP, CERDIP, SOIC, SOP)

TOP VIEW

V

1

2

3

4

5

6

7

8

16 NC

15 L = F

14 F

V

1

2

3

4

5

6

7

8

16 NC

15 L = F

14 F

CC

G = A

A

G = A

A

H = B

B

13 NC

12 K = E

11 E

H = B

B

13 NC

12 K = E

11 E

I = C

C

I = C

C

10 J = D

9

D

V

9

D

V

SS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

CD4049UB, CD4050B

Functional Block Diagrams

CD4049UB

CD4050B

3

5

2

3

2

A

B

C

D

E

F

G = A

H = B

I = C

A

B

C

D

E

F

G = A

H = B

I = C

4

5

7

4

7

6

9

10

12

15

9

10

12

15

J = D

K = E

L = F

J = D

K = E

L = F

11

14

11

14

1

V

CC

SS

CC

SS

8

NC = 13

NC = 16

NC = 13

NC = 16

Schematic Diagrams

V

CC

V

CC

P

N

P

N

P

N

R

OUT

R

IN

OUT

V

SS

V

SS

FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6

IDENTICAL UNITS

FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6

IDENTICAL UNITS

2

CD4049UB, CD4050B

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Package Thermal Impedance, θ (see Note1):

JA

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 C/W

D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 C/W

DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 C/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W

PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W

Maximum Junction Temperature (Plastic Package). . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . . 65 C to 150 C

o

Operating Conditions

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

o

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265 C

SOIC - Lead Tips Only

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

o

LIMITS AT INDICATED TEMPERATURE ( C)

TEST CONDITIONS

25

V

IN

O

PARAMETER

(V)

0,5

0,10

0,15

0,20

0,5

0,10

0,15

0,5

0,10

0,15

0,5

0,10

0,15

0,5

0,10

0,15

-

V

(V)

-55

1

-40

1

85

30

125

30

MIN

TYP

0.02

0.04

5.2

6.4

16

48

-1.2

-3.9

-3.0

-8.0

0

MAX

UNITS

µA

mA

V

CC

Quiescent Device Current

-

5

-

1

I

(Max)

DD

-

10

15

20

4.5

5

2

60

2

-

4

120

600

2.1

120

600

1.8

-

4

-

20

-

20

Output Low (Sink) Current

(Min)

0.4

0.5

1.5

4.6

2.5

9.5

13.5

-

3.3

4

3.1

3.8

9.6

25

2.6

3.2

8

-

I

OL

2.9

2.4

-

10

15

5

10

6.6

5.6

-

26

20

18

24

-0.65

-2.1

-1.65

-4.3

-

Output High (Source) Current

(Min)

-0.81

-2.6

-2.0

-5.2

0.05

4.95

9.95

-0.73

-2.4

-1.8

-4.8

0.05

4.95

9.95

-0.58

-1.9

-1.35

-3.5

0.05

4.95

9.95

-0.48

-1.55

-1.18

-3.1

0.05

4.95

9.95

-

I

OH

5

-

10

15

5

-

0.05

-

Out Voltage Low Level

(Max)

V

OL

-

10

15

5

-

0

V

-

0

V

Output Voltage High Level

(Min)

-

4.95

9.95

5

V

OH

-

10

15

5

10

15

-

V

-

14.95 14.95 14.95 14.95 14.95

-

V

Input Low Voltage, V (Max)

IL

4.5

9

1

2

1

2

1

2

1

2

-

1

V

CD4049UB

-

10

15

5

-

2

V

13.5

0.5

1

-

2.5

1.5

3

2.5

1.5

3

2.5

1.5

3

2.5

1.5

3

-

2.5

1.5

3

V

Input Low Voltage, V (Max)

IL

-

V

CD4050B

-

10

15

-

V

1.5

-

4

-

4

V

3

CD4049UB, CD4050B

DC Electrical Speciﬁcations

(Continued)

o

LIMITS AT INDICATED TEMPERATURE ( C)

TEST CONDITIONS

25

V

IN

O

PARAMETER

(V)

0.5

1

(V)

V

(V)

-55

4

-40

4

85

4

125

4

MIN

4

TYP

MAX

UNITS

CC

Input High Voltage, V Min

IH

-

5

-

V

CD4049UB

-

10

15

5

8

-

1.5

4.5

9

-

12.5

3.5

7

12.5

3.5

7

12.5

3.5

7

12.5

3.5

7

12.5

3.5

7

-

V

Input High Voltage, V Min

IH

-

V

CD4050B

-

10

15

18

-

V

13.5

-

11

±0.1

11

±0.1

11

±1

11

±1

11

-

V

-5

±10

Input Current, I Max

IN

0,18

±0.1

µA

o

AC Electrical Speciﬁcations T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ

A

r

f

L

TEST CONDITIONS

LIMITS (ALL PACKAGES)

PARAMETER

Propagation Delay Time

V

TYP

60

32

45

25

45

70

40

45

30

40

32

20

15

10

55

22

50

15

50

80

40

30

20

15

MAX

120

65

UNITS

IN

CC

5

ns

Low to High, t

CD4049UB

PLH

10

15

5

10

5

90

15

5

50

90

Propagation Delay Time

5

140

80

Low to High, t

CD4050B

PLH

10

15

5

10

5

90

15

5

60

80

Propagation Delay Time

5

65

High to Low, t

CD4049UB

PHL

10

15

5

10

5

40

30

15

5

30

20

Propagation Delay Time

5

110

55

High to Low, t

CD4050B

PHL

10

15

5

10

5

100

30

15

5

100

160

80

Transition Time, Low to High, t

Transition Time, High to Low, t

5

TLH

THL

10

15

5

10

15

5

60

10

15

10

15

40

30

4

CD4049UB, CD4050B

o

AC Electrical Speciﬁcations T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ (Continued)

A

r

f

L

TEST CONDITIONS

LIMITS (ALL PACKAGES)

PARAMETER

V

TYP

MAX

UNITS

IN

CC

Input Capacitance, C

-

15

22.5

pF

IN

CD4049UB

Input Capacitance, C

CD4050B

-

5

7.5

pF

IN

Typical Performance Curves

o

T

= 25 C

T

= 25 C

A

SUPPLY VOLTAGE (V ) = 5V

CC

SUPPLY VOLTAGE (V ) = 5V

CC

5

4

3

2

1

5

MINIMUM

MAXIMUM

4

3

MINIMUM

MAXIMUM

2

1

0

1

2

3

4

0

1

2

3

4

V , INPUT VOLTAGE (V)

I

FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER

CHARACTERISTICS FOR CD4049UB

FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER

CHARACTERISTICS FOR CD4050B

o

T

= 25 C

A

T

= 25 C

A

70

60

50

40

30

20

10

70

60

15V

10V

15V

10V

50

40

30

20

10

GATE TO SOURCE VOLTAGE (V ) = 5V

GS

GATE TO SOURCE VOLTAGE (V ) = 5V

GS

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

V

, DRAIN TO SOURCE VOLTAGE (V)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN

CHARACTERISTICS

5

CD4049UB, CD4050B

Typical Performance Curves (Continued)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

-8

-7

-6

-5

-4

-3

-2

-1

0

-8

-7

-6

-5

-4

-3

-2

-1

0

o

T

= 25 C

T = 25 C

A

-5

GATE TO SOURCE VOLTAGE

= -5V

-10

GATE TO SOURCE VOLTAGE

= -5V

-10

-15

-20

-25

-30

-35

V

GS

V

GS

-15

-10V

-15V

-20

-25

-30

-10V

-15V

-35

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

10

9

SUPPLY VOLTAGE

o

8

7

6

5

4

3

2

1

0

V

= 10V

CC

8

7

6

5

4

3

2

1

0

V

= 10V

125 C

o

CC

125 C

o

T

= -55 C

T

A

= -55 C

A

V

= 5V

V

= 5V

CC

o

-55 C

o

-55 C

o

125 C

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

V , INPUT VOLTAGE (V)

I

FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS

AS A FUNCTION OF TEMPERATURE FOR CD4049UB

FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS

AS A FUNCTION OF TEMPERATURE FOR CD4050B

5

10

o

T

= 25 C

T

= 25 C

A

5

4

10

4

3

2

10

15V; 1MHz

15V; 100kHz

10V; 100kHz

15V; 10kHz

10V; 10kHz

15V; 1kHz

3

2

10

LOAD CAPACITANCE

= 50pF

10

C

L

(11pF FIXTURE + 39pF EXT)

= 15pF

10

C

L

(11pF FIXTURE + 4pF EXT)

SUPPLY VOLTAGE V

CC

= 5V FREQUENCY (f) = 10kHz

10

2

3

4

5

2

3

4

5

6

7

8

10

f, INPUT FREQUENCY (kHz)

t , t , INPUT RISE AND FALL TIME (ns)

r

f

FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY

CHARACTERISTICS

FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE

AND FALL TIMES PER INVERTER FOR CD4049UB

6

CD4049UB, CD4050B

Typical Performance Curves (Continued)

6

5

4

3

2

10

o

T

= 25 C

A

15V; 1MHz

15V; 100kHz

10V; 100kHz

15V; 10kHz

10V; 10kHz

15V; 1kHz

10

1

SUPPLY VOLTAGE V

= 5V FREQUENCY (f) = 10kHz

CC

2

3

4

5

6

7

8

10

t , t , INPUT RISE AND FALL TIME (ns)

r

f

FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE

AND FALL TIMES PER INVERTER FOR CD4050B

Test Circuits

V

CC

V

CC

V

CC

INPUTS

OUTPUTS

V

IH

V

SS

+

DVM

-

V

IL

I

DD

V

SS

V

SS

NOTE: Test any one input with other inputs at V

or V

.

CC

SS

FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT

FIGURE 14. INPUT VOLTAGE TEST CIRCUIT

CMOS 10V LEVEL TO DTL/TTL 5V LEVEL

V

= 5V

CC

V

CC

COS/MOS

IN

OUTPUT

TO DTL/TTL

INPUTS

OUTPUTS

V

CC

CD4049

INPUTS

I

10V = V

5V = V

IH

OH

V

0 = V

IL

0 = V

OL

SS

V

SS

V

In Terminal - 3, 5, 7, 9, 11, or 14

Out Terminal - 2, 4, 6, 10, 12 or 15

SS

V

Terminal - 1

Terminal - 8

NOTE: Measure inputs sequentially, to both V

CC

and V connect

SS

CC

SS

all unused inputs to either V

or V .

CC

SS

FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION

FIGURE 15. INPUT CURRENT TEST CIRCUIT

7

CD4049UB, CD4050B

Test Circuits (Continued)

V

DD

0.1µF

I

500µF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C

L

10kHz,

100kHz, 1MHz

C

INCLUDES FIXTURE CAPACITANCE

L

FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS

8

CD4049UB, CD4050B

9

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

PACKAGING INFORMATION

Orderable Device

CD4049UBD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

40

2500

250

40

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CD4049UBDR

CD4049UBDT

CD4049UBDW

CD4049UBDWR

CD4049UBE

SOIC

PDIP

D

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

DW

N

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

CD4049UBF

CD4049UBF3A

CD4049UBM

ACTIVE

CDIP

SOIC

SO

J

16

1

None

Call TI

Level-NC-NC-NC

Call TI

OBSOLETE

ACTIVE

D

CD4049UBM96

CD4049UBNSR

D

Call TI

NS

2000

90

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CD4049UBPW

CD4049UBPWR

CD4050BD

ACTIVE

TSSOP

SOIC

PDIP

PW

D

16

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

2000

40

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CD4050BDR

CD4050BDT

CD4050BDW

CD4050BDWR

CD4050BE

D

2500

250

40

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

D

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

DW

N

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

CD4050BF

CD4050BF3A

CD4050BM

ACTIVE

CDIP

SOIC

SO

J

16

1

None

Call TI

Level-NC-NC-NC

Call TI

OBSOLETE

ACTIVE

D

CD4050BNSR

NS

2000

90

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CD4050BPW

ACTIVE

TSSOP

PW

16

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

CD4050BPWR

2000

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

JM38510/05553BEA

JM38510/05554BEA

ACTIVE

CDIP

J

16

1

None

Call TI

Level-NC-NC-NC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265

型号:	JM38510/05553BEA
Brand Name：	Texas Instruments
生命周期：	Active
零件包装代码：	DIP
包装说明：	DIP,
针数：	16
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	1.46
系列：	4000/14000/40000
JESD-30 代码：	R-GDIP-T16
长度：	19.05 mm
逻辑集成电路类型：	BUFFER
最大I（ol）：	0.018 A
功能数量：	6
输入次数：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
最大电源电流（ICC）：	0.03 mA
传播延迟（tpd）：	120 ns
认证状态：	Not Qualified
筛选级别：	MIL-M-38510 Class B
座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	15 V
最小供电电压 (Vsup)：	5 V
标称供电电压 (Vsup)：	10 V
表面贴装：	NO
技术：	CMOS
温度等级：	MILITARY
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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