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产品型号K4D263238E-GC2A的概述

K4D263238E-GC2A 芯片概述 K4D263238E-GC2A 是一款高性能的动态随机存取存储器（DRAM），由三星电子（Samsung Electronics）制造，广泛应用于计算机、服务器和移动设备。作为一种DDR2 SDRAM（双数据速率2同步动态随机存取存储器），该芯片具备较高的数据传输率和能效，相比早期的DDR1 SDRAM，其速度和性能都有显著提高。详细参数 K4D263238E-GC2A 的参数如下： - 容量: 2GB - 总线宽度: 64-bit - 数据速率: 533 Mbps - 工作频率: 266 MHz - 内存类型: DDR2 SDRAM - 工作电压: 1.8V - 封装类型: FBGA (Fine-Pitch Ball Grid Array) - 引脚数: 60 - 访问延迟: CL=3 (CAS Latency) 厂家、包装、封装 ...

产品型号K4D263238E-GC2A的Datasheet PDF文件预览

128M GDDR SDRAM

K4D263238E-GC

128Mbit GDDR SDRAM

1M x 32Bit x 4 Banks

Graphic Double Data Rate

Synchronous DRAM

with Bi-directional Data Strobe and DLL

(144-Ball FBGA)

Revision 1.7

November 2003

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

Revision History

Revision 1.7 (November 14, 2003)

• Typo corrected

Revision 1.6 (August 14, 2003)

• Added a note for the input reference voltage of clock in case of differential clocks

Revision 1.5 (August 11, 2003)

• Typo corrected

Revision 1.4 (April 30, 2003)

• Added Lead free package part number in the datasheet

Revision 1.3 (April 14, 2003)

• K4D263238E-GC2A/33/36 support wide voltage range from 2.375V to 2.94V

Revision 1.2 (April 7, 2003)

• Removed K4D263238E-GL36 from the spec.

Revision 1.1 (March 17, 2003)

• Typo corrected

Revision 1.0 (February 13, 2003)

• Defined DC spec

• Added K4D263238E-GC25 and K4D263238E-GL36 in the spec.

- 2 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

FEATURES

• VDD/VDDQ = 2.8V ± 5% for -GC25

• VDD/VDDQ = 2.5V ± 5% for -GC2A/33/36/40/45

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• No Wrtie-Interrupted by Read Function

• 4 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• MRS cycle with address key programs

-. Read latency 3, 4, 5 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• Auto & Self refresh

• 32ms refresh period (4K cycle)

• 144-Ball FBGA

• Maximum clock frequency up to 400MHz

• Maximum data rate up to 800Mbps/pin

• Differential clock input

ORDERING INFORMATION

Part NO.

Max Freq.

Max Data Rate

Interface

Package

SSTL_2

(VDD/VDDQ=2.8V)

K4D263238E-GC25

400MHz

800Mbps/pin

K4D263238E-GC2A

K4D263238E-GC33

K4D263238E-GC36

K4D263238E-GC40

K4D263238E-GC45

350MHz

300MHz

275MHz

250MHz

222MHz

700Mbps/pin

600Mbps/pin

550Mbps/pin

500Mbps/pin

444Mbps/pin

144-Ball FBGA

SSTL_2

(VDD/VDDQ=2.5V)

K4D263238E-VC is the Lead Free package part number.

GENERAL DESCRIPTION

FOR 1M x 32Bit x 4 Bank DDR SDRAM

The K4D263238E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by

32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

- 3 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

PIN CONFIGURATION (Top View)

DQS0

DM0

VSSQ

DQ3

DQ2

DQ0

DQ31

DQ29

DQ28

VSSQ

DM3

DQS3

DQ4

DQ6

VDDQ

DQ5

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

VSSQ

VDD

VDDQ

VSSQ

VSS

DQ1

VDDQ

VDD

VDDQ

VDD

DQ30

VSSQ

VDDQ

VSSQ

VSS

VDDQ

DQ26

VDDQ

DQ15

DQ13

DM1

DQ11

DQ9

DQ27

DQ25

DQ24

DQ14

DQ12

DQS1

DQ10

DQ8

VSSQ

VDD

DQ7

VSSQ

VSS

VSSQ

VSS

DQ17

DQ19

DQS2

DQ21

DQ22

CAS

VSSQ

VSS

VSSQ

VSS

VDDQ

Thermal Thermal Thermal Thermal

VSS VSS VSS VSS

Thermal Thermal Thermal Thermal

VSS VSS VSS VSS

Thermal Thermal Thermal Thermal

VSS VSS VSS VSS

Thermal Thermal Thermal Thermal

VDDQ

VDD

VDDQ

VDD

VSS

A10

VSS

VDD

A11

VSS

VDD

VSS

RFU1

RAS

BA1

RFU2

MCL

BA0

A8/AP

CKE

VREF

NOTE:

1. RFU1 is reserved for A12

2. RFU2 is reserved for BA2

3. VSS Thermal balls are optional

PIN DESCRIPTION

CK,CK

CKE

Differential Clock Input

Clock Enable

BA0, BA1

A0 ~A11

Bank Select Address

Address Input

Data Input/Output

Power

Chip Select

DQ0 ~ DQ31

VDD

RAS

CAS

Row Address Strobe

Column Address Strobe

Write Enable

VSS

Ground

VDDQ

VSSQ

Power for DQ’s

Ground for DQ’s

No Connection

Must Connect Low

DQS

Data Strobe

Data Mask

RFU

Reserved for Future Use

MCL

- 4 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

Type

Function

The differential system clock Input.

CK, CK*1

Input

All of the inputs are sampled on the rising edge of the clock except

DQ’s and DM’s that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CKE

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

RAS

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Data input and output are synchronized with both edge of DQS.

DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,

DQS3 for DQ24 ~ DQ31.

DQS0 ~ DQS3

DM0 ~ DM3

Input/Output

Input

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for

DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.

DQ0 ~ DQ31

BA0, BA1

Input/Output

Input

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.

Column address CA8 is used for auto precharge.

A0 ~ A11

Input

VDD/VSS

Power Supply

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

VDDQ/VSSQ

VREF

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

This pin is recommended to be left "No connection" on the device

Reserved for future use

MCL

Must Connect Low

Must connect low

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

- 5 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)

Intput Buffer

LWE

CK, CK

Data Input Register

Serial to parallel

LDMi

Bank Select

1Mx32

x32

DQi

CK,CK

ADDR

Column Decoder

Latency & Burst Length

Data Strobe

(DQS0~DQS3)

Programming Register

LWCBR

DLL

LCKE

LRAS LCBR

LWE

LCAS

CK,CK

LDMi

Timing Register

CK,CK

CKE

RAS

CAS

DMi

- 6 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

FUNCTIONAL DESCRIPTION

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order

Power up & Initialization Sequence

12 13

15 16 17

CK,CK

tRP

2 Clock min.

tRFC

2 Clock min.

tRP

2 Clock min.

Command

precharge

ALL Banks

MRS

DLL Reset

precharge

ALL Banks

1st Auto

Refresh

2nd Auto

Refresh

Mode

Any

Command

EMRS

200 Clock min.

Inputs must be

stable for 200us

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

- 7 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

MODE REGISTER SET(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

Address Bus

BA1

BA0

A11

A10

Mode Register

RFU

DLL

CAS Latency

Burst Length

Burst Type

DLL

Test Mode

Type

DLL Reset

mode

Sequential

Interleave

Normal

Test

Yes

Burst Length

Burst Type

CAS Latency

BA0

An ~ A0

MRS

Sequential Interleave

A6 A5 A4 Latency

Reserve

Reserved

EMRS

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Full page

Reserve

Reserved

MRS Cycle

CK, CK

Precharge

All Banks

Any

Command

NOP

MRS

NOP

tMRD=2 tCK

tRP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

- 8 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

EXTENDED MODE REGISTER SET(EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

Address Bus

BA1

BA0

A11

A10

Extended

Mode Register

RFU

D.I.C

RFU

D.I.C DLL

BA0

An ~ A0

MRS

DLL Enable

Output Driver Impedence Control

A6 A1

Enable

Disable

N/A

Weak

N/A

Do not use

60%

EMRS

Do not use

N/A

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

Figure 7. Extended Mode Register set

- 9 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

Unit

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

3.3

VDDQ

TSTG

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Symbol

Min

2.66

Typ

Max

2.94

Unit

Note

2.8

1, 8

Device Supply voltage

VDD

2.375

2.66

2.5

2.625

1, 9

2.8

2.94

1, 8

Output Supply voltage

VDDQ

2.375

0.49*VDDQ

VREF-0.04

VREF+0.15

-0.30

2.5

2.625

1, 9

Reference voltage

VREF

Vtt

0.51*VDDQ

VREF+0.04

VDDQ+0.30

VREF-0.15

Termination voltage

VREF

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

VIH(DC)

VIL(DC)

VOH

VOL

Vtt+0.76

IOH=-15.2mA, 7

Vtt-0.76

IOL=+15.2mA, 7

IIL

-5

IOL

-5

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

7. Output logic high voltage and low voltage is depend on output channel condition.

8. VDD/VDDQ = 2.8V ± 5% for K4D263238E-GC25

9. VDD/VDDQ = 2.5V ± 5% for K4D263238E-GC2A/33/36/40/45

10 . K4D263238E-GC2A/33/36 support wide voltage range from 2.375V to 2.94V.

- 10 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-25

-2A

-33

-36

-40

-45

Burst Lenth=2 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min)

Operating Current

(One Bank Active)

ICC1

530

455

400

375

350

Precharge Standby Current

in Power-down mode

ICC2P

ICC2N

ICC3P

ICC3N

ICC4

110

185

200

410

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min)

Precharge Standby Current

in Non Power-down mode

150

160

300

130

140

260

125

130

250

115

120

240

110

120

230

Active Standby Current

power-down mode

CKE ≤ VIL(max), tCC= tCC(min)

CKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min)

Active Standby Current

in Non Power-down mode

Operating Current

( Burst Mode)

IOL=0mA ,tCC= tCC(min),

Page Burst, All Banks activated.

1090

415

830

350

735

310

680

310

625

300

570

290

Refresh Current

ICC5

ICC6

ICC7

tRC ≥ tRFC(min)

CKE ≤ 0.2V

Self Refresh Current

Operating Current

(4Bank interleaving)

Burst Length=4 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min)

1210

935

830

770

710

655

Note : 1. Measured with outputs open.

2. Refresh period is 32ms.

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

VREF+0.35

Input High (Logic 1) Voltage ;DQ

VIH

VREF+0.4

VREF-0.35

VREF-0.4

VDDQ+0.6

0.5*VDDQ+0.2

Input Low (Logic 0) Voltage; DQ

VIL

0.7

Clock Input Differential Voltage; CK and CK

Clock Input Crossing Point Voltage; CK and CK

VID

VIX

0.8

1, 3

0.5*VDDQ-0.2

Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

3. 400MHz only

- 11 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

AC OPERATING TEST CONDITIONS (TA= 0 to 65°C)

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

CK and CK signal maximum peak swing

CK signal minimum slew rate

0.50*VDDQ

1.5

1.0

VREF+0.4/VREF-0.4

VREF

V/ns

Input Levels(VIH/VIL)

Input timing measurement reference level

Output timing measurement reference level

Output load condition

Vtt

See Fig.1

Note 1 : In case of differential clocks(CK and CK), input reference voltage for clock is a CK and CK ’s crossing point

Accordingly, clock duty should be measured at a CK and CK ’s crossing point.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

VREF

=0.5*VDDQ

CLOAD=30pF

(Fig. 1) Output Load Circuit

CAPACITANCE (TA= 25°C, f=1MHz)

Parameter

Symbol

CIN1

Min

1.0

Max

5.0

4.0

6.5

Unit

Input capacitance( CK, CK )

Input capacitance(A0~A11, BA0~BA1)

Input capacitance( CKE, CS, RAS,CAS, WE )

Data & DQS input/output capacitance(DQ0~DQ31)

Input capacitance(DM0 ~ DM3)

CIN2

CIN3

COUT

CIN4

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

CDC1

Value

Unit

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

0.1 + 0.01

CDC2

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

- 12 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

AC CHARACTERISTICS

-25

-2A

-33

-36

-40

-45

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

4.5

Max

CL=3

CL=4

CL=5

CK cycle time

2.86

3.3

3.6

4.0

tCK

2.5

0.45

CK high level width

CK low level width

0.55

0.35

1.1

0.6

1.15

0.45

0.55

0.35

1.1

0.6

1.15

0.45

-0.55

0.55

0.35

1.1

0.6

1.15

0.45

-0.6

0.55

0.6

0.40

1.1

0.6

1.15

0.45

-0.6

0.55

0.6

-0.6

0.40

1.1

0.6

1.2

0.45

-0.7

0.55

0.7

0.45

1.1

0.6

1.2

tCH

tCK

0.45

-0.55

0.45

-0.55

tCL

DQS out access time from CK

Output access time from CK

Data strobe edge to Dout edge

Read preamble

tDQSCK

tAC

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPREH

tWPST

tDQSH

tDQSL

tIS

tCK

0.9

0.4

0.8

Read postamble

0.4

CK to valid DQS-in

0.85

0.8

DQS-In setup time

DQS-in hold time

0.35

0.4

0.35

0.4

0.35

0.4

0.35

0.4

0.35

0.4

0.3

tCK

DQS write postamble

0.6

0.55

0.6

0.55

0.6

0.55

0.6

0.55

0.6

0.55

0.4

0.45

1.0

0.45

0.6

0.55

DQS-In high level width

DQS-In low level width

Address and Control input setup

Address and Control input hold

DQ and DM setup time to DQS

DQ and DM hold time to DQS

0.45

0.8

0.45

0.8

0.45

0.8

0.45

0.9

0.45

0.9

0.8

0.9

tIH

0.35

0.40

tDS

tDH

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

tCLmin

tCHmin

Clock half period

tHP

Data Hold skew factor

0.4

0.45

0.5

t^QHS

tHP-

tQHS

tHP-

tQHS

tHP-

tQHS

tHP-

tQHS

tHP-

tQHS

tHP-

tQHS

Data output hold time from DQS

tQH

Jitter over 1~6 clock cycle error

100

105

Cycle to cyde duty cycle error

Rise and fall times of CK

100

700

105

700

tDCERR

tR, tF

600

700

*1. The cycle to cycle jitter over 1~6 cycle short term jitter.

Simplified Timing @ BL=2, CL=4

tCH

tCL

tCK

CK, CK

tIS

tIH

tDQSCK

tDQSS

tWPREH

tDQSH

tDQSL

tRPST

Qa2

tRPRE

DQS

tWPRES

tDQSQ

tDS tDH

tAC

Qa1

Db0

Db1

COMMAND

WRITEB

READA

- 13 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case

output vaild window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL4, BL2)

tHP

CK, CK

DQS

tDQSQ(max)

tQH

tDQSQ(max)

Qa0

Qa1

COMMAND

READA

Power Down Timing

CK, CK

t_IS

CKE

3t_CK

t_IS

Command

VALID

NOP

VALID

Enter Power Down mode

(Read or Write operation

must not be in progress)

Exit Powr Down mode

- 14 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

AC CHARACTERISTICS (I)

-25

-2A

-33

-36

-40

-45

Unit Note

Parameter

Row cycle time

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

tCK

tRC

Refresh row cycle time

Row active time

tRFC

100K

100K tCK

tRAS

RAS to CAS delay for Read

RAS to CAS delay for Write

Row precharge time

tCK

tRCDRD

tRCDWR

tRP

Row active to Row active

tRRD

Last data in to Row precharge @Nor-

mal Precharge

tCK

tWR

Last data in to Row precharge @Auto

Precharge

tWR_A

Last data in to Read command

Col. address to Col. address

Mode register set cycle time

tCK

tCDLR

tCCD

tMRD

Auto precharge write recovery + Pre-

charge

tCK

tDAL

tXSR

tPDEX

tREF

Exit self refresh to read command

200

3tCK+

tIS

3tCK+

tIS

3tCK+

tIS

3tCK+

tIS

3tCK+

tIS

3tCK+

tIS

Power down exit time

Refresh interval time

7.8

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

(Unit : Number of Clock)

AC CHARACTERISTICS (II)

K4D263238E-GC25

Unit

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

400MHz ( 2.5ns )

tCK

K4D263238E-GC2A

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

tCK

350MHz ( 2.86ns )

300MHz ( 3.3ns )

275MHz ( 3.6ns )

250MHz ( 4.0ns )

222MHz ( 4.5ns )

K4D263238E-GC33

Frequency

300MHz ( 3.3ns )

275MHz ( 3.6ns )

250MHz ( 4.0ns )

222MHz ( 4.5ns )

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

tCK

- 15 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

K4D263238E-GC36

Unit

tCK

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

275MHz ( 3.6ns )

250MHz ( 4.0ns )

222MHz ( 4.5ns )

K4D263238E-GC40

Frequency

250MHz ( 4.0ns )

222MHz ( 4.5ns )

Unit

tCK

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

K4D263238E-GC45

Frequency

Unit

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

222MHz ( 4.5ns )

tCK

Simplified Timing(2) @ BL=4

CK, CK

BA[1:0]

BAa

BAb BAa

BAb

A8/AP

ADDR

(A0~A7,

A9,A10)

DQS

Da0

Da1 Da2 Da3

Da0 Da1 Da2 Da3

Db0 Db1 Db2 Db3

COMMAND

ACTIVEA

WRITEA

PRECH

ACTIVEA

ACTIVEB WRITEA

WRITEB

tRCD

tRAS

tRP

tRC

tRRD

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

- 16 -

Rev 1.7 (Nov. 2003)

128M GDDR SDRAM

K4D263238E-GC

PACKAGE DIMENSIONS (144-Ball FBGA)

A1 INDEX MARK

12.0

0.8x11=8.8

A1 INDEX MARK

0.10 Max

0.8

0.45 ± 0.05

0.40

13 12 11 10 9

8 7 6 5 4 3 2

0.35 ± 0.05

0.40

1.40 Max

Unit : mm

- 17 -

Rev 1.7 (Nov. 2003)

K4D263238E-GC2A相关文章

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K4D263238E-GC2A产品参数

型号:	K4D263238E-GC2A
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	BGA
包装说明：	LFBGA, BGA144,12X12,32
针数：	144
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.9
Is Samacsys：	N
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	0.55 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	350 MHz
I/O 类型：	COMMON
交错的突发长度：	2,4,8
JESD-30 代码：	S-PBGA-B144
JESD-609代码：	e0
长度：	12 mm
内存密度：	134217728 bit
内存集成电路类型：	DDR DRAM
内存宽度：	32
功能数量：	1
端口数量：	1
端子数量：	144
字数：	4194304 words
字数代码：	4000000
工作模式：	SYNCHRONOUS
最高工作温度：	65 °C
最低工作温度：
组织：	4MX32
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA
封装等效代码：	BGA144,12X12,32
封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
电源：	2.5 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.4 mm
自我刷新：	YES
连续突发长度：	2,4,8,FP
最大待机电流：	0.095 A
子类别：	DRAMs
最大压摆率：	0.935 mA
最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL
端子节距：	0.8 mm
端子位置：	BOTTOM
宽度：	12 mm
Base Number Matches：	1

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