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产品型号K4D623238B-QC55的概述

芯片K4D623238B-QC55的概述 K4D623238B-QC55是一款由韩国三星电子（Samsung Electronics）出品的动态随机存取存储器（DRAM）芯片，这款芯片在高性能计算和消费电子市场中广泛应用。凭借其优异的存储性能、低功耗特性和小型化设计，K4D623238B-QC55被广泛集成到各类电子设备中，如手机、平板电脑、笔记本电脑及一些高端电子设备中。该芯片采用了先进的工艺制造技术，其容量通常为2GB，工作电压相对较低，支持高速的数据传输。这一系列的技术参数使得K4D623238B-QC55在性能上具备了显著的优势，能够满足现代电子设备对内存的高要求。芯片K4D623238B-QC55的详细参数 K4D623238B-QC55的主要技术参数如下： - 容量：2GB - 接口类型：DDR2 SDRAM - 数据传输速率：可支持533 MT/s (Mega Tra...

产品型号K4D623238B-QC55的Datasheet PDF文件预览

64M DDR SDRAM

K4D623238B-QC

64Mbit DDR SDRAM

512K x 32Bit x 4 Banks

Double Data Rate Synchronous RAM

with Bi-directional Data Strobe and DLL

(100-Pin TQFP)

Revision 1.2

September 2001

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

Revision History

Revision 1.2 (September 1, 2001)

• Added K4D623238B-QL* as a low power part (ICC6=1mA)

• Added ICC7 (Operating current at 4bank interleaving)

• Added 100MHz@CL2

Revision 1.1 (August 2, 2001)

• Changed tCK(max) from 7ns to 10ns

Revision 1.0(June 22, 2001)

Revision 0.4(April 10, 2001) - Preliminary Spec

•Added K4D623238B-QC60

Revision 0.3 (February 10, 2001) - Preliminary Spec

Revision 0.2 (December 13, 2000) - Target Spec

•Defined Target Specification

Revision 0.0 (November 21, 2000)

- 2 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM

with Bi-directional Data Strobe and DLL

FEATURES

• 2.5V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• MRS cycle with address key programs

-. Read latency 3,4 (clock)

• Auto & Self refresh

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• 16ms refresh period (2K cycle)

• 100-Pin TQFP package

• Maximum clock frequency up to 222MHz

• Maximum data rate up to 444Mbps/pin

• Differential clock input

• No Write Interrupted by Read Function

ORDERING INFORMATION

Part NO.

Max Freq.

222MHz

200MHz

183MHz

166MHz

Max Data Rate

444Mbps/pin

400Mbps/pin

366Mbps/pin

333Mbps/pin

Interface

Package

K4D623238B-QC/L45

K4D623238B-QC/L50

K4D623238B-QC/L55

K4D623238B-QC/L60

SSTL_2

100 TQFP

GENERAL DESCRIPTION

FOR 512K x 32Bit x 4 Bank DDR SDRAM

The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32

bits, fabricated with SAMSUNGs’ high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

- 3 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

PIN CONFIGURATION (Top View)

100

DQ29

VSSQ

DQ30

DQ31

VSS

VDDQ

N.C

RFU

A10

VDD

N.C

100 Pin TQFP

20 x 14 mm2

N.C

VSSQ

RFU

0.65mm pin Pitch

DQS

VDDQ

VDD

DQ0

DQ1

VSSQ

DQ2

PIN DESCRIPTION

CK,CK

CKE

Differential Clock Input

BA0, BA1

A0 ~A10

DQ0 ~ DQ31

VDD

Bank Select Address

Address Input

Data Input/Output

Power

Clock Enable

Chip Select

RAS

CAS

Row Address Strobe

Column Address Strobe

Write Enable

VSS

Ground

VDDQ

Power for DQ’s

Ground for DQ’s

No Connection

Must Connect Low

DQS

Data Strobe

VSSQ

Data Mask

RFU

Reserved for Future Use

MCL

- 4 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

Type

Function

The differential system clock Input.

CK, CK*1

Input

All of the inputs are sampled on the rising edge of the clock except

DQ’s and DM’s that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CKE

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

RAS

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQS

Input/Output

Input

Data input and output are synchronized with both edge of DQS.

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for

DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.

DM0 ~ DM3

DQ0 ~ DQ31

BA0, BA1

Input/Output

Input

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA10, Column addresses : CA0 ~ CA7.

Column address CA8 is used for auto precharge.

A0 ~ A10

Input

VDD/VSS

Power Supply

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

VDDQ/VSSQ

VREF

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

This pin is recommended to be left "No connection" on the device

Reserved for future use

MCL

Must Connect Low

Must connect low

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

- 5 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

BLOCK DIAGRAM (512Kbit x 32I/O x 4 Bank)

Intput Buffer

LWE

LDMi

CK, CK

Data Input Register

Serial to parallel

Bank Select

512Kx32

x32

DQi

CK,CK

ADDR

Column Decoder

Latency & Burst Length

Data Strobe

Programming Register

LWCBR

DLL

LCKE

LRAS LCBR

LWE

LCAS

CK,CK

LDMi

Timing Register

CK,CK

CKE

RAS

CAS

DMi

- 6 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

FUNCTIONAL DESCRIPTION

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK, CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

Power up & Initialization Sequence

12 13

16 17

CK, CK

tRP

2 Clock min.

tRFC

2 Clock min.

tRP

2 Clock min.

Command

precharge

ALL Banks

precharge

ALL Banks

2nd Auto

Refresh

MRS

DLL Reset

1st Auto

Refresh

Mode

Any

Command

EMRS

200 Clock min.

Inputs must be

stable for 200us

- 7 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

MODE REGISTER SET(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A10 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

Address Bus

BA1

BA0

A10

Mode Register

RFU

DLL

CAS Latency

Burst Length

Burst Type

DLL

Test Mode

Type

DLL Reset

mode

Sequential

Interleave

Normal

Test

Yes

Burst Length

Burst Type

Sequential Interleave

CAS Latency

BA0

An ~ A0

MRS

A6 A5 A4 Latency

Reserve

Reserved

EMRS

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

Reserve

Full page

Reserve

Reserved

MRS Cycle

CK, CK

Precharge

All Banks

Any

Command

NOP

MRS

NOP

tMRD=2 tCK

tRP

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

- 8 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

EXTENDED MODE REGISTER SET(EMRS)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A10

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

Address Bus

BA1

RFU

BA0

A10

Extended

Mode Register

RFU

D.I.C

RFU

D.I.C

DLL

BA0

An ~ A0

DLL Enable

Enable

Output Driver Impedence Control

A6 A1

MRS

Normal

Weak

100%

60%

EMRS

Disable

N/A

Do not use

30%

Matched impedance

* RFU(Reserved for future use)

should stay "0" during EMRS

cycle.

Figure 7. Extended Mode Register set

- 9 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

2.0

Unit

VDDQ

TSTG

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter

Device Supply voltage

Output Supply voltage

Reference voltage

Symbol

VDD

VDDQ

VREF

Vtt

Min

2.375

Typ

Max

2.625

Unit

Note

2.50

2.375

2.50

2.625

0.49*VDDQ

VREF-0.04

VREF+0.15

-0.30

0.51*VDDQ

VREF+0.04

VDDQ+0.30

VREF-0.15

Termination voltage

VREF

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

VIH

VIL

VOH

VOL

IIL

Vtt+0.76

IOH=-15.2mA

Vtt-0.76

IOL=+15.2mA

-5

IOL

-5

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V

- 10 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-45

-50

-55

-60

Burst Lenth=2 tRC ³ tRC(min)

IOL=0mA, tCC= tCC(min)

Operating Current

(One Bank Active)

ICC1

300

280

265

250

Precharge Standby Current

in Power-down mode

ICC2P

ICC2N

ICC3P

ICC3N

ICC4

CKE £ VIL(max), tCC= tCC(min)

CKE ³ VIH(min), CS ³ VIH(min),

tCC= tCC(min)

Precharge Standby Current

in Non Power-down mode

115

105

190

110

105

180

105

170

100

105

160

Active Standby Current

power-down mode

CKE £ VIL(max), tCC= tCC(min)

CKE ³ VIH(min), CS ³ VIH(min),

tCC= tCC(min)

Active Standby Current in

in Non Power-down mode

Operating Current

( Burst Mode)

IOL=0mA ,tCC= tCC(min),

Page Burst, All Banks activated.

600

310

550

300

500

290

470

280

Refresh Current

ICC5

ICC6

tRC ³ tRFC(min)

CKE £ 0.2V

Self Refresh Current

Operating Current

( 4Bank Interleaving)

Burst Lenth=4 tRC ³ tRC(min)

IOL=0mA, tCC= tCC(min)

ICC7

750

700

650

620

Note : 1. Measured with outputs open.

2. Refresh period is 16ms.

3. K4D623238B-QC*

4. K4D623238B-QL*

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65C‘

Parameter

Symbol

VIH

Min

VREF+0.35

Typ

Max

Unit

Note

Input High (Logic 1) Voltage; DQ

Input Low (Logic 0) Voltage; DQ

VIL

VREF-0.35

VDDQ+0.6

0.5*VDDQ+0.2

Clock Input Differential Voltage ; CK and CK

Clock Input Crossing Point Voltage ; CK and CK

VID

0.7

VIX

0.5*VDDQ-0.2

Note :

1. VIH(Max) = 4.2V. The overshoot voltage duration is < 3ns at VDD

2. VIL(Min) = -1.5V. The undershoot voltage duration is < 3ns at VSS

3. VID is the magnitude of the difference between the input level on CK and the input level on CK

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

- 11 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

AC OPERATING TEST CONDITIONS (VDD=2.5V±0.125V, TA= 0 to 65 °C)

Parameter

Value

Unit

Note

Input reference voltage for CK(for single ended)

CK and CK signal maximum peak swing

CK signal minimum slew rate

0.50*VDDQ

1.5

1.0

VREF+0.35/VREF-0.35

VREF

V/ns

Input Levels(VIH/VIL)

Input timing measurement reference level

Output timing measurement reference level

Output load condition

Vtt

See Fig.1

Vtt=0.5*VDDQ

RT=50W

VREF

Output

Z0=50W

=0.5*VDDQ

CLOAD=30pF

(Fig. 1) Output Load Circuit

CAPACITANCE (VDD=3.3V, TA= 25°C, f=1MHz)

Parameter

Input capacitance( CK, CK )

Symbol

CIN1

Min

1.0

Max

5.0

Unit

Input capacitance(A0~A10, BA0~BA1)

CIN2

1.0

4.0

Input capacitance

( CKE, CS, RAS,CAS, WE )

CIN3

1.0

4.0

Data & DQS input/output capacitance(DQ0~DQ31)

Input capacitance(DM0 ~ DM3)

COUT

CIN4

1.0

6.0

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

CDC1

Value

Unit

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

0.1 + 0.01

CDC2

Note :

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

- 12 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

AC CHARACTERISTICS

-45

-50

-55

-60

Parameter

Symbol

Unit Note

Min

5.0

4.5

Max

Min

5.0

Max

Min

5.5

Max

Min

6.0

Max

CL=2

CL=3

CL=4

CK cycle time

tCK

CK high level width

0.45

-0.7

0.55

+0.7

+0.45

1.1

0.6

1.2

0.45

-0.7

0.55

+0.7

+0.45

1.1

0.6

1.2

0.45

-0.75

0.55

+0.75

+0.5

1.1

0.6

1.25

0.45

-0.75

0.55

0.75

0.5

1.1

0.6

1.25

tCK

tCH

CK low level width

tCL

DQS out access time from CK

Output access time from CK

Data strobe edge to Dout edge

Read preamble

tDQSCK

tAC

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPREH

tWPST

tDQSH

tDQSL

tIS

0.9

0.4

0.8

0.9

0.4

0.8

0.9

0.4

0.75

tCK

Read postamble

0.4

CK to valid DQS-in

0.75

DQS-In setup time

DQS-in hold time

0.3

0.4

1.0

0.45

0.3

0.4

1.0

0.45

0.25

0.4

0.25

0.4

1.1

0.5

tCK

DQS write postamble

DQS-In high level width

DQS-In low level width

0.6

0.4

Address and Control input setup

Address and Control input hold

DQ and DM setup time to DQS

DQ and DM hold time to DQS

1.1

tIH

tDS

0.5

tDH

tCLmin or

tCHmin

tCLmin or

tCHmin

tCLmin or

tCHmin

tCLmin or

tCHmin

Clock half period

tHP

tQH

Data output hold time from DQS

tHP-0.45

tHP-0.5

Simplified Timing @ BL=2, CL=3

tCH

tCL

tCK

CK, CK

tIS

tIH

tDQSCK

tDQSS

tWPREH

tDQSH

tWPST

tRPST

tRPRE

Hi-Z

DQS

tWPRES

tDQSQ

tDS tDH

tAC

Da1

Da2

Db0

Db1

COMMAND

WRITEB

READA

- 13 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case

output vaild window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL3, BL2)

tHP

CK, CK

DQS

tDQSQ(max)

tQH

tDQSQ(max)

Da0

Da1

COMMAND

READA

- 14 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

AC CHARACTERISTICS (I)

-45

-50

-55

-60

Unit

Note

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Row cycle time

tRC

tCK

Refresh row cycle time

Row active time

tRFC

100K

tRAS

100K

RAS to CAS delay for Read

RAS to CAS delay for Write

Row precharge time

tRCDRD

tRCDWR

tRP

Row active to Row active

tRRD

tWR

tCDLR

tCCD

tMRD

Last data in to Row precharge

Last data in to Read command

Col. address to Col. address

Mode register set cycle time

Auto precharge write recovery +

Precharge

tDAL

tCK

Exit self refresh to read command tXSR

200

1tCK+tIS

7.8

200

1tCK+tIS

7.8

200

1tCK+tIS

7.8

200

1tCK+tIS

7.8

tCK

Power down exit time

Refresh interval time

tPDEX

tREF

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

AC CHARACTERISTICS (II)

K4D623238B-QC45

Frequency

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

tCK

222MHz ( 4.5ns )

200MHz ( 5.0ns )

183MHz ( 5.5ns )

166MHz ( 6.0ns )

143MHz ( 7.0ns )

K4D623238B-QC50

Frequency

200MHz ( 5.0ns )

183MHz ( 5.5ns )

166MHz ( 6.0ns )

143MHz ( 7.0ns )

Unit

tCK

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

K4D623238B-QC55

Frequency

183MHz ( 5.5ns )

166MHz ( 6.0ns )

143MHz ( 7.0ns )

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

Unit

tCK

K4D623238B-QC60

Frequency

166MHz ( 6.0ns )

143MHz ( 7.0ns )

Unit

tCK

Cas Latency

tRC

tRFC

tRAS

tRCDRD tRCDWR

tRP

tRRD

tDAL

- 15 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

Simplified Timing(2) @ BL=4

CK, CK

BA[1:0]

BAa

BAb

BAa

BAb

A8/AP

ADDR

(A0~A7,

A9,A10)

DQS

Da0

Da1 Da2 Da3

Da0 Da1 Da2 Da3

Db0 Db1 Db2 Db3

COMMAND

ACTIVEA

WRITEA

PRECH

ACTIVEA

ACTIVEB WRITEA

WRITEB

tRCD

tRAS

tRP

tRC

tRRD

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

- 16 -

Rev. 1.2 (Sep. 2001)

64M DDR SDRAM

K4D623238B-QC

PACKAGE DIMENSIONS (TQFP)

Dimensions in Millimeters

0 ~ 7×

17.20 ± 0.20

14.00 ± 0.10

#100

23.20 ± 0.20

20.00 ± 0.10

0.825

0.30 ± 0.08

0.65

0.09~0.20

0.13 MAX

1.00 ± 0.10

1.20 MAX *

0.10 MAX

0.05 MIN

0.80 ± 0.20

- 17 -

Rev. 1.2 (Sep. 2001)

K4D623238B-QC55相关文章

配单直通车

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K4D623238B-QC55产品参数

型号:	K4D623238B-QC55
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	QFP
包装说明：	TQFP, TQFP100,.7X.9
针数：	100
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.86
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	0.75 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	182 MHz
I/O 类型：	COMMON
交错的突发长度：	2,4,8
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0
长度：	20 mm
内存密度：	67108864 bit
内存集成电路类型：	DDR DRAM
内存宽度：	32
功能数量：	1
端口数量：	1
端子数量：	100
字数：	2097152 words
字数代码：	2000000
工作模式：	SYNCHRONOUS
最高工作温度：	65 °C
最低工作温度：
组织：	2MX32
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP
封装等效代码：	TQFP100,.7X.9
封装形状：	RECTANGULAR
封装形式：	FLATPACK, THIN PROFILE
电源：	2.5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
自我刷新：	YES
连续突发长度：	2,4,8,FP
最大待机电流：	0.06 A
子类别：	DRAMs
最大压摆率：	0.65 mA
最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
宽度：	14 mm
Base Number Matches：	1

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