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    产品型号K4S281632A-TL1L的Datasheet PDF文件预览

    K4S281632A  
    CMOS SDRAM  
    128Mbit SDRAM  
    2M x 16Bit x 4 Banks  
    Synchronous DRAM  
    LVTTL  
    Revision 0.0  
    Aug. 1999  
    * Samsung Electronics reserves the right to change products or specification without notice.  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    2M x 16Bit x 4 Banks Synchronous DRAM  
    FEATURES  
    GENERAL DESCRIPTION  
    • JEDEC standard 3.3V power supply  
    • LVTTL compatible with multiplexed address  
    • Four banks operation  
    The K4S281632A is 134,217,728 bits synchronous high data  
    rate Dynamic RAM organized as 4 x 2,097,152 words by 16  
    bits, fabricated with SAMSUNG¢s high performance CMOS  
    technology. Synchronous design allows precise cycle control  
    with the use of system clock I/O transactions are possible on  
    every clock cycle. Range of operating frequencies, programma-  
    ble burst length and programmable latencies allow the same  
    device to be useful for a variety of high bandwidth, high perfor-  
    mance memory system applications.  
    • MRS cycle with address key programs  
    -. CAS latency (2 & 3)  
    -. Burst length (1, 2, 4, 8 & Full page)  
    -. Burst type (Sequential & Interleave)  
    • All inputs are sampled at the positive going edge of the system  
    clock.  
    • Burst read single-bit write operation  
    • DQM for masking  
    ORDERING INFORMATION  
    Part No.  
    Max Freq.  
    Interface Package  
    • Auto & self refresh  
    K4S281632A-TC/L75  
    K4S281632A-TC/L80  
    K4S281632A-TC/L1H  
    K4S281632A-TC/L1L  
    133MHz(CL=3)  
    125MHz(CL=3)  
    100MHz(CL=2)  
    100MHz(CL=3)  
    • 64ms refresh period (4K cycle)  
    54  
    LVTTL  
    TSOP(II)  
    K4S281632A-TC/L10 66MHz(CL=2 &3)  
    FUNCTIONAL BLOCK DIAGRAM  
    LWE  
    Data Input Register  
    LDQM  
    Bank Select  
    2M x 16  
    2M x 16  
    2M x 16  
    2M x 16  
    DQi  
    CLK  
    ADD  
    Column Decoder  
    Latency & Burst Length  
    LCKE  
    Programming Register  
    LRAS  
    LCBR  
    LWE  
    LCAS  
    LWCBR  
    LDQM  
    Timing Register  
    CLK  
    CKE  
    CS  
    RAS  
    CAS  
    WE  
    LDQM  
    UDQM  
    * Samsung Electronics reserves the right to change products or specification without notice.  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    PIN CONFIGURATION (Top view)  
    VDD  
    DQ0  
    VDDQ  
    DQ1  
    DQ2  
    VSSQ  
    DQ3  
    DQ4  
    VDDQ  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    VSS  
    54  
    53  
    52  
    51  
    50  
    49  
    48  
    47  
    46  
    45  
    44  
    43  
    42  
    41  
    40  
    39  
    38  
    37  
    36  
    35  
    34  
    33  
    32  
    31  
    30  
    29  
    28  
    DQ15  
    VSSQ  
    DQ14  
    DQ13  
    VDDQ  
    DQ12  
    DQ11  
    VSSQ  
    DQ10  
    DQ9  
    VDDQ  
    DQ8  
    VSS  
    N.C/RFU  
    UDQM  
    CLK  
    CKE  
    N.C  
    A11  
    A9  
    DQ5 10  
    DQ6 11  
    VSSQ  
    12  
    DQ7 13  
    14  
    VDD  
    LDQM 15  
    WE 16  
    CAS 17  
    RAS 18  
    CS 19  
    BA0 20  
    BA1 21  
    A10/AP 22  
    A0 23  
    A8  
    A7  
    A6  
    A5  
    A4  
    VSS  
    A1 24  
    A2 25  
    A3 26  
    VDD  
    54Pin TSOP (II)  
    (400mil x 875mil)  
    (0.8 mm Pin pitch)  
    27  
    PIN FUNCTION DESCRIPTION  
    Pin  
    Name  
    System clock  
    Input Function  
    CLK  
    Active on the positive going edge to sample all inputs.  
    Disables or enables device operation by masking or enabling all inputs except  
    CLK, CKE and DQM  
    CS  
    Chip select  
    Masks system clock to freeze operation from the next clock cycle.  
    CKE should be enabled at least one cycle prior to new command.  
    Disable input buffers for power down in standby.  
    CKE  
    Clock enable  
    Row/column addresses are multiplexed on the same pins.  
    Row address : RA0 ~ RA11, Column address : CA0 ~ CA8  
    A0 ~ A11  
    BA0 ~ BA1  
    RAS  
    Address  
    Selects bank to be activated during row address latch time.  
    Selects bank for read/write during column address latch time.  
    Bank select address  
    Row address strobe  
    Column address strobe  
    Write enable  
    Latches row addresses on the positive going edge of the CLK with RAS low.  
    Enables row access & precharge.  
    Latches column addresses on the positive going edge of the CLK with CAS low.  
    Enables column access.  
    CAS  
    Enables write operation and row precharge.  
    Latches data in starting from CAS, WE active.  
    WE  
    Makes data output Hi-Z, tSHZ after the clock and masks the output.  
    Blocks data input when L(U)DQM active.  
    L(U)DQM  
    Data input/output mask  
    DQ0 ~ 15  
    VDD/VSS  
    Data input/output  
    Data inputs/outputs are multiplexed on the same pins.  
    Power and ground for the input buffers and the core logic.  
    Power supply/ground  
    Isolated power supply and ground for the output buffers to provide improved noise  
    immunity.  
    VDDQ/VSSQ  
    Data output power/ground  
    No connection  
    /reserved for future use  
    N.C/RFU  
    This pin is recommended to be left No Connection on the device.  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    ABSOLUTE MAXIMUM RATINGS  
    Parameter  
    Voltage on any pin relative to Vss  
    Voltage on VDD supply relative to Vss  
    Storage temperature  
    Symbol  
    VIN, VOUT  
    VDD, VDDQ  
    TSTG  
    Value  
    -1.0 ~ 4.6  
    -1.0 ~ 4.6  
    -55 ~ +150  
    1
    Unit  
    V
    V
    °C  
    W
    Power dissipation  
    PD  
    Short circuit current  
    IOS  
    50  
    mA  
    Note :  
    Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.  
    Functional operation should be restricted to recommended operating condition.  
    Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
    DC OPERATING CONDITIONS  
    Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)  
    Parameter  
    Supply voltage  
    Symbol  
    VDD, VDDQ  
    VIH  
    Min  
    3.0  
    2.0  
    -0.3  
    2.4  
    -
    Typ  
    Max  
    3.6  
    Unit  
    V
    Note  
    3.3  
    Input logic high voltage  
    Input logic low voltage  
    Output logic high voltage  
    Output logic low voltage  
    Input leakage current  
    3.0  
    VDD+0.3  
    0.8  
    V
    1
    VIL  
    0
    -
    V
    2
    VOH  
    -
    V
    IOH = -2mA  
    IOL = 2mA  
    3
    VOL  
    -
    0.4  
    V
    ILI  
    -10  
    -
    10  
    uA  
    Notes :  
    1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.  
    2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.  
    3. Any input 0V £ VIN £ VDDQ,  
    Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.  
    CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)  
    Pin  
    Symbol  
    CCLK  
    CIN  
    Min  
    2.5  
    2.5  
    2.5  
    4.0  
    Max  
    4.0  
    5.0  
    5.0  
    6.5  
    Unit  
    pF  
    Note  
    Clock  
    1
    2
    2
    3
    RAS, CAS, WE, CS, CKE, DQM  
    Address  
    pF  
    CADD  
    COUT  
    pF  
    DQ0 ~ DQ15  
    pF  
    Notes :  
    1. -75 only specify a maximum value of 3.5pF  
    2. -75 only specify a maximum value of 3.8pF  
    3. -75 only specify a maximum value of 6.0pF  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    DC CHARACTERISTICS  
    (Recommended operating condition unless otherwise noted, TA = 0 to 70°C)  
    Version  
    -75 -80 -1H -1L -10  
    Parameter  
    Symbol  
    Test Condition  
    Unit Note  
    Burst length = 1  
    tRC ³ tRC(min)  
    IO = 0 mA  
    Operating current  
    (One bank active)  
    ICC1  
    150 150 140 140 140 mA  
    1
    ICC2P CKE £ VIL(max), tCC = 10ns  
    1
    Precharge standby current in  
    power-down mode  
    mA  
    ICC2PS CKE & CLK £ VIL(max), tCC = ¥  
    1
    CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns  
    ICC2N  
    20  
    mA  
    7
    Input signals are changed one time during 20ns  
    Precharge standby current in  
    non power-down mode  
    CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
    ICC2NS  
    Input signals are stable  
    ICC3P CKE £ VIL(max), tCC = 10ns  
    5
    Active standby current in  
    power-down mode  
    mA  
    ICC3PS CKE & CLK £ VIL(max), tCC = ¥  
    5
    CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns  
    ICC3N  
    30  
    20  
    mA  
    mA  
    Active standby current in  
    non power-down mode  
    (One bank active)  
    Input signals are changed one time during 20ns  
    CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
    ICC3NS  
    Input signals are stable  
    IO = 0 mA  
    Operating current  
    (Burst mode)  
    Page burst  
    4Banks Activated  
    tCCD = 2CLKs  
    ICC4  
    180 170 145 145 145 mA  
    220 220 210 210 210 mA  
    1
    Refresh current  
    ICC5  
    ICC6  
    tRC ³ tRC(min)  
    CKE £ 0.2V  
    2
    3
    4
    C
    L
    1.5  
    mA  
    uA  
    Self refresh current  
    800  
    Notes :  
    1. Measured with outputs open.  
    2. Refresh period is 64ms.  
    3. K4S281632A-TC**  
    4. K4S281632A-TL**  
    5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)  
    Parameter  
    AC input levels (Vih/Vil)  
    Value  
    2.4/0.4  
    1.4  
    Unit  
    V
    Input timing measurement reference level  
    Input rise and fall time  
    V
    tr/tf = 1/1  
    1.4  
    ns  
    V
    Output timing measurement reference level  
    Output load condition  
    See Fig. 2  
    3.3V  
    Vtt = 1.4V  
    1200W  
    50W  
    VOH (DC) = 2.4V, IOH = -2mA  
    VOL (DC) = 0.4V, IOL = 2mA  
    Output  
    Output  
    Z0 = 50W  
    50pF  
    50pF  
    870W  
    (Fig. 1) DC output load circuit  
    (Fig. 2) AC output load circuit  
    OPERATING AC PARAMETER  
    (AC operating conditions unless otherwise noted)  
    Version  
    Parameter  
    Symbol  
    Unit  
    Note  
    - 75  
    15  
    - 80  
    16  
    - 1H  
    20  
    20  
    20  
    50  
    100  
    70  
    2
    - 1L  
    20  
    -10  
    20  
    24  
    24  
    50  
    Row active to row active delay  
    RAS to CAS delay  
    tRRD(min)  
    tRCD(min)  
    tRP(min)  
    ns  
    ns  
    1
    1
    1
    1
    20  
    20  
    20  
    Row precharge time  
    20  
    20  
    20  
    ns  
    tRAS(min)  
    tRAS(max)  
    tRC(min)  
    45  
    48  
    50  
    ns  
    Row active time  
    us  
    Row cycle time  
    65  
    68  
    70  
    80  
    ns  
    1
    2,5  
    5
    Last data in to row precharge  
    Last data in to Active delay  
    Last data in to new col. address delay  
    Last data in to burst stop  
    tRDL(min)  
    tDAL(min)  
    tCDL(min)  
    tBDL(min)  
    tCCD(min)  
    CLK  
    -
    2 CLK + 20 ns  
    1
    1
    1
    2
    CLK  
    CLK  
    CLK  
    2
    2
    Col. address to col. address delay  
    3
    CAS latency=3  
    CAS latency=2  
    Number of valid output data  
    ea  
    4
    -
    1
    Notes :  
    1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time  
    and then rounding off to the next higher integer.  
    2. Minimum delay is required to complete write.  
    3. All parts allow every cycle column address change.  
    4. In case of row precharge interrupt, auto precharge and read burst stop.  
    5. For -80/1H/1L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .  
    SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
    - 75  
    - 80  
    - 1H  
    - 1L  
    - 10  
    Parameter  
    Symbol  
    tCC  
    Unit Note  
    Min Max Min Max Min Max Min Max Min Max  
    CAS latency=3  
    7.5  
    -
    8
    -
    10  
    10  
    10  
    12  
    10  
    13  
    CLK cycle time  
    1000  
    1000  
    1000  
    1000  
    1000 ns  
    1
    1,2  
    2
    CAS latency=2  
    CAS latency=3  
    CAS latency=2  
    CAS latency=3  
    CAS latency=2  
    5.4  
    -
    6
    -
    6
    6
    6
    7
    7
    CLK to valid  
    output delay  
    tSAC  
    ns  
    7
    2.7  
    -
    3
    -
    3
    3
    3
    3
    2
    1
    1
    3
    3
    3
    3
    2
    1
    1
    3
    Output data  
    hold time  
    tOH  
    ns  
    3
    CLK high pulse width  
    CLK low pulse width  
    Input setup time  
    tCH  
    tCL  
    2.5  
    2.5  
    1.5  
    0.8  
    1
    3
    3
    2
    1
    1
    3.5  
    3.5  
    2.5  
    1.5  
    1
    ns  
    ns  
    ns  
    ns  
    ns  
    3
    3
    3
    3
    2
    tSS  
    Input hold time  
    tSH  
    tSLZ  
    CLK to output in Low-Z  
    CAS latency=3  
    CAS latency=2  
    5.4  
    -
    6
    -
    6
    6
    6
    7
    7
    CLK to output  
    in Hi-Z  
    tSHZ  
    ns  
    7
    Notes :  
    1. Parameters depend on programmed CAS latency.  
    2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
    3. Assumed input rise and fall time (tr & tf) = 1ns.  
    If tr & tf is longer than 1ns, transient time compensation should be considered,  
    i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
    DQ BUFFER OUTPUT DRIVE CHARACTERISTICS  
    Parameter  
    Symbol  
    Condition  
    Min  
    Typ  
    Max  
    Unit  
    Notes  
    Measure in linear  
    region : 1.2V ~ 1.8V  
    Output rise time  
    trh  
    1.37  
    4.37  
    3.8  
    Volts/ns  
    Volts/ns  
    Volts/ns  
    Volts/ns  
    3
    Measure in linear  
    region : 1.2V ~ 1.8V  
    Output fall time  
    Output rise time  
    Output fall time  
    tfh  
    trh  
    tfh  
    1.30  
    2.8  
    3
    Measure in linear  
    region : 1.2V ~ 1.8V  
    3.9  
    2.9  
    5.6  
    1,2  
    1,2  
    Measure in linear  
    region : 1.2V ~ 1.8V  
    2.0  
    5.0  
    Notes :  
    1. Rise time specification based on 0pF + 50 W to VSS, use these values to design to.  
    2. Fall time specification based on 0pF + 50 W to VDD, use these values to design to.  
    3. Measured into 50pF only, use these values to characterize to.  
    4. All measurements done with respect to VSS.  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    66MHz and 100MHz Pull-up  
    1.5 2.5  
    IBIS SPECIFICATION  
    0
    0.5  
    1
    2
    3
    3.5  
    IOH Cha.racteristics (Pull-up)  
    0
    -100  
    -200  
    -300  
    -400  
    -500  
    -600  
    100MHz  
    Min  
    I (mA)  
    100MHz  
    Max  
    I (mA)  
    -2.4  
    -27.3  
    66MHz  
    Min  
    I (mA)  
    Voltage  
    (V)  
    3.45  
    3.3  
    3.0  
    2.6  
    2.4  
    2.0  
    1.8  
    1.65  
    1.5  
    1.4  
    1.0  
    0.0  
    0.0  
    -21.1  
    -34.1  
    -58.7  
    -67.3  
    -73.0  
    -77.9  
    -80.8  
    -88.6  
    -93.0  
    -74.1  
    -0.7  
    -7.5  
    -129.2  
    -153.3  
    -197.0  
    -226.2  
    -248.0  
    -269.7  
    -284.3  
    -344.5  
    -502.4  
    -13.3  
    -27.5  
    -35.5  
    -41.1  
    -47.9  
    -52.4  
    -72.5  
    -93.0  
    Voltage  
    IOH Min (100MHz)  
    IOH Min (66MHz)  
    IOH Max (66 and 100MHz)  
    66MHz and 100MHz Pull-down  
    IOL Characteristics (Pull-down)  
    250  
    200  
    150  
    100  
    50  
    100MHz  
    Min  
    100MHz  
    Max  
    66MHz  
    Min  
    I (mA)  
    0.0  
    Voltage  
    (V)  
    0.0  
    I (mA)  
    0.0  
    I (mA)  
    0.0  
    0.4  
    27.5  
    41.8  
    51.6  
    58.0  
    70.7  
    72.9  
    75.4  
    77.0  
    77.6  
    80.3  
    81.4  
    70.2  
    17.7  
    26.9  
    33.3  
    37.6  
    46.6  
    48.0  
    49.5  
    50.7  
    51.5  
    54.2  
    54.9  
    0.65  
    0.85  
    1.0  
    1.4  
    1.5  
    1.65  
    1.8  
    1.95  
    3.0  
    107.5  
    133.8  
    151.2  
    187.7  
    194.4  
    202.5  
    208.6  
    212.0  
    219.6  
    222.6  
    3.45  
    0
    0
    0.5  
    1
    1.5  
    2
    2.5  
    3
    3.5  
    Voltage  
    IOL Min (100MHz)  
    IOL Min (66MHz)  
    IOL Max (100MHz)  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    CMOS SDRAM  
    Minimum VDD clamp current  
    (Referenced to VDD)  
    VDD Clamp @ CLK, CKE, CS, DQM & DQ  
    VDD (V)  
    0.0  
    0.2  
    0.4  
    0.6  
    0.7  
    0.8  
    0.9  
    1.0  
    1.2  
    1.4  
    1.6  
    1.8  
    2.0  
    2.2  
    2.4  
    2.6  
    I (mA)  
    0.0  
    0.0  
    0.0  
    0.0  
    0.0  
    0.0  
    0.0  
    0.23  
    1.34  
    3.02  
    5.06  
    7.35  
    9.83  
    12.48  
    15.30  
    18.31  
    20  
    15  
    10  
    5
    0
    0
    1
    2
    3
    Voltage  
    I (mA)  
    Minimum VSS clamp current  
    -2 -1  
    VSS Clamp @ CLK, CKE, CS, DQM & DQ  
    -3  
    0
    VSS (V)  
    -2.6  
    -2.4  
    -2.2  
    -2.0  
    -1.8  
    -1.6  
    -1.4  
    -1.2  
    -1.0  
    -0.9  
    -0.8  
    -0.7  
    -0.6  
    -0.4  
    -0.2  
    0.0  
    I (mA)  
    -57.23  
    -45.77  
    -38.26  
    -31.22  
    -24.58  
    -18.37  
    -12.56  
    -7.57  
    -3.37  
    -1.75  
    -0.58  
    -0.05  
    0.0  
    0
    -10  
    -20  
    -30  
    -40  
    -50  
    -60  
    0.0  
    0.0  
    0.0  
    Voltage  
    I (mA)  
    Rev. 0.0 Aug. 1999  
    K4S281632A  
    SIMPLIFIED TRUTH TABLE  
    Command  
    CMOS SDRAM  
    A11,  
    CKEn-1  
    CKEn  
    CS  
    RAS  
    CAS  
    WE  
    DQM BA0,1  
    A10/AP  
    Note  
    A9 ~ A0  
    Register  
    Mode register set  
    Auto refresh  
    H
    X
    H
    L
    L
    L
    L
    L
    X
    OP code  
    1,2  
    3
    H
    L
    L
    L
    L
    H
    X
    X
    X
    X
    Entry  
    3
    Refresh  
    Self  
    L
    H
    L
    H
    X
    L
    H
    X
    H
    H
    X
    H
    3
    fefresh  
    Exit  
    H
    3
    Bank active & row addr.  
    H
    H
    X
    X
    X
    X
    V
    V
    Row address  
    Column  
    address  
    (A0 ~ A8)  
    Read &  
    column address  
    Auto precharge disable  
    Auto precharge enable  
    Auto precharge disable  
    Auto precharge enable  
    L
    H
    L
    4
    4,5  
    4
    L
    L
    H
    H
    L
    L
    H
    L
    Column  
    address  
    (A0 ~ A8)  
    Write &  
    column address  
    H
    X
    X
    V
    H
    X
    L
    4,5  
    6
    Burst stop  
    Precharge  
    H
    H
    X
    X
    L
    L
    H
    L
    H
    H
    L
    L
    X
    X
    Bank selection  
    All banks  
    V
    X
    X
    H
    H
    L
    X
    V
    X
    X
    H
    X
    V
    X
    X
    H
    X
    V
    X
    X
    H
    X
    V
    X
    V
    X
    X
    H
    X
    V
    Entry  
    H
    L
    X
    Clock suspend or  
    active power down  
    X
    X
    Exit  
    L
    H
    L
    X
    H
    L
    X
    X
    Entry  
    H
    Precharge power down mode  
    H
    L
    Exit  
    L
    H
    X
    X
    DQM  
    H
    H
    V
    X
    X
    X
    7
    H
    L
    X
    H
    X
    H
    No operation command  
    Notes :  
    1. OP Code : Operand code  
    A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)  
    2. MRS can be issued only at all banks precharge state.  
    A new command can be issued after 2 CLK cycles of MRS.  
    3. Auto refresh functions are as same as CBR refresh of DRAM.  
    The automatical precharge without row precharge command is meant by "Auto".  
    Auto/self refresh can be issued only at all banks precharge state.  
    4. BA0 ~ BA1 : Bank select addresses.  
    If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
    If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
    If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
    If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
    If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
    5. During burst read or write with auto precharge, new read/write command can not be issued.  
    Another bank read/write command can be issued after the end of burst.  
    New row active of the associated bank can be issued at tRP after the end of burst.  
    6. Burst stop command is valid at every burst length.  
    7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
    but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
    Rev. 0.0 Aug. 1999  
    配单直通车
    K4S281632B-NC1H产品参数
    型号:K4S281632B-NC1H
    是否Rohs认证：不符合
    生命周期：Obsolete
    IHS 制造商：SAMSUNG SEMICONDUCTOR INC
    零件包装代码：TSOP2
    包装说明：TSOP, TSSOP54,.46,16
    针数：54
    Reach Compliance Code：unknown
    ECCN代码：EAR99
    HTS代码：8542.32.00.02
    风险等级：5.79
    Is Samacsys：N
    访问模式：FOUR BANK PAGE BURST
    最长访问时间：6 ns
    其他特性：AUTO/SELF REFRESH
    最大时钟频率 (fCLK)：100 MHz
    I/O 类型：COMMON
    交错的突发长度：1,2,4,8
    JESD-30 代码：R-PDSO-G54
    JESD-609代码：e0
    长度：11.2 mm
    内存密度：134217728 bit
    内存集成电路类型：SYNCHRONOUS DRAM
    内存宽度：16
    功能数量：1
    端口数量：1
    端子数量：54
    字数：8388608 words
    字数代码：8000000
    工作模式：SYNCHRONOUS
    最高工作温度：70 °C
    最低工作温度：
    组织：8MX16
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：TSOP
    封装等效代码：TSSOP54,.46,16
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, THIN PROFILE
    峰值回流温度（摄氏度）：NOT SPECIFIED
    电源：3.3 V
    认证状态：Not Qualified
    刷新周期：4096
    座面最大高度：1.2 mm
    自我刷新：YES
    连续突发长度：1,2,4,8,FP
    最大待机电流：0.001 A
    子类别：DRAMs
    最大压摆率：0.21 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子面层：Tin/Lead (Sn/Pb)
    端子形式：GULL WING
    端子节距：0.4 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：10.16 mm
    Base Number Matches：1
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