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K9F4008W0A-TCB0芯片概述 K9F4008W0A-TCB0是一款由三星电子（Samsung Electronics）公司生产的NAND闪存芯片，经过设计可广泛应用于存储需求的各类电子产品中。其关键设计目标是提供高性能、高密度和低功耗的存储解决方案，尤其适合用于移动设备、数字产品及工控设备等领域。K9F4008W0A-TCB0芯片通常用于需要大量数据存储与快速读取的场合，例如智能手机、平板电脑、SSD（固态硬盘）、嵌入式系统以及其他消费电子产品。 K9F4008W0A-TCB0详细参数该芯片的具体特点如下： - 存储容量：512MB（64M x 8位或32M x 8位×2） - 制造工艺：采用先进的65nm或更小的制程技术，确保低功耗和高性能。 - 接口标准：支持同步和异步操作，提供灵活的接口设计。 - 工作电压：工作电压为2.7V至3.6V，适合于大多数电池供电的小型设备...

产品型号K9F4008W0A-TCB0的Datasheet PDF文件预览

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

Document Title

512K x 8 bit NAND Flash Memory

Revision History

Revision No. History

Draft Date

Remark

0.0

1.0

1.1

Initial issue.

April 10th 1998

Preliminary

1. Changed Operating Voltage 2.7V ~ 5.5V ® 3.0V ~ 5.5V

July 14th 1998

April 10th 1999

Data Sheet 1999

1. Added CE don’t care mode during the data-loading and reading

1.2

1.3

1. Changed device name

- KM29W040AT -> K9F4008W0A-TCB0

- KM29W040AIT -> K9F4008W0A-TIB0

Sep. 15th 1999

Jul. 23th 2001

1.Powerup sequence is added

: Recovery time of minimum 1ms is required before internal circuit gets

ready for any command sequences

~ 2.5V

High

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.

3. AC parameter tAR is devided into tAR1, tAR2 (before revision)

ALE to RE Delay

tAR

250

(after revision)

ALE to RE Delay(ID Delay)

tAR1

tAR2

ALE to RE Delay(Read Cycle)

250

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

512K x 8 Bit NAND Flash Memory

FEATURES

GENERAL DESCRIPTION

· Voltage Supply: 3.0V~5.5V

· Organization

- Memory Cell Array : 512K x 8 bit

The K9F4008W0A is a 512Kx8bit NAND Flash Memory. Its

NAND cell structure provides the most cost-effective solution

for Digital Audio Recording. A Program operation programs a

32-byte frame in typical 500ms and an Erase operation erase a

4K-byte block in typical 6ms. Data in a frame can be read out at

a burst cycle rate of 120ns/byte. The I/O pins serve as the ports

for address and data input/output as well as for command

inputs. The on-chip write controller automates the program and

erase operations, including program or erase pulse repetition

where required, and performs internal verification of cell data.

- Data Register

: 32 x 8 bit

· Automatic Program and Erase (Typical)

- Frame Program : 32 Byte in 500ms

- Block Erase : 4K Byte in 6ms

· 32-Byte Frame Read Operation

- Random Access : 15ms(Max.)

- Serial Frame Access : 120ns(Min.)

· Command/Address/Data Multiplexed I/O port

· Low Operation Current (Typical)

- 10mA Standby Current

- 10mA Read/ Program/Erase Current

· Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

· Package

The K9F4008W0A is an optimum solution for flash memory

application that do not require the high performance levels or

capacity of larger density flash memories. These application

include data storage in digital Telephone Answering

Devices(TAD) and other consumer applications that require

voice data storage.

- 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)

PIN DESCRIPTION

PIN CONFIGURATION

Pin Name

I/O0 ~ I/O7

CLE

Pin Function

Data Inputs/Outputs

Command Latch Enable

Address Latch Enable

Chip Enable

VSS

CLE

ALE

N.C

VCC

R/B

GND

N.C

ALE

Read Enable

Write Enable

Write Protect

GND

R/B

Ground Input

Ready/Busy output

Power

N.C

I/O0

I/O1

I/O2

I/O3

VSS

N.C

I/O7

I/O6

I/O5

I/O4

VCC

VSS

Ground

N.C

No Connection

44(40) TSOP (II)

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC, VSS or GND inputs disconnected.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

X-Buffers

A7 - A18

Latches

4M Bit

& Decoders

NAND Flash ARRAY

32Byte x 4Frames x 4096Rows

Y-Buffers

Latches

A0 - A6

& Decoders

Page Register & S/A

Y-Gating

Command

I/O Buffers & Latches

Control Logic

& High Voltage

Generator

I/O0

I/O7

Global Buffers

CLE ALE WP

Figure 2. ARRAY ORGANIZATION

Good Block

1Block = 32 Rows

= 4K Bytes

The 1st Block (4KB)

1 Frame = 32 Bytes

1 Row = 4 Frames = 128 Bytes

1 Block = 32 Rows = 4K Bytes

1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks

= 4Mbits

4K Rows

(=128 Blocks)

8 bit

128Bytes

I/O0 ~ I/O7

Frame Register

32 Bytes

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

Column Address (A0-A4)

Frame Address (A5-A6)

1st Cycle

2nd Cycle

3rd Cycle

Row Address (A7-A11)

Block Address (A12-A18)

A10

A18

A11

A12

A13

A14

A15

(1)

A16

A17

NOTE : *(1) : X can be VIL or VIH

* The device ignores any additional input of address cycles than reguired.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell

arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The

memory array is composed of unit NAND structures in which 8 cells are connected serially.

Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The

array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is

executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.

The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to

higher density flash memories by maintaining consistency in system board design. Command, address and data are all written

through I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and

Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus

cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a

19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles fol-

lowing by a command input. In the Block Erase operation, however, only the two row address cycles are required.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of

the K9F4008W0A.

Table 1. COMMAND SETS

Function

1st. Cycle

00h

2nd. Cycle

Acceptable Command during Busy

Read

Reset

FFh

10h

D0h

Frame Program

Block Erase

Status read

Read ID

80h

60h

70h

90h

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched

into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of

WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.

However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to

standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge

of RE which also increments the internal column address counter by one.

I/O Port : I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z

when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when

the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is

in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip

is deselected or when outputs are disabled.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to VSS

VIN

-0.6 to +7.0

-10 to +125

-40 to +125

-65 to +150

K9F4008W0A-TCB0

K9F4008W0A-TIB0

Temperature Under Bias

TBIAS

TSTG

°C

Storage Temperature

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C)

Parameter

Supply Voltage

Symbol

VCC

Min

3.0

Typ.

Max

5.5

Unit

VSS

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Vcc = 3.0V ~ 3.6V

Vcc = 3.6V ~ 5.5V

Parameter

Symbol

Test Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Burst Read Cycle

Program

ICC1

ICC2

tRC=120ns,CE=VIL, IOUT=0mA

Oper-

ating

Current

Erase

ICC3

Stand-by Current(TTL)

Stand-by Current(CMOS)

Input Leakage Current

Output Leakage Current

ISB1

ISB2

ILI

CE=VIH, WP=0V/VCC

CE=VCC-0.2, WP=0V/VCC

VIN=0 to 5.5V

±10

ILO

VOUT=0 to 5.5V

VCC+

0.3

VCC+

0.5

Input High Voltage, All

inputs

VIH

2.4

Input Low Voltage, All inputs

Output High Voltage Level

Output Low Voltage Level

Output Low Current(R/B)

VIL

VOH

VOL

IOH=-400mA

-0.3

2.4

0.6

-0.3

2.4

0.8

IOL=2.1mA

0.4

IOL(R/B) VOL=0.4V

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

125

128

Block

NOTE :

1. The K9F4008W0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase

or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

AC TEST CONDITION

(K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C, VCC=3.0V ~ 5.5V unless otherwise noted)

Value

Parameter

Vcc=3.0V ~ 3.6V

0.4V to 2.6V

Vcc=3.6V ~ 5.5V

0.4V to 2.6V

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

5ns

0.8V and 2.0V

1 TTL GATE and CL = 100pF

CAPACITANCE(TA=25°C, Vcc=5.0V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

Input / Output Capacitance

Input Capacitance

CI/O

VIL=0V

VIN=0V

CIN

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

ALE

Mode

Command Input

Read Mode

Write Mode

Address Input(3clock)

Command Input

Address Input(3clock)

Data Input

Sequential Read & Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X⁽¹⁾

(2)

0V/VCC

Stand-by

NOTE : 1. X can be VIL or VIH

2. WP should be biased to CMOS high or CMOS low for standby.

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

0.5

Max

Unit

Program Time

tPROG

Nop

Number of Partial Program Cycles in the Same Frame

Block Erase Time

cycles

tBERS

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

tCLS

tCLH

tCS

Min

120

Max

Unit

CLE Set-up Time

CLE Hold Time

CE Setup Time

CE Hold Time

tCH

WE Pulse Width

ALE Setup Time

ALE Hold Time

Data Set-up Time

Data Hold Time

Write Cycle Time

tWP

tALS

tALH

tDS

tDH

tWC

WE High Hold Time

tWH

AC Characteristics for Operation

Parameter

Symbol

Min

Max

Unit

Data Transfer from Cell to Register

ALE to RE Delay(ID Delay)

ALE to RE Delay(Read Cycle)

CE low to RE low (ID read)

CLE to RE Delay

tAR1

tAR2

tCR

250

100

tCLR

tRR

Ready to RE Low

RE Pulse Width

tRP

WE High to Busy

tWB

200

Read Cycle Time

tRC

120

RE Access Time

tREA

tRHZ

tCHZ

tREH

tIR

RE High to Output Hi-Z

CE High to Output Hi-Z

RE High Hold Time

Output Hi-Z to RE Low

CE High to Ready(in case of interception by CE at read)

RE Low to Status Output

tCRY

tRSTO

tCSTO

tWHR

tWHRID

tRST

100+tr(R/B)⁽¹⁾

CE Low to Status Output

WE High to RE Low

100

RE access time(Read ID)

Device Resetting Time(Read/Program/Erase)

5/10/500

NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The informa-

tion regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd

page of the invalid block(s) with 00h data. Devices with invalid block(s) have the same quality level or as devices with all valid blocks

and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is iso-

lated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid

block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not

require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the invalid

block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the

system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table

via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh" on the 1st and 2nd page

Create (or update)

Check "FFh" ?

Invalid Block(s) Table

Yes

Last Block ?

Yes

End

Figure 1. Flow chart to create invalid block table.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

K9F4008W0A Technical Notes(Continued)

Error in program or erase operation

Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-

ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block

replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Erase Failure

Program Failure

Detection and Countermeasure sequence

Read after Erase --> Block Replacement

Block

Frame

Status Read after Program --> Block Replacement

Program Failure

("1" --> "0")

Single Bit

Block Verify after Program --> Block Replacement

Block Replacement

Block A

1st

{

(n-1)th

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)

* Step3

Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

During Erase operation ;

When the error occurs after an erase operation, prevent future accesses to this bad block

(again by creating a table within the system or other appropriate scheme.)

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

System Interface Using CE don’t-care.

For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal

32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for

voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-

ing would provide significant savings in power consumption.

Figure 3. Program Operation with CE don’t-care.

CLE

CE don’t-care

ALE

80h

Start Add.(3Cycle)

Data Input

10h

I/O0~7

(Max. 60ns)

tCEA

tCS

tCH

tREA

tWP

I/O0~7

out

Timing requirements : If CE is is exerted high during sequential

data-reading, the falling edge of CE to valid data(tCEA) must

be kept greater than 60ns.

Figure 4. Read Operation with CE don’t-care.

CLE

CE don’t-care

Must be held

low during tR.

ALE

R/B

Data Output(sequential)

00h

Start Add.(3Cycle)

I/O0~7

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

* Command Latch Cycle

CLE

tCLS

tCS

tCLH

tCH

tWP

tALS

tALH

ALE

tDH

tDS

Command

I/O0~7

* Address Latch Cycle

tCLS

CLE

tCS

tWC

tWP

tWH

tALH

tALS

ALE

tDH

tDS

A8~A15

A16~A18

I/O0~7

A0~A7

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

* Input Data Latch Cycle

tCLH

CLE

tCH

tWC

tALS

ALE

tWP

tWH

tDH

tDS

I/O0~7

DIN 1

DIN 31

DIN 0

* Burst Read Cycle After Frame Access(CLE=L, WE=H, ALE=L)

tRC

tRHZ*

tREH

tRP

tREA

tRHZ*

tRHZ

I/O0~7

R/B

Dout

tRR

NOTES : Transition is measured±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

* Status Read Cycle

tCLR

CLE

tCLH

tREA

tCH

tWP

tCSTO

tCHZ

tWHR

tDH

tDS

tRHZ

tRSTO

tIR

Status Output

70h

I/O0~7

READ OPERATION(READ ONE FRAME)

CLE

ALE

tCHZ

tWB

tAR2

tRHZ

tRC

tRR

A8 ~ A15 A16 ~ A18

Dout N

Dout N+2 Dout N+3

Dout 32

00h

A0 ~ A7

Dout N+1

I/O0~7

R/B

Column

Address

Row

Address

Busy

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

READ OPERATION(INTERCEPTED BY CE)

CLE

tWB

tCHZ

tAR2

ALE

tRR

A16~A18

Dout N+2 Dout N+3

00h

A0~A7

A8~A15

Dout N Dout N+1

I/O0~7

R/B

Column

Address

Row

Address

Busy

PROGRAM OPERATION

CLE

tWC

ALE

tPROG

tWB

Din

N+1

10h

80h

A0 ~ A7 A8 ~ A15 A16 ~ A18

70h

I/O0

I/O0~7

R/B

Sequential Data Column

Input Command Address

1 up to 32 Byte Data

Serial Input

Read Status

Command

Program

Command

Row

Address

I/O0=0 Successful Program

I/O0=1 Error in Program

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

BLOCK ERASE OPERATION

CLE

tWB

tBERS

ALE

60h

A8~A15 A16~A18

DOh

I/O0~7

R/B

Block

Address

Busy

Auto Block Erase Setup Command

Erase Command

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

DEVICE OPERATION

FRAME READ

Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also ini-

tiated by writing 00h to the command register along with three address cycles. The three cycle address input must be given for

access to each new frame.

The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the data

registers in less than 15ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once

the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying

low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address

within the frame(column 32).

Figure 3. Read Operation

CLE

ALE

R/B

Busy(Seek Time)

Start Add.(3Cycle)

A0~A7 & A8~A18

00h

Data Output(Sequential)

I/O0~7

Seek Time

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

FRAME PROGRAM

The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist

of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming period

in which the loaded data is programmed into the appropriate cells.

The sequential data loading period begins by inputting the frame program setup command(80h), followed by the three cycle address

input and then sequential data loading. The bytes other than those to be programmed do not need to be loaded.

The frame Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the

serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings

necessary for program and verify, thereby freeing the CPU for other tasks. The CPU can detect the completion of a program cycle by

monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset command are

valid while programming is in progress. When the frame Program is complete, the Write Status Bit(I/O0) may be checked. The internal

write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status

command mode until another valid command is written to the command register.

Figure 4. Frame Program Operation

tPROG

R/B

I/O0~7

80h

Address & Data Input

10h

A0~A7 & A8~A18

32 Byte Data

FRAME PROGRAM

While the frame size of the device is 32 Bytes, not all the bytes in a frame have to be programmed at once. The device supports par-

tial frame programming in which a frame may be partially programmed up to 10 separate program operations. The program size in

each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any preset

size. However, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to

"1" data without an erase operation. To perform a partial frame program operation, the user only writes the partial frame data that is

to programmed. Just as in the standard frame program operation, an 80h command is followed by start address data. However, only

the partial program data need be divided when programming a frame in 10 partial program operations.

Figure 5. Example of Dividing a Frame into 10 Partial Program Units

1st partial program start address (00h)

2nd partial program start address (04h)

3rd partial program start address (06h)

9th partial program start address (18h)

10th partial program start address (1Fh)

Single

Frame

FA A2 43 CB 81

28 E0 2A D5 - - - - - - 32 B5 7D 6F AA E1 D7 C0

10th partial frame program data

9th partial frame program data

3rd partial frame program data

2nd partial frame program data

1st partial frame program data

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

BLOCK ERASE

The Erase operation is done 4K Bytes(1 block) at a time. Block address loading is accomplished in two cycles initiated by an Erase

Setup command(60h). Only address A12 to A18 are valid while A8 to A11 is ignored. The Erase Confirm command(D0h) following the

block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command

ensures that memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse

repetition where required.

Figure 6. Block Erase Operation

tBERS

R/B

I/O0~7

60h

Address Input(2Cycle)

Block Add. : A8~A18

D0h

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether

the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs the

contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the

system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does

not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in

Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the

required read command(00h) should be input before serial page read cycle.

Table2. Read Status Register Definition

I/O #

Status

Definition

"0" : Successful Program

I/O0

Program

"1" : Error in Program

I/O1

I/O2

I/O3

I/O4

"0"

Reserved for Future Use

"0"

I/O5

"0"

I/O6

I/O7

Device Operation

Write Protect

"0" : Busy

"0" : Protected

"1" : Ready

"1" : Not Protected

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during the

read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase operations,

the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The device enters

the Read mode after completion of Reset operation as shown Table 3. If the device is already in reset state a new reset command will

not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset com-

mand is not necessarily for normal device operation. Refer to Figure 7 below.

Figure 7. RESET Operation

tRST

R/B

I/O0~7

FFh

Table3. Device Status

After Power-up

After Reset

Operation Mode

Read

K9F4008W0A-TCB0, K9F4008W0A-TIB0

FLASH MEMORY

Figure 9. Read ID Operation

tCLR

CLE

tCEA

tWHR

tAR1

ALE

tREA

I/O0~7

Add. Input(1Cycle)

A0~A7:"0"

Dout(A4H)

90h

Dout(ECh)

Maker code

Device code

Package Dimensions

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a frame program, erase or read seek

completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or

a random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an

open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and cur-

rent drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 10). Its value can be

determined by the following guidance.

ibusy

VCC

Ready Vcc

R/B

2.0V

open drain output

0.8V

Busy

GND

Device

Fig 10 Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 3.3V, Ta = 25°C , C_L= 100pF

381

3.3

Ibusy

300n

290

1.1

1.65

189

200n

100n

0.825

4.2

Rp(ohm)

Rp value guidance

VCC(Max.) - VOL(Max.)

3.2V

Rp(min) =

IOL + SIL

8mA + SIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

Package Dimensions

FLASH MEMORY

DATA PROTECTTION

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL

during power-up and power-down and recovery time of minimum 1ms is required before internal circuit gets ready for any command

sequences as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.

Figure 11. AC Waveforms for Power Transition

~ 2.5V

VCC

High

10ms

Package Dimensions

FLASH MEMORY

PACKAGE DIMENSIONS

44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)

44(40) - TSOP2 - 400F

Unit :mm/Inch

0~8°

0.25

TYP

0.010

#44(40)

#23(21)

0.50

0.020

#22(20)

+0.10

0.15

-0.05

+0.004

-0.002

0.006

18.81

0.741

Max.

18.41±0.10

0.725±0.004

0.10

MAX

0.004

0.805

0.032

0.35±0.10

0.014±0.004

0.80

(

)

0.0315

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K9F4008W0A-TCB0产品参数

型号:	K9F4008W0A-TCB0
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP40/44,.46,32
针数：	44
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
风险等级：	5.82
Is Samacsys：	N
最长访问时间：	50 ns
命令用户界面：	YES
数据轮询：	NO
JESD-30 代码：	R-PDSO-G40
JESD-609代码：	e0
长度：	18.41 mm
内存密度：	4194304 bit
内存集成电路类型：	FLASH
内存宽度：	8
功能数量：	1
部门数/规模：	128
端子数量：	40
字数：	524288 words
字数代码：	512000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	512KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP40/44,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
页面大小：	32 words
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3/5 V
编程电压：	3 V
认证状态：	Not Qualified
就绪/忙碌：	YES
座面最大高度：	1.2 mm
部门规模：	4K
最大待机电流：	0.00005 A
子类别：	Flash Memories
最大压摆率：	0.02 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	NO
类型：	NAND TYPE
宽度：	10.16 mm
Base Number Matches：	1

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