PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
64Kx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
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Synchronous Operation.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
Single 5V±5% Power Supply.
Byte Writable Function.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
The KM718B90 is a 1,179,648 bits Synchronous Static Random
Access Memory designed to support 66MHz of Intel secondary
caches.
It is organized as 65,536 words of 18bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high perfor-
mance cache RAM applications.
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TTL-Level Three-State Output.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
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3.3V I/O Compatible.
52-Pin PLCC Package.
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Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC) inputs.
Subsequent burst addresses are generated internally in the sys-
tem¢s burst sequence and are controlled by the burst address
advance(ADV) input.
FAST ACCESS TIMES
Parameter
Cycle Time
Symbol -8 -9 -10 -11 Unit
tCYC
tCD
15 15 17 20
ns
ns
ns
Clock Access Time
8
5
9
5
10 11
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
Output Enable Access
tOE
5
6
The KM718B90 is implemented with SAMSUNG¢s high perfor-
mance BiCMOS technology and is available in a 52pin PLCC
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Pin Name
A0 - A15
K
Pin Function
Address Inputs
7
6 5 4 3 2 1 52 51 50 49 48 47
Clock
I/O9
I/O10
VCC
I/O8
46
45
44
43
42
41
40
39
38
37
36
35
34
8
9
LW, UW
CS
Write Enable
Chip Selects
I/O7
I/O6
VCC
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VCC
I/O1
I/O0
10
11
12
13
14
15
16
17
18
19
20
VSS
OE
Output Enable
Burst Address Advance
Address Status
Data Inputs/Outputs
+5V Power Supple
Ground
I/O11
I/O12
I/O13
I/O14
VSS
ADV
52-PLCC-SQ
ADSP, ADSC
I/O0~I/O17
VCC
VCC
I/O15
I/O16
I/O17
VSS
21 22 23 24 25 26 27 28 29 30 31 32 33
April 1997
Rev 1.1
- 2 -