KSZ8081MLXIA全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

KSZ8081MLX

10BASE-T/100BASE-TX

Physical Layer Transceiver

Features

Target Applications

• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3

Compliant Ethernet Transceiver

• Game Consoles

• IP Phones

• IP Set-Top Boxes

• IP TVs

• MII Interface Support

• Back-to-Back Mode Support for a 100 Mbps Cop-

per Repeater

• LOM

• MDC/MDIO Management Interface for PHY Reg-

ister Configuration

• Printers

• Programmable Interrupt Output

• LED Outputs for Link and Activity Status Indica-

tion

• On-Chip Termination Resistors for the Differential

Pairs

• Baseline Wander Correction

• HP Auto MDI/MDI-X to Reliably Detect and Cor-

rect Straight-Through and Crossover Cable Con-

nections with Disable and Enable Option

• Auto-Negotiation to Automatically Select the

Highest Link-Up Speed (10/100 Mbps) and

Duplex (Half/Full)

• Power-Down and Power-Saving Modes

• LinkMD^®TDR-Based Cable Diagnostics to Iden-

tify Faulty Copper Cabling

• Parametric NAND Tree Support for Fault Detec-

tion Between Chip I/Os and the Board

• HBM ESD Rating (6 kV)

• Loopback Modes for Diagnostics

• Single 3.3V Power Supply with V_DDI/O Options

for 1.8V, 2.5V, or 3.3V

• Built-In 1.2V Regulator for Core

• Available in 48-pin 7 mm x 7 mm LQFP Package

 2016 Microchip Technology Inc.

DS00002264A-page 1

KSZ8081MLX

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

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DS00002264A-page 2

 2016 Microchip Technology Inc.

KSZ8081MLX

Table of Contents

1.0 Introduction ..................................................................................................................................................................................... 4

2.0 Pin Description and Configuration .................................................................................................................................................. 5

3.0 Functional Description .................................................................................................................................................................. 11

4.0 Register Descriptions .................................................................................................................................................................... 26

5.0 Operational Characteristics ........................................................................................................................................................... 35

6.0 Electrical Characteristics ............................................................................................................................................................... 36

7.0 Timing Diagrams ........................................................................................................................................................................... 38

8.0 Reset Circuit ................................................................................................................................................................................. 46

9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 47

10.0 Reference Clock - Connection and Selection ............................................................................................................................. 48

11.0 Magnetic - Connection and Selection ......................................................................................................................................... 49

12.0 Package Outline .......................................................................................................................................................................... 51

Appendix A: Data Sheet Revision History ........................................................................................................................................... 52

The Microchip Web Site ...................................................................................................................................................................... 53

Customer Change Notification Service ............................................................................................................................................... 53

Customer Support ............................................................................................................................................................................... 53

Product Identification System ............................................................................................................................................................. 54

 2016 Microchip Technology Inc.

DS00002264A-page 3

KSZ8081MLX

1.0

1.1

INTRODUCTION

General Description

The KSZ8081MLX is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and

reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.

The KSZ8081MLX is a highly-integrated, compact solution. It reduces board cost and simplifies board layout by using

on-chip termination resistors for the differential pairs, by integrating a low-noise regulator to supply the 1.2V core, and

by offering 1.8/2.5/3.3V digital I/O interface support.

The KSZ8081MLX offers the Media Independent Interface (MII) for direct connection with MII-compliant Ethernet MAC

processors and switches.

The KSZ8081MLX provides diagnostic features to facilitate system bring-up and debugging in production testing and in

product deployment. Parametric NAND tree support enables fault detection between KSZ8081MLX I/Os and the board.

LinkMD^®TDR-based cable diagnostics identify faulty copper cabling.

The KSZ8081MLX is available in the 48-pin, lead-free LQFP package.

FIGURE 1-1:

SYSTEM BLOCK DIAGRAM

MDC/MDIO

MANAGEMENT

MEDIA TYPES:

10BASE-T

100BASE-TX

MII

RJ-45

CONNECTOR

10/100Mbps

MII MAC

KSZ8081MLX

XO

XI

25MHz

XTAL

22pF

DS00002264A-page 4

 2016 Microchip Technology Inc.

KSZ8081MLX

2.0

PIN DESCRIPTION AND CONFIGURATION

FIGURE 2-1:

48-PIN 7 MM X 7 MM LQFP ASSIGNMENT (TOP VIEW)

48

47

46

45

44

43

42

41

40

39

38

37

1

2

3

4

5

6

7

8

9

GND

TXD1 36

TXD0 35

TXEN 34

TXC 33

GND

VDD_1.2

NC

INTRP /

NAND_TREE#

32

NC

VDD_1.2 31

GND 30

KSZ8081MLX

VDDA_3.3

NC

RXER /

29

ISO

RXC /

B-CAST_OFF

RXM

28

RXDV /

10 RXP

11 TXM

12 TXP

27

CONFIG2

NC 26

VDDIO 25

13

14

15

16

17

18

19

20

21

22

23

24

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DS00002264A-page 5

KSZ8081MLX

TABLE 2-1:

SIGNALS - KSZ8081MLX

Type

Note

2-1

Number

Name

Description

1

2

3

GND

Ground.

1.2V Core V_DD(power supplied by KSZ8081MLX). Decouple with 2.2 µF and

0.1 µF capacitors to ground, and join with Pin 31 by power trace or plane.

4

VDD_!.2

P

5

6

NC

—

No Connect. This pin is not bonded and can be left floating.

7

VDDA_3.3

NC

P

3.3V Analog V_DD.

8

—

No Connect. This pin is not bonded and can be left floating.

Physical Receive or Transmit Signal (– differential).

Physical Receive or Transmit Signal (+ differential).

Physical Transmit or Receive Signal (– differential).

Physical Transmit or Receive Signal (+ differential).

Ground.

9

RXM

RXP

I/O

GND

10

11

12

13

TXM

TXP

GND

Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator

or external clock source is used.

14

15

16

17

18

XO

XI

O

I

Crystal/Oscillator/External Clock Input (25 MHz ±50 ppm).

Set PHY Transmit Output Current. Connect a 6.49 kΩ resistor to ground on

this pin.

REXT

GND

MDIO

GND

Ground.

Ipu/

Opu

Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-

drain, and requires an external 1.0 kΩ pull-up resistor.

Management Interface (MII) Clock Input. This clock pin is synchronous to the

MDIO data pin.

19

20

MDC

Ipu

MII Mode: MII Receive Data Output[3] (Note 2-2)

Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the

de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

RXD3/

PHYAD0

Ipu/O

MII Mode: MII Receive Data Output[2] (Note 2-2)

Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the

de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

RXD2/

PHYAD1

21

22

Ipd/O

MII Mode: MII Receive Data Output[1] (Note 2-2)

Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the

de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

RXD1/

PHYAD2

DS00002264A-page 6

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 2-1:

SIGNALS - KSZ8081MLX (CONTINUED)

Type

Number

Note

Name

2-1

Description

MII Mode: MII Receive Data Output[0] (Note 2-2)

Config. Mode: The pull-up/pull-down value is latched as DUPLEX at the de-

assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

RXD0/

DUPLEX

23

Ipu/O

24

25

26

GND

VDDIO

NC

GND

P

Ground.

3.3V, 2.5V, or 1.8V Digital V_DD

.

—

No Connect. This pin is not bonded and can be left floating.

MII Mode: MII Receive Data Valid Output.

RXDV/

CONFIG2

Config. Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-

assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

27

Ipd/O

MII Mode: MII Receive Clock Output.

RXC/

B-CAST_OFF

Config. Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the

de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

28

29

Ipd/O

MII Mode: MII Receive Error output

Config. Mode: The pull-up/pull-down value is latched as ISOLATE at thede-

assertion of reset See the Strap-In Options - KSZ8081MLX section for details.

RXER/

ISO

30

31

GND

P

Ground.

1.2V Core V_DD(power supplied by KSZ8081MLX). Decouple with 0.1 µF

capacitor to ground, and join with Pin 4 by power trace or plane.

VDD_1.2

Interrupt Output: Programmable interrupt output.

This pin has a weak pull-up, is open drain, and requires an external 1.0 kꢀ

pull-up resistor.

Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the

de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

INTRP/

NAND_Tree#

Ipu/

Opu

32

33

MII Mode: MII Transmit Clock Output.

At the de-assertion of reset, this pin needs to latch in a pull-down value for

normal

operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solu-

tion. It is better having an external pull-down resistor to avoid MAC side pulls

this pin high.

TXC

Ipd/O

34

35

36

37

38

39

TXEN

TXD0

TXD1

GND

I

MII Mode: MII Transmit Enable input.

MII Mode: MII Transmit Data Input[0] (Note 2-3)

MII Mode: MII Transmit Data Input[1] (Note 2-3)

Ground.

I

GND

TXD2

TXD3

I

MII Mode: MII Transmit Data Input[2] (Note 2-3)

MII Mode: MII Transmit Data Input[3] (Note 2-3)

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DS00002264A-page 7

KSZ8081MLX

TABLE 2-1:

SIGNALS - KSZ8081MLX (CONTINUED)

Type

Note

2-1

Number

Name

Description

MII Mode: MII Collision Detect output

COL/

CONFIG0

Config. Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-

assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

40

41

Ipd/O

MII Mode: MII Carrier Sense Output

CRS/

CONFIG1

Config. Mode: The pull-up/pull-down value is latched as CONFIG1 at the de-

assertion of reset. See the Strap-In Options - KSZ8081MLX section for

details.

LED Output: Programmable LED0 Output

Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at

the de-assertion of reset. See the Strap-In Options section for details.

The LED0 pin is programmable using Register 1Fh Bits [5:4], and is defined

as follows:

LED Mode = [00]

Link/Activity

No Link

Link

Pin State

High

LED Definition

OFF

LED0/

NWAYEN

42

Ipu/O

Low

ON

Activity

Toggle

Blinking

LED Mode = [01]

Link

Pin State

High

LED Definition

No Link

Link

OFF

ON

Low

LED Mode = [10], [11] Reserved

LED Output: Programmable LED1 output

Config. Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of

reset. See the Strap-In Options section for details.

The LED1 pin is programmable using Register 1Fh Bits [5:4], and is defined

as follows:

LED Mode = [00]

Speed

Pin State

High

LED Definition

10BASE-T

100BASE-TX

LED Mode = [01]

Activity

OFF

ON

LED1/

SPEED

43

Ipu/O

Low

Pin State

High

LED Definition

OFF

No Activity

Activity

Toggle

Blinking

LED Mode = [10], [11] Reserved

DS00002264A-page 8

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 2-1:

SIGNALS - KSZ8081MLX (CONTINUED)

Type

Number

Note

Name

2-1

Description

No Connect for normal operation, an external pull-up resistor for NAND tree

testing.

44

TEST/NC

Ipd

45

46

47

NC

—

No Connect. This pin is not bonded and can be left floating.

Chip Reset (active low).

RST#

NC

Ipu

—

48

No Connect. This pin is not bonded and can be left floating.

Note 2-1

P = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = Input with internal pull-up (see Electrical Characteristics for value).

Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal

pull-up (see Electrical Characteristics for value).

Note 2-2

Note 2-3

MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0]

presents valid data to the MAC.

MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]

presents valid data from the MAC.

2.1

Strap-In Options

The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins

may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with

the RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7 kꢀ) or pull-

down (1.0 kꢀ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.

TABLE 2-2:

Pin Number

STRAP-IN OPTIONS - KSZ8081MLX

Type

Pin Name

Description

Note 2-4

22

21

PHYAD2

PHYAD1

The PHY address is latched at de-assertion of reset and is configu-

rable to any value from 0 to 7. The default PHY address is 00001.

PHY address 00000 is enabled only if the B-CAST_OFF strap-in pin

is pulled high. PHY address Bits [4:3] are set to 00 by default.

Ipd/O

20

27

PHYAD0

The CONFIG[2:0] strap-in pins are latched at the de-assertion of

reset.

CONFIG2

CONFIG[2:0] Mode

41

40

CONFIG1

CONFIG0

000

110

MII (default)

MII back-to-back

001 – 101,

111

Reserved, not used

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DS00002264A-page 9

KSZ8081MLX

TABLE 2-2:

Pin Number

STRAP-IN OPTIONS - KSZ8081MLX (CONTINUED)

Type

Pin Name

Description

Note 2-4

Isolate Mode:

Pull-up = Enable

29

43

ISO

Ipd/O

Ipu/O

Pull-down (default) = Disable

At the de-assertion of reset, this pin value is latched into Register 0h,

Bit [10].

Speed Mode:

Pull-up (default) = 100 Mbps

Pull-down = 10 Mbps

At the de-assertion of reset, this pin value is latched into Register 0h,

Bit [13] as the speed select, and also is latched into Register 4h

(auto-negotiation advertisement) as the speed capability support.

SPEED

Duplex Mode:

Pull-up (default) = Half-duplex

23

42

28

DUPLEX

NWAYEN

Ipu/O

Pull-down = Full-duplex

At the de-assertion of reset, this pin value is latched into Register 0h,

Bit [8].

Nway Auto-Negotiation Enable:

Pull-up (default) = Enable auto-negotiation

Pull-down = Disable auto-negotiation

At the de-assertion of reset, this pin value is latched into Register 0h,

Bit [12].

Broadcast Off – for PHY Address 0:

Pull-up = PHY Address 0 is set as an unique PHY address

Pull-down (default) = PHY Address 0 is set as a broadcast PHY

address

B-CAST_OFF

NAND_Tree#

Ipd/O

At the de-assertion of reset, this pin value is latched by the chip.

NAND Tree Mode:

Pull-up (default) = Disable

Pull-down = Enable

32

Ipu/Opu

At the de-assertion of reset, this pin value is latched by the chip.

Note 2-4

Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal

pull-up (see Electrical Characteristics for value).

DS00002264A-page 10

 2016 Microchip Technology Inc.

KSZ8081MLX

3.0

FUNCTIONAL DESCRIPTION

The KSZ8081MLX is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3

Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two dif-

ferential pairs and by integrating the regulator to supply the 1.2V core.

On the copper media side, the KSZ8081MLX supports 10BASE-T and 100BASE-TX for transmission and reception of

data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and

correction for straight-through and crossover cables.

On the MAC processor side, the KSZ8081MLX offers the Media Independent Interface (MII) for direct connection with

MII compliant Ethernet MAC processors and switches.

The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.

3.1

10BASE-T/100BASE-TX Transceiver

3.1.1

100BASE-TX TRANSMIT

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized

data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is

set by an external 6.49 kꢀ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX

transmitter.

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust

its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-

pensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit con-

verts MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.

Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.

3.1.3

SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and

baseline wander. The de-scrambler recovers the scrambled signal.

3.1.4

10BASE-T TRANSMIT

The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same mag-

netic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with typical ampli-

tude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental

frequency when driven by an all-ones Manchester-encoded signal.

3.1.5

10BASE-T RECEIVE

On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent

 2016 Microchip Technology Inc.

DS00002264A-page 11

KSZ8081MLX

noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL

locks onto the incoming signal and the KSZ8081MLX decodes a data frame. The receive clock is kept active during idle

periods between data receptions.

3.1.6

SQE AND JABBER FUNCTION (10BASE-T ONLY)

In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed

to test the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the

10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the

10BASE-T transmitter is re-enabled and COL is de-asserted (returns to low).

3.1.7

PLL CLOCK SYNTHESIZER

The KSZ8081MLX generates all internal clocks and all external clocks for system timing from an external 25 MHz crys-

tal, oscillator, or reference clock.

3.1.8

AUTO-NEGOTIATION

The KSZ8081MLX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their

own capabilities with those they received from their link partners. The highest speed and duplex setting that is common

to the two link partners is selected as the mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priority 1: 100BASE-TX, full-duplex

• Priority 2: 100BASE-TX, half-duplex

• Priority 3: 10BASE-T, full-duplex

• Priority 4: 10BASE-T, half-duplex

If auto-negotiation is not supported or the KSZ8081MLX link partner is forced to bypass auto-negotiation, then the

KSZ8081MLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and

allows the KSZ8081MLX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation

advertisement protocol.

Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).

By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or

disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex

is set by Register 0h, Bit [8].

The auto-negotiation link-up process is shown in Figure 3-1.

DS00002264A-page 12

 2016 Microchip Technology Inc.

KSZ8081MLX

FIGURE 3-1:

AUTO-NEGOTIATION FLOW CHART

START AUTO-NEGOTIATION

PARALLEL

OPERATION

FORCE LINK SETTING

YES

NO

ATTEMPT AUTO-

NEGOTIATION

LISTEN FOR 100BASE-TX

IDLES

LISTEN FOR 10BASE-T

LINK PULSES

BYPASS AUTO-NEGOTIATION

AND SET LINK MODE

NO

JOIN FLOW

LINK MODE SET?

YES

LINK MODE SET

3.2

MII Interface

The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface

between MII PHYs and MACs, and has the following key characteristics:

• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi-

cation).

• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 4 bits wide, a nibble.

By default, the KSZ8081MLX is configured to MII mode after it is powered up or hardware reset with the following:

• A 25 MHz crystal connected to XI, XO (Pins 15, 14), or an external 25 MHz clock source (oscillator) connected to

XI.

• The CONFIG[2:0] strapping pins (Pins 27, 41, 40) set to 000 (default setting).

3.2.1

MII SIGNAL DEFINITION

Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.

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KSZ8081MLX

TABLE 3-1:

MII SIGNAL DEFINITION

Direction with

Respect to PHY,

KSZ8081 Signal

MII Signal

Name

Direction with

Respect to MAC

Description

Transmit Clock

(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)

TXC

Output

Input

TXEN

Input

Output

Transmit Enable

TXD[3:0]

Transmit Data[3:0]

Receive Clock

(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)

RXC

Output

Input

RXDV

RXD[3:0]

RXER

CRS

Output

Input

Receive Data Valid

Receive Data[3:0]

Input or not required Receive Error

Input

Carrier Sense

COL

Collision Detection

3.2.1.1

Transmit Clock (TXC)

TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].

TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.2.1.2

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the

first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is

negated before the first TXC following the final nibble of a frame.

TXEN transitions synchronously with respect to TXC.

3.2.1.3

Transmit Data[3:0] (TXD[3:0])

When TXEN is asserted, TXD[3:0] are the data nibbles accepted by the PHY for transmission. TXD[3:0] is 00 to indicate

idle when TXEN is de-asserted.

TXD[3:0] transitions synchronously with respect to TXC.

3.2.1.4

Receive Clock (RXC)

RXC provides the timing reference for RXDV, RXD[3:0], and RXER.

In 10 Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference

clock when the line is idle or the link is down.

In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s

reference clock.

RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.

3.2.1.5

Receive Data Valid (RXDV)

RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].

In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted

until the end of the frame.

In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.

RXDV transitions synchronously with respect to RXC.

3.2.1.6

Receive Data[3:0] (RXD[3:0])

RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]

transfers a nibble of recovered data from the PHY.

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KSZ8081MLX

3.2.1.7

Receive Error (RXER)

RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY

can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being

transferred from the PHY.

RXER transitions synchronously with respect to RXC.

3.2.1.8

Carrier Sense (CRS)

CRS is asserted and de-asserted as follows:

In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the recep-

tion of an end-of-frame (EOF) marker.

In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-asserted

when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE

symbols are received without /T/R.

3.2.1.9

Collision Detection (COL)

COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This

informs the MAC that a collision has occurred during its transmission to the PHY.

COL transitions asynchronously with respect to TXC and RXC.

3.2.2

MII SIGNAL DIAGRAM

The KSZ8081MLX MII pin connections to the MAC are shown in Figure 3-2.

FIGURE 3-2:

KSZ8081MLX MII INTERFACE

'

MII

KSZ8081MLX

ETHERNET MAC

TXC

TXEN

TXD[3:0]

TXD[3:0

]

RXC

RXDV

RXD[3:0]

RXER

RXD[3:0]

RXER

CRS

COL

CRS

COL

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KSZ8081MLX

3.3

Back-to-Back Mode – 100 Mbps Copper Repeater

Two KSZ8081MLX devices can be connected back-to-back to form a 100BASE-TX to 100BASE-TX copper repeater.

FIGURE 3-3:

KSZ8081MLX TO KSZ8081MLX BACK-TO-BACK COPPER REPEATER

RXP/RXM

TXP/TXM

RxD

TxD

KSZ8081MLX

(COPPER MODE)

XI

25MHz

OSC

XI

KSZ8081MLX

(COPPER MODE)

TXP/TXM

RXP/RXM

TxD

RxD

3.3.1

MII BACK-TO-BACK MODE

In MII back-to-back mode, a KSZ8081MLX interfaces with another KSZ8081MLX to provide a complete 100 Mbps cop-

per repeater solution.

The KSZ8081MLX devices are configured to MII back-to-back mode after power-up or reset with the following:

• Strapping pin CONFIG[2:0] (Pins 27, 41, 40) set to 110.

• A common 25 MHz reference clock connected to XI (Pin 15) of both KSZ8081MLX devices.

• MII signals connected as shown in Table 3-2.

TABLE 3-2:

MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER

REPEATER)

KSZ8081MLX (100BASE-TX Copper)

[Device 2]

[Device 1]

Pin Name

Pin Number

Pin Type

Pin Name

Pin Number

Pin Type

RXDV

RXD3

RXD2

RXD1

RXD0

TXEN

TXD3

TXD2

TXD1

TXD0

27

20

21

22

23

34

39

38

36

35

Output

Input

TXEN

TXD3

TXD2

TXD1

TXD0

RXDV

RXD3

RXD2

RXD1

RXD0

34

39

38

36

35

27

20

21

22

23

Input

Output

Input

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KSZ8081MLX

3.4

MII Management (MIIM) Interface

The KSZ8081MLX supports the IEEE 802.3 MII management interface, also known as the Management Data Input/

Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and control

the state of the KSZ8081MLX. An external device with MIIM capability is used to read the PHY status and/or configure

the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows the external con-

troller to communicate with one or more PHY devices.

• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE

802.3 Specification. The additional registers are provided for expanded functionality. See the Register Map section

for details.

As the default, the KSZ8081MLX supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is

defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8081MLX device, or write to mul-

tiple KSZ8081MLX devices simultaneously.

PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF,

Pin 28) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.

The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MLX

device.

The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock.

Table 3-3 shows the MII management frame format for the KSZ8081MLX.

TABLE 3-3:

MII MANAGEMENT FRAME FORMAT FOR THE KSZ8081MLX

Read/

PHY

REG

Start of

Frame

Preamble

Write OP Address Address TA

Code

Data Bits[15:0]

Idle

Bits[4:0] Bits[4:0]

Read

Write

32 1’s

01

10

01

000AA

RRRRR Z0

RRRRR 10

DDDDDDDD_DDDDDDDD

Z

3.5

Interrupt (INTRP)

INTRP (Pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status

update to the KSZ8081MLX PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and disable

the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which

interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.

Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.

The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

3.6

HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable

between the KSZ8081MLX and its link partner. This feature allows the KSZ8081MLX to use either type of cable to con-

nect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs

from the link partner and assigns transmit and receive pairs of the KSZ8081MLX accordingly.

HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, Bit [13]. MDI and MDI-X mode

is selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.

Table 3-4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.

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KSZ8081MLX

TABLE 3-4:

MDI/MDI-X PIN DESCRIPTION

MDI

MDI-X

RJ-45 Pin

Signal

RJ-45 Pin

Signal

1

2

3

6

TX+

TX–

RX+

RX–

1

2

3

6

RX+

RX–

TX+

TX–

3.6.1

STRAIGHT CABLE

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-4 shows

a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).

FIGURE 3-4:

TYPICAL STRAIGHT CABLE CONNECTION

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

1

TRANSMIT PAIR

RECEIVE PAIR

2

3

STRAIGHT

CABLE

3

4

RECEIVE PAIR

5

TRANSMIT PAIR

5

6

7

8

6

7

8

MODULAR CONNECTOR

(RJ-45)

MODULAR CONNECTOR

(RJ-45)

NIC

HUB

(REPEATER OR SWITCH)

3.6.2

CROSSOVER CABLE

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.

Figure 3-5 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

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KSZ8081MLX

FIGURE 3-5:

TYPICAL CROSSOVER CABLE CONNECTION

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

1

2

3

4

5

6

7

8

CROSSOVER

CABLE

RECEIVE PAIR

2

RECEIVE PAIR

3

4

TRANSMIT PAIR

5

TRANSMIT PAIR

6

7

8

MODULAR CONNECTOR

(RJ-45)

HUB

(RJ-45)

HUB

(REPEATER OR SWITCH)

3.7

Loopback Mode

The KSZ8081MLX supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback

• Remote (analog) loopback

3.7.1

LOCAL (DIGITAL) LOOPBACK

This loopback mode checks the MII transmit and receive data paths between the KSZ8081MLX and the external MAC,

and is supported for both speeds (10/100 Mbps) at full-duplex.

The loopback data path is shown in Figure 3-6.

1. The MII MAC transmits frames to the KSZ8081MLX.

2. Frames are wrapped around inside the KSZ8081MLX.

3. The KSZ8081MLX transmits frames back to the MII MAC.

FIGURE 3-6:

LOCAL (DIGITAL) LOOPBACK

KSZ8081MLX

AFE

PCS

MII

MAC

MII

(ANALOG)

(DIGITAL)

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KSZ8081MLX

The following programming action and register settings are used for local loopback mode:

For 10/100 Mbps loopback:

Set Register 0h,

Bit [14] = 1

// Enable local loopback mode

Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed

Bit [12] = 0

Bit [8] = 1

// Disable auto-negotiation

// Select full-duplex mode

3.7.2

REMOTE (ANALOG) LOOPBACK

This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and

receive data paths between the KSZ8081MLX and its link partner, and is supported for 100BASE-TX full-duplex mode

only.

The loopback data path is shown in Figure 3-7.

1. The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8081MLX.

2. Frames are wrapped around inside the KSZ8081MLX.

3. The KSZ8081MLX transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.

FIGURE 3-7:

REMOTE (ANALOG) LOOPBACK

KSZ8081MLX

AFE

(ANALOG)

PCS

(DIGITAL)

MII

RJ-45

CAT-5

(UTP)

100BASE-TX

LINK PARTNER

RJ-45

The following programming steps and register settings are used for remote loopback mode:

1. Set Register 0h,

Bits [13] = 1 // Select 100 Mbps speed

Bit [12] = 0 // Disable auto-negotiation

Bit [8] = 1

// Select full-duplex mode

Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.

2. Set Register 1Fh,

Bit [2] = 1

// Enable remote loopback mode

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KSZ8081MLX

3.8

LinkMD^®Cable Diagnostic

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.

These include open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the

shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides

the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as

a numerical value that can be translated to a cable distance.

LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the

PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the

cable differential pair for testing.

3.8.1

USAGE

The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:

1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].

2. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.

3. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.

4. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:

00 = normal condition (valid test)

01 = open condition detected in cable (valid test)

10 = short condition detected in cable (valid test)

11 = cable diagnostic test failed (invalid test)

The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is

not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal

generated or a signal from another source.

5. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.

The distance to the cable fault can be determined by the following formula:

EQUATION 3-1:

·

DDistance to cable fault in meters = 0.38  Register 1Dh, bits[8:0]

Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.

The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation

that varies significantly from the norm.

3.9

NAND Tree Support

The KSZ8081MLX provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND

tree is a chain of nested NAND gates in which each KSZ8081MLX digital I/O (NAND tree input) pin is an input to one

NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested NAND

gates.

The NAND tree test process includes:

• Enabling NAND tree mode

• Pulling all NAND tree input pins high

• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order

• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input

driven low

Table 3-5 lists the NAND tree pin order.

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KSZ8081MLX

TABLE 3-5:

NAND TREE TEST PIN ORDER FOR KSZ8081MLX

Pin Number

Pin Name

NAND Tree Description

18

19

20

21

22

23

27

28

29

32

33

34

35

36

38

39

42

43

40

41

MDIO

MDC

Input

Output

RXD3

RXD2

RXD1

RXD0

RXDV

RXC

RXER

INTRP

TXC

TXEN

TXD0

TXD1

TXD2

TXD3

LED0

LED1

COL

CRS

3.9.1

NAND TREE I/O TESTING

Use the following procedure to check for faults on the KSZ8081MLX digital I/O pin connections to the board:

1. Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 32) or software (Register 16h,

Bit [5]). Pin 44 TEST/NC has to use a pull-up resistor for normal NAND tree testing.

2. Use board logic to drive all KSZ8081MLX NAND tree input pins high.

3. Use board logic to drive each NAND tree input pin, in KSZ8081MLX NAND tree pin order, as follows:

a) Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low

to indicate that the first pin is connected properly.

b) Leave the first pin (MDIO) low.

c) Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to

high to indicate that the second pin is connected properly.

d) Leave the first pin (MDIO) and the second pin (MDC) low.

e) Toggle the third pin from high to low, and verify that the CRS/CONFIG1 pin switches from high-to-low to indi-

cate that the third pin is connected properly.

f) Continue with this sequence until all KSZ8081MLX NAND tree input pins have been toggled.

Each KSZ8081MLX NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or low-to-high

to indicate a good connection. If the CRS pin fails to toggle when the KSZ8081MLX input pin toggles from high to low,

the input pin has a fault.

3.10 Power Management

The KSZ8081MLX incorporates a number of power-management modes and features that provide methods to consume

less energy. These are discussed in the following sections.

3.10.1

POWER-SAVING MODE

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled

by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon-

nected (no link).

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KSZ8081MLX

In this mode, the KSZ8081MLX shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL

circuits.

By default, power-saving mode is disabled after power-up.

3.10.2

ENERGY-DETECT POWER-DOWN MODE

Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is

unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled

and the cable is disconnected (no link).

EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD

mode) to turn off all KSZ8081MLX transceiver blocks, except for the transmitter and energy-detect circuits.

Power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres-

ence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same low-

power state, with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them.

By default, energy-detect power-down mode is disabled after power-up.

3.10.3

POWER-DOWN MODE

Power-down mode is used to power down the KSZ8081MLX device when it is not in use after power-up. It is enabled

by writing a ‘1’ to Register 0h, Bit [11].

In this mode, the KSZ8081MLX disables all internal functions except the MII management interface. The KSZ8081MLX

exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.

3.10.4

SLOW-OSCILLATOR MODE

Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 15) and select the on-chip slow

oscillator when the KSZ8081MLX device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h, Bit [5].

Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081MLX device in the lowest power

state with all internal functions disabled except the MII management interface. To properly exit this mode and return to

normal PHY operation, use the following programming sequence:

1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].

2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].

3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].

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KSZ8081MLX

3.11 Reference Circuit for Power and Ground Connections

The KSZ8081MLX is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground

connections are shown in Figure 3-8 and Table 3-6 for 3.3V V_DDIO

.

FIGURE 3-8:

KSZ8081MLX POWER AND GROUND CONNECTIONS

FERRITE

BEAD

7

VDDA_3.3

31

0.1μF

22μF

VDD_1.2

`

0.1μF

2.2μF

KSZ8081MLX

3.3V

VDDIO

VDD_1.2

25

4

`

0.1uF

0.1μF

22μF

GND

13 17 24 30

1

2

3

37

TABLE 3-6:

KSZ8081MLX POWER PIN DESCRIPTION

Pin Number

Power Pin

Description

VDD_1.2

VDDA_3.3

VDDIO

4

Connect with Pin 31 by power trace or plane.

Decouple with 2.2 µF and 0.1 µF capacitors to ground.

7

Connect to board’s 3.3V supply through a ferrite bead.

Decouple with 22 µF and 0.1 µF capacitors to ground.

25

31

Connect to board’s 3.3V supply for 3.3V V_DDIO.

Decouple with 22 µF and 0.1 µF capacitors to ground.

VDD_1.2

Connect with Pin 4 by power trace or plane.

Decouple with 0.1 µF capacitor to ground.

3.12 Typical Current/Power Consumption

Table 3-7, Table 3-8, and Table 3-9 show typical values for current consumption by the transceiver (VDDA_3.3) and dig-

ital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081MLX device for the indicated

nominal operating voltages. These current and power consumption values include the transmit driver current and on-

chip regulator current for the 1.2V core.

TABLE 3-7:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

3.3V Transceiver

(VDDA_3.3)

3.3V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

14 mA

30 mA

12 mA

13 mA

11 mA

152 mW

155 mW

82.5 mW

135 mW

10BASE-T Full-duplex @ 100% utilization

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KSZ8081MLX

TABLE 3-7:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

3.3V Transceiver

(VDDA_3.3)

3.3V Digital I/Os

(VDDIO)

Condition

Total Chip Power

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

14 mA

10 mA

79.2 mW

66 mW

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

3.77 mA

1.54 mA

1.75 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

2.59 mA

1.36 mA

1.51 mA

0.45 mA

13.5 mW

5.97 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

TABLE 3-8:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

3.3V Transceiver

(VDDA_3.3)

2.5V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

15 mA

27 mA

15 mA

11 mA

3.55 mA

11 mA

12 mA

10 mA

1.35 mA

140 mW

142 mW

74.5 mW

114 mW

74.5 mW

61.3 mW

15.1 mW

10BASE-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

Software power-down mode (Reg. 0h, Bit [11] =1)

2.29 mA

1.15 mA

1.34 mA

0.29 mA

10.9 mW

4.52 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

TABLE 3-9:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

3.3V Transceiver

(VDDA_3.3)

1.8V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

15 mA

27 mA

15 mA

11 mA

4.05 mA

11 mA

12 mA

9 mA

132 mW

134 mW

65.7 mW

105 mW

65.7 mW

52.5 mW

15.5 mW

10BASE-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

9 mA

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

1.21 mA

Software power-down mode (Reg. 0h, Bit [11] =1)

2.79 mA

1.65 mA

1.21 mA

0.19 mA

11.4 mW

5.79 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

 2016 Microchip Technology Inc.

DS00002264A-page 25

KSZ8081MLX

4.0

REGISTER DESCRIPTIONS

This chapter describes the various control and status registers (CSRs).

4.1

Register Map

TABLE 4-1:

REGISTERS SUPPORTED BY KSZ8081MLX

Register Number (hex)

Description

0h

1h

Basic Control

Basic Status

2h

PHY Identifier 1

3h

PHY Identifier 2

4h

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Auto-Negotiation Next Page

Link Partner Next Page Ability

Reserved

5h

6h

7h

8h

9h

10h

11h

12h - 14h

15h

16h

17h

18h

19h - 1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Digital Reserved Control

AFE Control 1

Reserved

RXER Counter

Operation Mode Strap Override

Operation Mode Strap Status

Expanded Control

Reserved

Interrupt Control/Status

Reserved

LinkMD Control/Status

PHY Control 1

PHY Control 2

4.2

Register Descriptions

TABLE 4-2:

REGISTER DESCRIPTIONS

Mode

Note 4-1

Address Name

Description

Default

Register 0h – Basic Control

1 = Software reset

0.15

0.14

Reset

0 = Normal operation

This bit is self-cleared after a ‘1’ is written to it.

RW/SC

RW

0

1 = Loopback mode

0 = Normal operation

Loopback

Set by the SPEED

strapping pin.

See the Strap-In

Options section for

details.

1 = 100 Mbps

0 = 10 Mbps

This bit is ignored if auto-negotiation is enabled

(Register 0.12 = 1).

0.13

Speed Select

RW

DS00002264A-page 26

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Note 4-1

Address Name

Description

Set by the NWAYEN

strapping pin.

See the Strap-In

Options section for

details.

1 = Enable auto-negotiation process

Auto-Negoti- 0 = Disable auto-negotiation process

ation Enable If enabled, the auto-negotiation result overrides the

settings in Registers 0.13 and 0.8.

0.12

0.11

RW

1 = Power-down mode

0 = Normal operation

If software reset (Register 0.15) is used to exit

power-down mode (Register 0.11 = 1), two soft-

Power-Down

0

ware reset writes (Register 0.15 = 1) are required.

The first write clears power-down mode; the sec-

ond write resets the chip and re-latches the pin

strapping pin values.

Set by the ISO strap-

ping pin.

See the Strap-In

Options section for

details.

1 = Electrical isolation of PHY from MII

0 = Normal operation

0.10

0.9

Isolate

RW

1 = Restart auto-negotiation process

Restart Auto-

Negotiation

0 = Normal operation.

This bit is self-cleared after a ‘1’ is written to it.

RW/SC

0

The inverse of the

DUPLEX strapping

pin value.

See the Strap-In

Options section for

details.

1 = Full-duplex

Duplex Mode

0.8

RW

0 = Half-duplex

1 = Enable COL test

Collision Test

0.7

RW

RO

0

0 = Disable COL test

0.6:0

Reserved

000_0000

Register 1h - Basic Status

1 = T4 capable

0 = Not T4 capable

1.15

1.14

1.13

1.12

100BASE-T4

RO

0

1

100BASE-TX 1 = Capable of 100 Mbps full-duplex

Full-Duplex 0 = Not capable of 100 Mbps full-duplex

100BASE-TX 1 = Capable of 100 Mbps half-duplex

Half-Duplex 0 = Not capable of 100 Mbps half-duplex

10BASE-T

Full-Duplex

1 = Capable of 10 Mbps full-duplex

0 = Not capable of 10 Mbps full-duplex

10BASE-T

1 = Capable of 10 Mbps half-duplex

1.11

1.10:7

1.6

RO

1

Half-Duplex 0 = Not capable of 10 Mbps half-duplex

Reserved

000_0

1

1 = Preamble suppression

0 = Normal preamble

No Preamble

Auto-Negoti-

ation Com-

plete

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

1.5

RO

0

1 = Remote fault

0 = No remote fault

1.4

1.3

Remote Fault

RO/LH

RO

0

1

Auto-Negoti- 1 = Can perform auto-negotiation

ation Ability 0 = Cannot perform auto-negotiation

 2016 Microchip Technology Inc.

DS00002264A-page 27

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

1 = Link is up

0 = Link is down

1.2

1.1

1.0

Link Status

RO/LL

RO/LH

RO

0

1

Jabber

Detect

1 = Jabber detected

0 = Jabber not detected (default is low)

Extended

Capability

1 = Supports extended capability registers

Register 2h - PHY Identifier 1

Assigned to the 3rd through 18th bits of the Organi-

zationally Unique Identifier (OUI). KENDIN Com-

munication’s OUI is 0010A1 (hex).

PHY ID

Number

2.15:0

RO

0022h

Register 3h - PHY Identifier 2

Assigned to the 19th through 24th bits of the Orga-

nizationally Unique Identifier (OUI). KENDIN Com- RO

munication’s OUI is 0010A1 (hex).

PHY ID Num-

ber

3.15:10

0001_01

01_0110

Model Num-

ber

3.9:4

3.3:0

Six-bit manufacturer’s model number

RO

Revision

Number

Indicates silicon

revision.

Four-bit manufacturer’s revision number

Register 4h - Auto-Negotiation Advertisement

1 = Next page capable

4.15

RW

1

Note: Recommend to set this bit to ‘0’.

4.14

4.13

4.12

Reserved

RO

RW

RO

0

1 = Remote fault supported

0 = No remote fault

Remote Fault

Reserved

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

4.11:10

4.9

Pause

RW

RO

00

1 = T4 capable

0 = No T4 capability

100BASE-T4

0

Set by the SPEED

strapping pin.

See the Strap-In

Options section for

details.

100BASE-TX 1 = 100 Mbps full-duplex capable

Full-Duplex 0 = No 100 Mbps full-duplex capability

4.8

4.7

RW

Set by the SPEED

strapping pin.

See the Strap-In

Options section for

details.

100BASE-TX 1 = 100 Mbps half-duplex capable

Half-Duplex 0 = No 100 Mbps half-duplex capability

10BASE-T

Full-Duplex

1 = 10 Mbps full-duplex capable

0 = No 10 Mbps full-duplex capability

4.6

RW

1

10BASE-T

1 = 10 Mbps half-duplex capable

4.5

1

Half-Duplex 0 = No 10 Mbps half-duplex capability

Selector

4.4:0

[00001] = IEEE 802.3

Field

0_0001

DS00002264A-page 28

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Description

Mode

Default

Note 4-1

Address Name

Register 5h - Auto-Negotiation Link Partner Ability

1 = Next page capable

0 = No next page capability

5.15

5.14

RO

0

1 = Link code word received from partner

0 = Link code word not yet received

Acknowledge

1 = Remote fault detected

0 = No remote fault

5.13

5.12

Remote Fault

Reserved

RO

0

Reserved

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

5.11:10

Pause

RO

00

[11] = Asymmetric and symmetric pause

1 = T4 capable

0 = No T4 capability

5.9

100BASE-T4

RO

0

100BASE-TX 1 = 100 Mbps full-duplex capable

Full-Duplex 0 = No 100 Mbps full-duplex capability

5.8

5.7

5.6

5.5

5.4:0

0

100BASE-TX 1 = 100 Mbps half-duplex capable

Half-Duplex 0 = No 100 Mbps half-duplex capability

0

10BASE-T

Full-Duplex

1 = 10 Mbps full-duplex capable

0 = No 10 Mbps full-duplex capability

0

10BASE-T

1 = 10 Mbps half-duplex capable

Half-Duplex 0 = No 10 Mbps half-duplex capability

0

Selector

[00001] = IEEE 802.3

Field

0_0001

Register 6h - Auto-Negotiation Expansion

6.15:5

Reserved

RO

0000_0000_000

0

Parallel

Detection

Fault

1 = Fault detected by parallel detection

0 = No fault detected by parallel detection

6.4

RO/LH

Link Partner

1 = Link partner has next page capability

0 = Link partner does not have next page capability

6.3

RO

0

1 = Local device has next page capability

0 = Local device does not have next page capabil- RO

ity

6.2

6.1

6.0

1

0

Page

Received

1 = New page received

0 = New page not received yet

RO/LH

Link Partner 1 = Link partner has auto-negotiation capability

Auto-Negoti- 0 = Link partner does not have auto-negotiation

RO

ation Able

capability

Register 7h - Auto-Negotiation Next Page

1 = Additional next pages will follow

0 = Last page

7.15

7.14

7.13

RW

RO

RW

0

1

Reserved

Message

Page

1 = Message page

0 = Unformatted page

Acknowl-

edge2

1 = Will comply with message

0 = Cannot comply with message

7.12

RW

0

 2016 Microchip Technology Inc.

DS00002264A-page 29

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

1 = Previous value of the transmitted link code

word equaled logic 1

7.11

Toggle

RO

0

0 = Logic 0

Message

Field

7.10:0

11-bit wide field to encode 2048 messages

RW

000_0000_0001

Register 8h - Link Partner Next Page Ability

1 = Additional next pages will follow

0 = Last page

8.15

8.14

8.13

8.12

RO

0

1 = Successful receipt of link word

0 = No successful receipt of link word

Acknowledge

Message

Page

1 = Message page

0 = Unformatted page

Acknowl-

edge2

1 = Can act on the information

0 = Cannot act on the information

1 = Previous value of transmitted link code word

equal to logic 0

0 = Previous value of transmitted link code word

equal to logic 1

8.11

Toggle

RO

0

Message

Field

8.10:0

11-bit wide field to encode 2048 messages

000_0000_0000

Register 10h – Digital Reserved Control

10.15:5

Reserved

RW

0000_0000_000

1 = Turn PLL off automatically in EDPD mode

0 = Keep PLL on in EDPD mode.

See also Register 18h, Bit [11] for EDPD mode

10.4

PLL Off

0

10.3:0

Reserved

0000

Register 11h – AFE Control 1

11.15:6

Reserved

RW

0000_0000_00

Slow-oscillator mode is used to disconnect the

input reference crystal/clock on the XI pin and

select the on-chip slow oscillator when the

KSZ8081MLX device is not in use after power-up.

1 = Enable

Slow-Oscilla-

tor Mode

Enable

11.5

RW

0

0 = Disable

This bit automatically sets software power-down to

the analog side when enabled.

11.4:0

Reserved

RW

0_0000

0000h

Register 15h – RXER Counter

RXER

Counter

15.15:0

Receive error counter for symbol error frames

RO/SC

Register 16h – Operation Mode Strap Override

0 = Normal operation

1 = Factory test mode

0

Reserved

Factory

Mode

Set by the pull-up /

pull-down value of

TXC (Pin 33).

16.15

If TXC (Pin 33) latches in a pull-up value at the de- RW

assertion of reset, write a ‘0’ to this bit to clear

Reserved Factory Mode.

16.14:11

16.10

Reserved

RW

RO

000_0

0

DS00002264A-page 30

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Note 4-1

Address Name

Description

B-

1 = Override strap-in for B-CAST_OFF

If bit is ‘1’, PHY Address 0 is non-broadcast.

16.9

CAST_OFF

Override

RW

0

16.8

16.7

16.6

16.5

Reserved

RW

0_0

0

MII B-to-B

Override

1 = Override strap-in for MII back-to-back mode

(also set Bit 1 of this register to ‘1’)

Reserved

0

NAND Tree

Override

1 = Override strap-in for NAND tree mode

0

16.4:1

16.0

Reserved

RW

0_000

1

MII Override 1 = Override strap-in for MII mode

Register 17h - Operation Mode Strap Status

[000] = Strap to PHY Address 0

[001] = Strap to PHY Address 1

[010] = Strap to PHY Address 2

[011] = Strap to PHY Address 3

[100] = Strap to PHY Address 4

[101] = Strap to PHY Address 5

[110] = Strap to PHY Address 6

[111] = Strap to PHY Address 7

PHYAD[2:0]

Strap-In Sta-

tus

17.15:13

RO

—

17.12:10

17.9

Reserved

B-

Reserved

RO

—

CAST_OFF 1 = Strap to B-CAST_OFF

Strap-In

Status

If bit is ‘1’, PHY Address 0 is non-broadcast.

17.8

17.7

17.6

17.5

Reserved

RO

—

MII B-to-B

Strap-In

Status

1 = Strap to MII back-to-back mode

Reserved

NAND Tree

Strap-In

Status

1 = Strap to NAND tree mode

17.4:1

17.0

Reserved

RO

—

MII Strap-In

Status

1 = Strap to MII mode

Register 18h - Expanded Control

18.15:12

Reserved

RW

0000

1

Energy-detect power-down mode

1 = Disable

0 = Enable

EDPD

Disabled

18.11

See also Register 10h, Bit [4] for PLL off.

1 = MII output is random latency

100BASE-TX 0 = MII output is fixed latency

18.10

RW

0

Latency

For both settings, all bytes of received preamble

are passed to the MII output.

18.9:7

Reserved

00_0

 2016 Microchip Technology Inc.

DS00002264A-page 31

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

10BASE-T

Preamble

Restore

1 = Restore received preamble to MII output

0 = Remove all seven bytes of preamble before

sending frame (starting with SFD) to MII output

18.6

RW

0

18.5:0

Reserved

RW

00_0000

Register 1Bh – Interrupt Control/Status

Jabber Inter- 1 = Enable jabber interrupt

1B.15

RW

0

rupt Enable

0 = Disable jabber interrupt

Receive

Error Inter-

rupt Enable

1 = Enable receive error interrupt

0 = Disable receive error interrupt

1B.14

Page

Received

Interrupt

Enable

1 = Enable page received interrupt

0 = Disable page received interrupt

1B.13

1B.12

1B.11

RW

0

Parallel

Detect Fault 1 = Enable parallel detect fault interrupt

Interrupt

Enable

0 = Disable parallel detect fault interrupt

Link Partner

Acknowl-

edge Inter-

rupt Enable

1 = Enable link partner acknowledge interrupt

0 = Disable link partner acknowledge interrupt

Link-Down

Interrupt

Enable

1= Enable link-down interrupt

0 = Disable link-down interrupt

1B.10

1B.9

RW

0

RemoteFault

Interrupt

Enable

1 = Enable remote fault interrupt

0 = Disable remote fault interrupt

Link-Up

Interrupt

Enable

1 = Enable link-up interrupt

0 = Disable link-up interrupt

1B.8

1B.7

1B.6

RW

0

Jabber Inter- 1 = Jabber occurred

rupt

RO/SC

0 = Jabber did not occur

Receive

Error Inter-

rupt

1 = Receive error occurred

0 = Receive error did not occur

Page

Receive

Interrupt

1 = Page receive occurred

0 = Page receive did not occur

1B.5

1B.4

RO/SC

0

Parallel

Detect Fault

Interrupt

1 = Parallel detect fault occurred

0 = Parallel detect fault did not occur

Link Partner

Acknowl-

edge Inter-

rupt

1 = Link partner acknowledge occurred

0 = Link partner acknowledge did not occur

1B.3

RO/SC

0

Link-Down

Interrupt

1 = Link-down occurred

0 = Link-down did not occur

1B.2

1B.1

RO/SC

0

RemoteFault 1 = Remote fault occurred

Interrupt 0 = Remote fault did not occur

DS00002264A-page 32

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Note 4-1

Address Name

Description

Link-Up

Interrupt

1 = Link-up occurred

0 = Link-up did not occur

1B.0

RO/SC

0

Register 1Dh – LinkMD Control/Status

1 = Enable cable diagnostic test. After test has

Cable Diag- completed, this bit is self-cleared.

1D.15

nostic Test

Enable

0 = Indicates cable diagnostic test (if enabled) has RW/SC

completed and the status information is valid for

read.

0

[00] = Normal condition

[01] = Open condition has been detected in cable

[10] = Short condition has been detected in cable

[11] = Cable diagnostic test has failed

Cable Diag-

nostic Test

Result

1D.14:13

RO

00

Short Cable 1 = Short cable (<10 meter) has been detected by

1D.12

RO

RW

RO

0

Indicator

LinkMD

1D.11:9

1D.8:0

Reserved

000

Cable Fault

Counter

Distance to fault

0_0000_0000

Register 1Eh – PHY Control 1

1E.15:10

Reserved

RO

0000_00

0

Enable

Pause (Flow

Control)

1 = Flow control capable

0 = No flow control capability

1E.9

1 = Link is up

0 = Link is down

1E.8

Link Status

RO

0

Polarity Sta- 1 = Polarity is reversed

1E.7

1E.6

1E.5

RO

—

0

tus

0 = Polarity is not reversed

Reserved

MDI/MDI-X

State

1 = MDI-X

0 = MDI

—

Energy

Detect

1 = Signal present on receive differential pair

0 = No signal detected on receive differential pair

1E.4

1E.3

RO

RW

0

1 = PHY in isolate mode

0 = PHY in normal operation

PHY Isolate

[000] = Still in auto-negotiation

[001] = 10BASE-T half-duplex

[010] = 100BASE-TX half-duplex

[011] = Reserved

Operation

Mode Indica-

tion

1E.2:0

RO

RW

000

[100] = Reserved

[101] = 10BASE-T full-duplex

[110] = 100BASE-TX full-duplex

[111] = Reserved

Register 1Fh – PHY Control 2

1 = HP Auto MDI/MDI-X mode

0 = Microchip Auto MDI/MDI-X mode

1F.15

HP_MDIX

1

 2016 Microchip Technology Inc.

DS00002264A-page 33

KSZ8081MLX

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

When Auto MDI/MDI-X is disabled,

1 = MDI-X mode

Transmit on RXP, RXM (Pins 10, 9) and Receive

on TXP, TXM (Pins 12, 11)

0 = MDI mode

MDI/MDI-X

Select

1F.14

RW

0

Transmit on TXP, TXM (Pins 12, 11) and Receive

on RXP, RXM (Pins 10, 9)

Pair Swap

Disable

1 = Disable Auto MDI/MDI-X

0 = Enable Auto MDI/MDI-X

1F.13

1F.12

RW

0

Reserved

1 = Force link pass

0 = Normal link operation

This bit bypasses the control logic and allows the

transmitter to send a pattern even if there is no link.

1F.11

Force Link

RW

0

Power Sav- 1 = Enable power saving

1F.10

1F.9

RW

0

ing

0 = Disable power saving

Interrupt

Level

1 = Interrupt pin active high

0 = Interrupt pin active low

Enable Jab- 1 = Enable jabber counter

1F.8

RW

1

0

ber

0 = Disable jabber counter

1F.7:6

Reserved

[00] = LED1: Speed

LED0: Link/Activity

[01] = LED1: Activity

LED0: Link

1F.5:4

LED Mode

RW

00

[10], [11] = Reserved

Disable

Transmitter

1 = Disable transmitter

0 = Enable transmitter

1F.3

1F.2

1F.1

RW

0

Remote

Loopback

1 = Remote (analog) loopback is enabled

0 = Normal mode

Enable SQE 1 = Enable SQE test

Test 0 = Disable SQE test

Disable Data 1 = Disable scrambler

Scrambling 0 = Enable scrambler

1F.0

Note 4-1

RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low.

DS00002264A-page 34

 2016 Microchip Technology Inc.

KSZ8081MLX

5.0

5.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (V_IN)

(V_{DD_1.2}).................................................................................................................................................... –0.5V to +1.8V

(V_DDIO, V_{DDA_3.3})...................................................................................................................................... –0.5V to +5.0V

Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V

Output Voltage (all outputs)....................................................................................................................... –0.5V to +5.0V

Lead Temperature (soldering, 10s)....................................................................................................................... +260°C

Storage Temperature (T_S)...................................................................................................................... –55°C to +150°C

*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating

may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-

ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect

reliability.

5.2

Operating Ratings**

Supply Voltage

(V_{DDIO_3.3}, V_{DDA_3.3}) ........................................................................................................................ +3.135V to +3.465V

(V_{DDIO_2.5}) ........................................................................................................................................ +2.375V to +2.625V

(V_{DDIO_1.8}) ........................................................................................................................................ +1.710V to +1.890V

Ambient Temperature

(T_ACommercial)...........................................................................................................................................0°C to +70°C

(T_AIndustrial) ...........................................................................................................................................–40°C to +85°C

Maximum Junction Temperature (T_Jmax.)........................................................................................................... +125°C

Thermal Resistance (Θ_JA)...................................................................................................................................+76°C/W

Thermal Resistance (Θ_JC) ..................................................................................................................................+15°C/W

**The device is not guaranteed to function outside its operating ratings.

Note:

Do not drive input signals without power supplied to the device.

 2016 Microchip Technology Inc.

DS00002264A-page 35

KSZ8081MLX

6.0

ELECTRICAL CHARACTERISTICS

T_A= 25°C. Specification is for packaged product only.

TABLE 6-1:

Parameters

Supply Current (V_DDIO, V_{DDA_3.3}= 3.3V), Note 6-1

ELECTRICAL CHARACTERISTICS

Symbol

Min.

Typ.

Max.

Units

Note

10BASE-T

I_{DD1_3.3V}

I_{DD2_3.3V}

—

41

47

—

mA

Full-duplex traffic @ 100% utilization

100BASE-TX

Ethernet cable disconnected

(Reg. 18h.11 = 0)

EDPD Mode

I_{DD3_3.3V}

I_{DD4_3.3V}

—

20

4

—

mA

Software power-down

(Reg. 0h.11 = 1)

Power-Down Mode

CMOS Level Inputs

2.4

2.0

1.5

—

V

V_DDIO= 3.3V

Output High Voltage

Output Low Voltage

V_OH

V

_DDIO= 2.5V

_DDIO= 1.8V

—

V

0.4

0.3

10

V

V_DDIO= 3.3V

V_OL

|I_OZ

I_LED

—

V

_DDIO= 2.5V

_DDIO= 1.8V

—

V

Output Tri-State Leakage

LED Output

|

—

µA

Output Drive Current

—

8

—

mA

Each LED pin (LED0, LED1)

V_DDIO= 3.3V

All Pull-Up/Pull-Down Pins (including Strapping Pins)

30

39

48

26

34

53

45

61

99

43

59

99

73

102

178

79

kꢀ

Internal Pull-Up Resistance

pu

pd

V_DDIO= 2.5V

V_DDIO= 1.8V

V_DDIO= 3.3V

Internal Pull-Down

Resistance

113

200

V_DDIO= 2.5V

V_DDIO= 1.8V

100BASE-TX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

100ꢀ termination across differential

V_O

0.95

—

1.05

2

V

Voltage

output

100ꢀ termination across differential

Output Voltage Imbalance

V_IMB

%

output

Rise/Fall Time

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

t_r/t_f

—

3

—

5

0.5

±0.25

5

ns

%

—

0

—

Output Jitter

0.7

—

ns

Peak-to-peak

10BASE-T Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

100ꢀ termination across differential

V_P

2.2

—

2.8

V

Voltage

output

Jitter Added

—

3.5

—

ns

Peak-to-peak

—

Rise/Fall Time

t_r/t_f

25

10BASE-T Receive

Squelch Threshold

Transmitter - Drive Setting

Reference Voltage of I_SET

V_SQ

—

400

—

mV

V

5 MHz square wave

V_SET

0.65

R(I_SET) = 6.49 kꢀ

DS00002264A-page 36

 2016 Microchip Technology Inc.

KSZ8081MLX

TABLE 6-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Parameters

Symbol

Min.

Typ.

Max.

Units

Note

100 Mbps Mode - Industrial Applications Parameters

XI (25 MHz clock input) to MII TXC

(25 MHz clock output) delay, refer-

enced to rising edges of both clocks.

Clock Phase Delay – XI

Input to MII TXC Output

—

15

—

20

25

ns

Link loss detected at receive

differential inputs to PHY signal

indication time for each of the

following:

Link Loss Reaction

(Indication) Time

t_llr

4.4

—

µs

1. For LED mode 01, Link LED output

changes from low (link-up) to high

(link-down).

2. INTRP pin asserts for link-down

status change.

Note 6-1

Current consumption is for the single 3.3V supply KSZ8081MLX device only, and includes the

transmit driver current and the 1.2V supply voltage (V_{DD_1.2}) that are supplied by the KSZ8081MLX.

 2016 Microchip Technology Inc.

DS00002264A-page 37

KSZ8081MLX

7.0

7.1

TIMING DIAGRAMS

MII SQE Timing (10BASE-T)

FIGURE 7-1:

MII SQE TIMING (10BASE-T)

t_WL

TXC

t_WH

t_P

TXEN

COL

t_SQE

t_SQEP

TABLE 7-1:

Parameter

MII SQE TIMING (10BASE-T) PARAMETERS

Description

Min.

Typ.

Max.

Units

t_P

TXC period

—

400

200

2.2

—

ns

µs

t_WL

TXC pulse width low

t_WH

t_SQE

t_SQEP

TXC pulse width high

COL (SQE) delay after TXEN de-asserted

COL (SQE) pulse duration

1.0

DS00002264A-page 38

 2016 Microchip Technology Inc.

KSZ8081MLX

7.2

MII Transmit Timing (10BASE-T)

FIGURE 7-2:

MII TRANSMIT TIMING (10BASE-T)

t_P

t_WL

TXC

t_WH

t_SU2

TXEN

t_HD2

TXD[3:0]

t_SU1

t_HD1

t_CRS1

CRS

t_CRS2

TABLE 7-2:

Parameter

MII TRANSMIT TIMING (10BASE-T) PARAMETERS

Description

Min.

Typ.

Max.

Units

t_P

TXC period

—

120

0

400

200

—

ns

µs

t_WL

TXC pulse width low

t_WH

TXC pulse width high

t_SU1

t_SU2

t_HD1

t_HD2

t_CRS1

t_CRS2

TXD[3:0] setup to rising edge of TXC

TXEN setup to rising edge of TXC

TXD[3:0] hold from rising edge of TXC

TXEN hold from rising edge of TXC

TXEN high to CRS asserted latency

TXEN low to CRS de-asserted latency

—

0

—

600

1.0

 2016 Microchip Technology Inc.

DS00002264A-page 39

KSZ8081MLX

7.3

MII Receive Timing (10BASE-T)

FIGURE 7-3:

MII RECEIVE TIMING (10BASE-T)

CRS

t_RLAT

t_OD

RXDV

RXD[3:0]

RXER

t_P

t_WL

RXC

t_WH

TABLE 7-3:

Parameter

MII RECEIVE TIMING (10BASE-T) PARAMETERS

Description

Min.

Typ.

Max.

Units

t_P

RXC period

—

400

200

205

—

ns

t_WL

t_WH

t_OD

RXC pulse width low

RXC pulse width high

(RXDV, RXD[3:0], RXER) output delay from rising

edge of RXC

ns

µs

t_RLAT

CRS to (RXDV, RXD[3:0]) latency

—

7.2

—

DS00002264A-page 40

 2016 Microchip Technology Inc.

KSZ8081MLX

7.4

MII Transmit Timing (100BASE-TX)

FIGURE 7-4:

MII TRANSMIT TIMING (100BASE-TX)

t_WL

TXC

t_WH

t_HD2

t_SU2

t_P

TXEN

TXD[3:0]

CRS

t_HD1

t_SU1

DATA

IN

t_CRS2

t_CRS1

TABLE 7-4:

Parameter

MII TRANSMIT TIMING (100BASE-TX) PARAMETERS

Description

Min.

Typ.

Max.

Units

t_P

TXC period

—

10

0

40

20

—

72

—

ns

t_WL

TXC pulse width low

t_WH

TXC pulse width high

t_SU1

t_SU2

t_HD1

t_HD2

t_CRS1

t_CRS2

TXD[3:0] setup to rising edge of TXC

TXEN setup to rising edge of TXC

TXD[3:0] hold from rising edge of TXC

TXEN hold from rising edge of TXC

TXEN high to CRS asserted latency

TXEN low to CRS de-asserted latency

0

—

 2016 Microchip Technology Inc.

DS00002264A-page 41

KSZ8081MLX

7.5

MII Receive Timing (100BASE-TX)

FIGURE 7-5:

MII RECEIVE TIMING (100BASE-TX)

CRS

t_RLAT

RXDV

t_OD

RXD[3:0]

RXER

t_WL

RXC

t_WH

t_P

TABLE 7-5:

Parameter

MII RECEIVE TIMING (10BASE-T) PARAMETERS

Description

Min.

Typ.

Max.

Units

t_P

RXC period

—

16

40

20

21

—

25

ns

t_WL

t_WH

t_OD

RXC pulse width low

RXC pulse width high

(RXDV, RXD[3:0], RXER) output delay from rising

edge of RXC

ns

t_RLAT

CRS to (RXDV, RXD[3:0]) latency

—

170

—

DS00002264A-page 42

 2016 Microchip Technology Inc.

KSZ8081MLX

7.6

Auto-Negotiation Timing

FIGURE 7-6:

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING

AUTO -NEGOTIATION

FAST LINK PULSE (FLP) TIMING

FLP

BURST

FLP

BURST

TX+/TX-

t_FLPW

t_BTB

CLOCK

PULSE

DATA

PULSE

CLOCK

PULSE

DATA

PULSE

TX+/TX-

t_PW

t_CTD

t_CTC

TABLE 7-6:

Parameter

AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS

Description

Min.

Typ.

Max.

Units

t_BTB

t_FLPW

t_PW

FLP burst to FLP burst

8

—

16

2

24

—

ms

ns

µs

—

FLP burst width

Clock/Data pulse width

—

100

64

—

t_CTD

t_CTC

—

Clock pulse to data pulse

Clock pulse to clock pulse

Number of clock/data pulses per FLP burst

55.5

111

17

69.5

139

33

128

—

 2016 Microchip Technology Inc.

DS00002264A-page 43

KSZ8081MLX

7.7

MDC/MDIO Timing

FIGURE 7-7:

MDC/MDIO TIMING

t_P

MDC

t_MD1

t_MD2

MDIO

(PHY INPUT)

VALID

DATA

VALID

DATA

t_MD3

MDIO

(PHY OUTPUT)

VALID

DATA

TABLE 7-7:

Parameter

MDC/MDIO TIMING PARAMETERS

Description

Min.

Typ.

Max.

Units

f_c

MDC Clock Frequency

MDC period

—

10

4

2.5

400

—

10

—

MHz

ns

t_P

t_MD1

t_MD2

t_MD3

MDIO (PHY input) setup to rising edge of MDC

ns

MDIO (PHY input) hold from rising edge of MDC

MDIO (PHY output) delay from rising edge of MDC

—

ns

5

222

ns

DS00002264A-page 44

 2016 Microchip Technology Inc.

KSZ8081MLX

7.8

Power-Up/Reset Timing

The KSZ8081MLX reset timing requirement is summarized in Figure 7-8 and Table 7-8.

FIGURE 7-8:

POWER-UP/RESET TIMING

SUPPLY

VOLTAGES

t_SR

t_VR

RST#

t_CS

t_CH

STRAP-IN

VALUE

t_RC

STRAP-IN /

OUTPUT PIN

TABLE 7-8:

POWER-UP/RESET TIMING PARAMETERS

Description

Parameter

Min.

Typ.

Max.

Units

t_VR

t_SR

Supply voltage (V_DDIO, V_{DDA_3.3}) rise time

300

10

—

µs

Stable supply voltage (V_DDIO, V_{DDA_3.3}) to reset

high

ms

t_CS

t_CH

t_RC

Configuration setup time

Configuration hold time

Reset to strap-in pin output

5

6

—

ns

The supply voltage (V_DDIOand V_{DDA_3.3}) power-up waveform should be monotonic. The 300 µs minimum rise time is

from 10% to 90%.

For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are read

and updated at the de-assertion of reset.

After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) inter-

face.

 2016 Microchip Technology Inc.

DS00002264A-page 45

KSZ8081MLX

8.0

RESET CIRCUIT

Figure 8-1 shows a reset circuit recommended for powering up the KSZ8081MLX if reset is triggered by the power sup-

ply.

FIGURE 8-1:

RECOMMENDED RESET CIRCUIT

VDDIO

D1: 1N4148

D1

R 10K

KSZ8081MLX

RST#

C 10μF

Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,

the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2

is used if using different V_DDIObetween the switch and CPU/FPGA, otherwise, the different V_DDIOwill fight each other.

If different V_DDIOhave to use in a special case, a low V_F(<0.3V) diode is required (for example, Vishay’s BAT54,

MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same V_DDIO

voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same

V_DDIOvoltage.

FIGURE 8-2:

RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT

VDDIO

R 10K

D1

KSZ8081MLX

RST#

CPU/FPGA

RST_OUT_n

D2

C 10μF

D1, D2: 1N4148

DS00002264A-page 46

 2016 Microchip Technology Inc.

KSZ8081MLX

9.0

REFERENCE CIRCUITS — LED STRAP-IN PINS

The pull-up, float, and pull-down reference circuits for the LED0/NWAYEN strapping pin are shown in Figure 9-1 for 3.3V

and 2.5V V_DDIO

.

FIGURE 9-1:

REFERENCE CIRCUITS FOR LED STRAPPING PINS

VDDIO = 3.3V, 2.5V

PULL-UP

4.7k

220

KSZ8081MLX

LED PIN

VDDIO = 3.3V, 2.5V

FLOAT

220

KSZ8081MLX

LED PIN

VDDIO = 3.3V, 2.5V

PULL-DOWN

220

KSZ8081MLX

LED PIN

1k

For 1.8V V_DDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the

SPEED and NWAYEN strap-in pins are functional with a 4.7 kꢀ pull-up to 1.8V V_DDIOor float for a value of ‘1’, and with

a 1.0 kꢀ pull-down to ground for a value of ‘0’.

If using RJ45 jacks with integrated LEDs and 1.8V V_DDIO, a level shifting is required from LED 3.3V to 1.8V. For example,

use a bipolar transistor or a level shift device.

 2016 Microchip Technology Inc.

DS00002264A-page 47

KSZ8081MLX

10.0 REFERENCE CLOCK - CONNECTION AND SELECTION

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081MLX.

For the KSZ8081MLX in all operating modes, the reference clock is 25 MHz. The reference clock connections to XI (Pin

15) and XO (Pin 14), and the reference clock selection criteria, are provided in Figure 10-1 and Table 10-1.

FIGURE 10-1:

25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION

22pF

XI

25MHz OSC

50ppꢀ

NC

XO

25MHz XTAL

50ppꢀ

TABLE 10-1: 25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA

Characteristics

Value

Frequency

25 MHz

±50 ppm

40ꢀ

Frequency Tolerance (max.); Note 10-1

Crystal Series Resistance (typ.)

Crystal Load Capacitance (typ.)

16 pF

Note 10-1

±60 ppm for overtemperature crystal.

DS00002264A-page 48

 2016 Microchip Technology Inc.

KSZ8081MLX

11.0 MAGNETIC - CONNECTION AND SELECTION

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs

exceeding FCC requirements.

The KSZ8081MLX design incorporates voltage-mode transmit drivers and on-chip terminations.

With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential

pairs. Therefore, the two transformer center tap pins on the KSZ8081MLX side should not be connected to any power

supply source on the board; instead, the center tap pins should be separated from one another and connected through

separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode voltage is dif-

ferent between transmitting and receiving differential pairs.

Figure 11-1 shows the typical magnetic interface circuit for the KSZ8081MLX.

FIGURE 11-1:

TYPICAL MAGNETIC INTERFACE CIRCUIT

1

TXP

2

3

TXM

RXP

RXM

4

5

6

7

8

4 x 75

1000pF/2kV

(2 x 0.1μF)

SIGNAL GROUND

CHASSIS GROUND

Table 11-1 lists recommended magnetic characteristics.

TABLE 11-1: MAGNETICS SELECTION CRITERIA

Parameter

Value

Test Conditions

Turns Ratio

Open-Circuit Inductance (min.)

Insertion Loss (max.)

HIPOT (min.)

1 CT : 1 CT

350 µH

—

100 mV, 100 kHz, 8 mA

100 kHz to 100 MHz

—

–1.1 dB

1500 V_RMS

Table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side

that can be used with the KSZ8081MLX.

 2016 Microchip Technology Inc.

DS00002264A-page 49

KSZ8081MLX

TABLE 11-2: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS

Manufacturer

Part Number

Temperature Range

Magnetic + RJ-45

Bel Fuse

Delta

S558-5999-U7

SI-46001-F

SI-50170-F

LF8505

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

No

Yes

No

HALO

HFJ11-2450E

TG110-E055N5

LF-H41S-1

H1102

Yes

No

HALO

LANKom

Pulse

No

Pulse

H1260

No

Pulse

HX1188

No

Pulse

J00-0014

Yes

No

Pulse

JX0011D21NL

TLA-6T718A

HB726

TDK

Transpower

Wurth/Midcom

000-7090-37R-LF1

No

DS00002264A-page 50

 2016 Microchip Technology Inc.

KSZ8081MLX

12.0 PACKAGE OUTLINE

FIGURE 12-1:

48-LEAD LQFP 7 MM X 7 MM PACKAGE

Note: For the ꢀost current package drawings, please see the Microchip Packaging Specification located at

http://www.ꢀicrochip.coꢀ/packaging.

 2016 Microchip Technology Inc.

DS00002264A-page 51

KSZ8081MLX

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Section/Figure/Entry

Revision

Correction

Converted Micrel data sheet KSZ8081MLX to

Microchip DS00002264A. Minor text changes

throughout.

DS00002264A (08-30-16)

—

DS00002264A-page 52

 2016 Microchip Technology Inc.

KSZ8081MLX

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://microchip.com/support

 2016 Microchip Technology Inc.

DS00002264A-page 53

KSZ8081MLX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

XX

PART NO.

Device

X

XX

Examples:

X

a)

b)

c)

d)

KSZ8081MLXCA

MII Interface

48-pin LQFP

No Special Attribute

Commercial Temperature

Tray

KSZ8081MLXIA

MII Interface

Media Type

Interface Package

Temperature

Special

Attribute

Device:

KSZ8081

Interface:

Package:

M = MII

48-pin QFN

No Special Attribute

Industrial Temperature

Tray

KSZ8081MLXCA-TR

MII Interface

L = 48-pin LQFP

Special Attribute:

Temperature:

X = None

48-pin QFN

No Special Attribute

Commercial Temperature

Tape & Reel

KSZ8081MLXIA-TR

MII Interface

CA = 0C to +70C (Commercial)

IA = –40C to +85C (Industrial)

48-pin QFN

Media Type:

blank = Tray

TR = Tape & Reel

No Special Attribute

Industrial Temperature

Tape & Reel

DS00002264A-page 54

 2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO

REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-

chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold

harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other

countries.

ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial

Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless

DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-0908-3

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

and India. The Company’s quality system processes and procedures

CERTIFIEDꢀBYꢀDNVꢀ

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TSꢀ16949ꢀ==ꢀ

 2016 Microchip Technology Inc.

DS00002264A-page 55

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Guangzhou

Tel: 86-20-8755-8029

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Sweden - Stockholm

Tel: 46-8-5090-4654

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

Tel: 248-848-4000

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Houston, TX

Tel: 281-894-5983

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Taiwan - Kaohsiung

Tel: 886-7-213-7828

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

06/23/16

DS00002264A-page 56

 2016 Microchip Technology Inc.

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