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KS8721CL

Micrel, Inc.

KS8721CL

3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver

Rev. 1.2

Features

General Description

• Single chip 100BASE-TX/100BASE-FX/10BASE-T

physical layer solution

TheKS8721CLisa10BASE-T,100BASE-TX,and100BASE-

FXphysicallayertransceiverprovidingMII/RMIIinterfacesto

MACsandswitches. Usingauniquemixed-signaldesignthat

extends signaling distance while reducing power consump-

tion, the KS8721CL represents Micrel’s fourth generation

single-port Fast Ethernet PHY.

• 2.5V CMOS design; 2.5/3.3V tolerance on I/O

• 3.3V single power supply with built-in voltage regulator;

Power consumption <340mW (including output driver

current)

• Fully compliant to IEEE 802.3u standard

• Supports MII and Reduced MII (RMII)

• Supports 10BASE-T, 100BASE-TX, and 100BASE-FX

with far-end-fault (FEF) detection

TheKS8721CLcontains10BASE-Tphysicalmediumattach-

ment (PMA), physical medium dependent (PMD), and physi-

cal coding sub-layer (PCS) functions. It also has on-chip

10BASE-T output filtering. This eliminates the need for

external filters and allows a single set of line magnetics to be

used to meet requirements for both 100BASE-TX and

10BASE-T.

• Supports power-down and power-saving modes

• Configurable through MII serial management ports or via

external control pins

• Supports auto-negotiation and manual selection for

10/100Mbps speed and full-/half-duplex modes

• On-chip, built-in, analog front-end filtering for both

100BASE-TX and 10BASE-T

The KS8721CL automatically configures itself for 100Mbps

or10Mbpsandfull-orhalf-duplexoperation,usinganon-chip

auto-negotiation algorithm. It is the ideal physical layer

transceiver for 100BASE-TX/10BASE-T applications.

• Available in Lead-free and Industrial Temperature

packages.

Functional Diagram

4B/5B Encoder

NRZ/NRZI

Scrambler

TXD3

TXD2

TXD1

TXD0

TXER

MLT3 Encoder

10/100

Pulse

TX+

TX-

Parallel/Serial

Transmitter

Shaper

Parallel/Serial

Manchester Encoder

TXC

TXEN

CRS

COL

MII/RMII

Registers

and

Adaptive EQ

Base Line

4B/5B Decoder

Descrambler

Serial/Parallel

RX+

RX-

Clock

MDIO

MDC

Wander Correction

MLT3 Decoder

NRZI/NRZ

Controller

Interface

Recovery

RXD3

RXD2

RXD1

RXD0

RXER

RXDV

RXC

Auto

Negotiation

10BaseT

Receiver

Manchester Decoder

Serial/Parallel

Power

Down or

Saving

LINK

ACTIVITY

FDX

SPD

LED

XI

XO

Driver

PLL

PWRDWN

Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

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Features (continued)

Ordering Information

Part Number Temp. Range

Package

48-Pin LQFP

Lead Finish

Standard

Lead-free

• LED outputs for link, activity, full-/half-duplex, and speed

• Supports back-to-back, FX to TX for media converter

applications

KS8721CL

0°C to +70°C

KSZ8721CL

• Supports MDI/MDI-X auto-crossover

• Commercial temperature range: 0°C to +70°C

• Industrial temperature range: –40°C to +85°C

• Available in 48-pin LQFP

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Revision History

Revision Date

Summary of Changes

0.90

1.0

7/20/04

10/08/04

1/27/05

Created.

Updated series resistance for crystal specification to 40Ω.

1.1

MDIO resistor value changes to 4.7kΩ.

Added note on strapping option pins. Updated bits 1b.0 - 1b.7 to self-clearing.

Updated Electrical characteristics.

Updated reference schematic for strapping option configuration to 3.3V.

Updated bits 1f.4-1f.2 to reserved. Added aditional magnetics to qualified transformer table.

Added reset reference circuit.

1.2

3/16/05

Added RMII timing.

Corrected LED signal references to collision.

Removed KS8721CLI from ordering information.

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Table Of Contents

Pin Description ............................................................................................................................................................ 6

Strapping Option......................................................................................................................................................... 9

Pin Configuration ...................................................................................................................................................... 10

Introduction ........................................................................................................................................................... 11

100BASE-TX Transmit ........................................................................................................................................ 11

100BASE-TX Receive ......................................................................................................................................... 11

PLL Clock Synthesizer......................................................................................................................................... 11

Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 11

10BASE-T Transmit............................................................................................................................................. 11

10BASE-T Receive.............................................................................................................................................. 11

SQE and Jabber Function (10BASE-T only) ....................................................................................................... 11

Auto-Negotiation .................................................................................................................................................. 11

MII Management Interface................................................................................................................................... 12

MII Data Interface ................................................................................................................................................ 12

Transmit Clock ............................................................................................................................................. 12

Receive Clock .............................................................................................................................................. 12

Transmit Enable ........................................................................................................................................... 12

Receive Data Valid ...................................................................................................................................... 12

Error Signals ................................................................................................................................................ 12

Carrier Sense ............................................................................................................................................... 12

Collision........................................................................................................................................................ 13

RMII (Reduced MII) Data Interface ..................................................................................................................... 13

RMII Signal Definition .......................................................................................................................................... 13

Reference Clock .................................................................................................................................................. 13

Carrier Sense/Receive Data Valid ....................................................................................................................... 13

Receive Data ....................................................................................................................................................... 13

Transmit Enable................................................................................................................................................... 13

Transmit Data ...................................................................................................................................................... 14

Collision Detection ............................................................................................................................................... 14

RX_ER

........................................................................................................................................................... 14

RMII AC Characteristics ...................................................................................................................................... 14

Unused RMII Pins................................................................................................................................................ 14

Auto-Crossover (Auto-MDI/MDI-X)...................................................................................................................... 15

Power Management............................................................................................................................................. 16

100BT FX Mode .................................................................................................................................................. 16

Media Converter Operation ................................................................................................................................. 16

Circuit Design Reference for Power Supply ........................................................................................................ 17

Register Map ........................................................................................................................................................... 18

Register 0h: Basic Control .................................................................................................................................. 18

Register 1h: Basic Status ................................................................................................................................... 18

Register 2h: PHY Identifier 1 .............................................................................................................................. 19

Register 3h: PHY Identifier 2 .............................................................................................................................. 19

Register 4h: Auto-Negotiation Advertisement..................................................................................................... 19

Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 19

Register 6h: Auto-Negotiation Expansion ........................................................................................................... 20

Register 7h: Auto-Negotiation Next Page ........................................................................................................... 20

Register 8h: Link Partner Next Page Ability........................................................................................................ 20

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Register Map (continued)

Register 15h: RXER Counter...................................................................................................................................... 21

Register 1bh: Interrupt Control/Status Register.......................................................................................................... 21

Register 1fh: 100BASE-TX PHY Controller ................................................................................................................ 21

Absolute Maximum Ratings........................................................................................................................................ 23

Operating Ratings........................................................................................................................................................ 23

Electrical Characteristics ............................................................................................................................................ 23

Timing Diagrams.......................................................................................................................................................... 25

Selection of Isolation Transformer ............................................................................................................................ 31

Selection of Reference Crystal ................................................................................................................................... 31

Package Information ................................................................................................................................................... 32

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Pin Description

Pin Number

Pin Name

Type⁽¹⁾

Pin Function

1

MDIO

I/O

Management Independent Interface (MII) Data I/O. This pin requires an external

4.7K pull-up resistor.

2

3

MDC

I

MII Clock Input. This pin is synchronous to the MDIO.

RXD3/

Ipd/O

MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.

When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.

RXD [3..0] is invalid when RXDV is de-asserted.

PHYAD

During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See

“Strapping Options” section for details.

4

5

6

7

RXD2/

Ipd/O

P

MII Receive Data Output.

PHYAD2

During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See

“Strapping Options” section for details.

RXD1/

MII Receive Data Output.

PHYAD3

During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See

“Strapping Options” section for details.

RXD0/

MII Receive Data Output.

PHYAD4

During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See

“Strapping Options” section for details.

VDDIO

Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage

regulator. See “Circuit Design Ref. for Power Supply" section for details.

8

9

GND

Ipd/O

Ground.

RXDV/

CRSDV/

MII Receive Data Valid Output.

During reset, the pull-up/pull-down value is latched as PCS_LPBK. See

PCS_LPBK

“Strapping Options” section for details.

10

11

RXC

RXER/ISO

O

Ipd/O

MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.

MII Receive Error Output.

During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See

“Strapping Options” section for details.

12

13

GND

VDDC

GND

P

Ground.

Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply"

section for details.

14

15

TXER

Ipd

I/O

MII Transmit Error Input.

MII Transmit Clock Output.

TXC/

REFCLK

Input for crystal or an external 50MHz clock. When REFCLK pin is used for

REF clock interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave

XO pin unconnected.

16

17

18

TXEN

TXD0

TXD1

Ipd

MII Transmit Enable Input.

MII Transmit Data Input.

Notes:

1. P = Power supply.

GND = Ground.

I = Input.

I/O = Bidirectional.

Ipd = Input w/ internal pull-down.

Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.

Ipu = Input w/ internal pull-up.

Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.

O = Output.

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Pin Number

Pin Name

TXD2

TXD3

Type⁽¹⁾

Ipd

Pin Function

19

20

21

MII Transmit Data Input.

MII Collision Detect Output.

COL/RMII

Ipd/O

During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping

Options” section for details.

22

CRS/

Ipd/O

MII Carrier Sense Output.

RMII_BTB

During reset, the pull-up/pull-down value is latched as RMII back-to-back mode

when RMII mode is selected. See “Strapping Options” section for details.

23

24

GND

VDDIO

GND

P

Ground.

Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of voltage regulator.

See “Circuit Design Ref. for Power Supply” section for details.

25

26

INT#/

Ipu/O

Management Interface (MII) Interrupt Out. Interrupt level set by

Register 1f, bit 9.

PHYAD0

During reset, latched as PHYAD[0]. See “Strapping Options” section for details.

LED0/TEST

PHYAD0

Link LED Output. The external pull-down enable test mode and only used

for the factory test. Active low.

Link

No Link

Link

Pin State

H

L

LED Definition

“Off”

“On”

27

28

LED1/

SPD100/

nFEF

Ipu/O

Speed LED Output. Latched as SPEED (Register 0, bit 13) during power-up/

reset. See “Strapping Options” section for details. Active low.

Speed

10BT

Pin State

H

LED Definition

“Off”

100BT

L

“On”

LED2/

Full-duplex LED Output. Latched as DUPLEX (register 0h, bit 8) during power-up/

reset. See “Strapping DUPLEX Options” section for details. Active low.

Duplex

Half

Pin State

H

LED Definition

“Off”

Full

L

“On”

29

30

LED3/

Ipu/O

Ipu

LED Output. Latched as ANEG_EN (register 0h, bit 12) during power-up/

NWAYEN

reset. See “Strapping Options” section for details.

Activity

Pin State

LED Definition

Activity

–

“Toggle”

PD#

Power Down. 1 = Normal operation, 0 = Power-down. Active low.

Notes:

1. P = Power supply.

GND = Ground.

I = Input.

I/O = Bidirectional.

Ipd = Input w/ internal pull-down.

Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.

Ipu = Input w/ internal pull-up.

Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.

O = Output.

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Pin Number

Pin Name

Type⁽¹⁾

Pin Function

31

VDDRX

P

Analog 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for

details.

32

33

34

RX-

RX+

FXSD/FXEN

I

Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.

Receive Input: Differential receive input pin for 100FX, 100BASE-TX, or 10BASE-T.

Ipd/O

Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is

disable. The default is “0”. See “100BT FX Mode” section for more details.

35

36

37

38

GND

REXT

GND

I

P

Ground.

External resistor (6.49kW ) connects to REXT and GND.

VDDRCV

Analog 2.5V power supply. 2.5V power output of voltage regulator. See “Circuit

Design Ref. for Power Supply” section for details.

39

40

GND

TX-

GND

O

Ground.

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or

10BASE-T.

41

42

TX+

VDDTX

O

P

Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.

Transmitter 2.5V power supply. See “Circuit Design Ref. for Power Supply” section

for details.

43

44

45

46

GND

XO

GND

O

Ground.

XTAL feedback: Used with XI for Xtal application.

Crystal Oscillator Input: Input for a crystal or an external 25MHz clock.

If an oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no-

connect.

XI

I

47

48

VDDPLL

RST#

P

Analog PLL 2.5V power supply. See “Circuit Design Ref. for Power Supply”

section for details.

Ipu

Chip Reset. Active low, minimum of 50µs pulse is required.

Notes:

1. P = Power supply.

GND = Ground.

I = Input.

I/O = Bidirectional.

Ipd = Input w/ internal pull-down.

Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.

Ipu = Input w/ internal pull-up.

Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.

O = Output.

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Strapping Options⁽¹⁾

Pin Number

Pin Name

Type⁽²⁾

Description

6,5,

PHYAD[4:1]/

Ipd/O

PHY Address latched at power-up/reset. The default PHY address is 00001.

4,3

RXD[0:3]

25

PHYAD0/

INT#

Ipu/O

Ipd/O

9⁽³⁾

PCS_LPBK/

Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.

RXDV

11⁽³⁾

21⁽³⁾

22⁽³⁾

ISO/RXER

RMII/COL

Ipd/O

Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.

Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.

RMII_BTB

Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,

CRS

PU = Enable.

27

SPD100/

No FEF/

LED1

Ipu/O

Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)

= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as

the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0

means no Far_End _Fault.)

28

DUPLEX/

LED2

Ipu/O

Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU

(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as

the Duplex support in register 4h.

29

30

NWAYEN/

LED3

Ipu/O

Ipu

Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/

reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.

PD#

Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.

Notes:

1. Strap-in is latched during power-up or reset.

2. Ipu = Input w/ internal pull-up.

Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.

Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.

See “Reference Circuit” section for pull-up/pull-down and float information.

3. Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset. It is

recommended that an external pull-down via 1kΩ resistor be used in their applications to augment the 8721's internal pull-down.

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Pin Configuration

48 47 46 45 44 43 42 4140 39 38 37

36

35

34

GND

MDIO

MDC

1

2

3

RXD3/PHYAD1

RXD2/PHYAD2

RXD1/PHYAD3

RXD0/PHYAD4

VDDIO

FXSD/FXEN

RX+

33

32

31

30

29

28

27

4

RX–

5

VDDRX

6

PD#

7

LED3/NWAYEN

LED2/DUPLEX

LED1/SPD100

LED0/TEST

INT#/PHYAD0

GND

8

9

RXDV/PCS_LPBK

RXC

10

26

25

RXER/ISO

GND

11

12

13 14 15 16 17 18 19 20 21 22 23 24

48-Pin LQFP (LQ)

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Introduction

100BASE-TX Transmit

The100BASE-TXtransmitfunctionperformsparallel-to-serialconversion,NRZ-to-NRZIconversion,andMLT-3encodingand

transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial

bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from

NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49kΩ resistor

for the 1:1 transformer ratio. Its typical rise/fall time of 4ns complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX

driver.

100BASE-TX Receive

The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to-NRZI conversion, data and clock

recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to

compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are

a function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the

variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable

characteristics. It then tunes itself for optimization. This is an ongoing process and can self-adjust for environmental changes

such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to

compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit converts

the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A

synchronized 25MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of RCK25 and is valid for

the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference

clock and both TXC and RXC clocks continue to run.

PLL Clock Synthesizer

The KS8721CL generates 125MHz, 25MHz, and 20MHz clocks for system timing. An internal crystal oscillator circuit provides

the reference clock for the synthesizer.

Scrambler/De-scrambler (100BASE-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic interference

(EMI) and baseline wander.

10BASE-T Transmit

When TXEN (transmit enable) goes high, data encoding and transmission begins. The KS8721CL continues to encode and

transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last transition occurs at

the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated

into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-

emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when

driven by an all-ones, Manchester-encoded signal.

10BASE-T Receive

On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a

PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A

squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noise at the RX+ or

RX- input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal

and the KS8721CL decodes a data frame. This activates the carrier sense (CRS) and RXDV signals and makes the receive

data (RXD) available. The receive clock is maintained active during idle periods in between data reception.

SQE and Jabber Function (10BASE-T only)

In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a test of

the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL goes high if

TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T transmitter is re-

enabled and COL goes low.

Auto-Negotiation

The KS8721CL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It automatically

choosesitsmodeofoperationbyadvertisingitsabilitiesandcomparingthemwiththosereceivedfromitslinkpartnerwhenever

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auto-negotiationisenabled. Itcanalsobeconfiguredtoadvertise100BASE-TXor10BASE-Tineitherfull-orhalf-duplexmode

(please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode.

Duringauto-negotiation,thecontentsofRegister4,codedinfastlinkpulse(FLP),aresenttoitslinkpartnerundertheconditions

of power-on, link-loss, or restart. At the same time, the KS8721CL monitors incoming data to determine its mode of operation.

The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or 100BASE-TX idle is detected.

The operation mode is configured based on the following priority:

Priority 1: 100BASE-TX, full-duplex

Priority 2: 100BASE-TX, half-duplex

Priority 3: 10BASE-T, full-duplex

Priority 4: 10BASE-T, half-duplex

When the KS8721CL receives a burst of FLP from its link partner with three identical link code words (ignoring acknowledge

bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the KS8721CL detects

the second code words, it then configures itself according to the above-mentioned priority. In addition, the KS8721CL also

checksfor100BASE-TXidleor10BASE-TNLPsymbols.Ifeitherisdetected,theKS8721CLautomaticallyconfigurestomatch

the detected operating speed.

MII Management Interface

The KS8721CL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output

(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721CL. The MDIO

interface consists of the following:

• A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).

• A specific protocol that runs across the above-mentioned physical connection that allows one controller to

communicate with multiple KS8721CL devices. Each KS8721CL is assigned an MII address between 0 and 31 by

the PHYAD inputs.

• An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions are

specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.

TheINTPRTpinfunctionsasamanagementdatainterruptintheMII. AnactiveLoworHighinthispinindicatesastatuschange

on the KS8721CL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0]

are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.

MII Data Interface

The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller

(MAC) to the KS8721CL, and for receiving data from the line. Normal data transmission is implemented in 4B nibble mode (4-

bit wide nibbles).

TransmitClock(TXC): ThetransmitclockisnormallygeneratedbytheKS8721CLfromanexternal25MHzreferencesource

at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721CL

normally samples these signals on the rising edge of the TXC.

Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down,

and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the

receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle.

The KS8721CL synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals

at the rising edge of the clock with 10ns setup and hold times.

Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after

the last bit of the packet.

Receive Data Valid: The KS8721CL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will

determine timing changes in the following way:

• For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last

nibble of the data packet.

• For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D” and

remains asserted until the end of the packet.

Error Signals: Whenever the KS8721CL receives an error symbol from the network, it asserts RXER and drives “1110” (4B)

on the RXD pins. When the MAC asserts TXER, the KS8721CL will drive “H” symbols (a Transmit Error defined in the IEEE

802.3 4B/5B code group) out on the line to force signaling errors.

Carrier Sense (CRS): For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier

Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair, causes de-assertion of CRS. The PMA layer will also de-assert

CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-

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asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an

end-of-frame (EOF) marker.

Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721CL

asserts its collision signal, which is asynchronous to any clock.

RMII (Reduced MII) Data Interface

RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet

PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].

This interface has the following characteristics:

• It is capable of supporting 10Mbps and 100Mbps data rates.

• A single clock reference is sourced from the MAC to PHY (or from an external source).

• It provides independent 2-bit wide (di-bit) transmit and receive data paths.

• It uses TTL signal levels compatible with common digital CMOS ASIC processes.

RMII Signal Definition

Direction

Signal Name

(w/respect to the PHY) (w/respect to the MAC)

Use

REF_CLK

Input

Input or Output

Synchronous clock reference for receive, transmit and

control interface

CRS_DV

RXD[1:0]

TX_EN

Output

Input

Output

Carrier Sense/Receive Data Valid

Receive Data

Transmit Enable

TXD[1:0]

Input

Output

Transmit Data

RX_ER

Output

Input (Not Required)

Receive Error

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and

RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as

an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.

Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs

implemented on a single IC.

Carrier Sense/Receive Data Valid (CRS_DV)

CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in

10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the

carrier is detected.

Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains

continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the

first REF_CLK that follows the final di-bit.

ThedataonRXD[1:0]isconsideredvalidonceCRS_DVisasserted.However,sincetheassertionofCRS_DVisasynchronous

relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes place (see “Definition

of RXD[1:0] Behavior”).

Receive Data [1:0] (RXD[1:0])

RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two

bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined

value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle when CRS_DV is de-

asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be

defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion

of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place.

Transmit Enable (TX_EN)

Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is

asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented

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to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transitions synchronously

with respect to REF_CLK.

Transmit Data [1:0] (TXD[1:0])

TransmitDataTXD[1:0]transitionssynchronouslywithrespecttoREF_CLK. WhenTX_ENisasserted, TXD[1:0]areaccepted

for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other

than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on

TXD[1:0] while TX_EN is de-asserted are ignored by the PHY.

Collision Detection

Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably

regenerates the COL signal of the MII by ending TX_EN and CRS_DV.

During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a

self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL signal.

Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since

the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.

RX_ER

The PHY provides RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11–

Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a coding error

or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) is detected

somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to

REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC.

RMII AC Characteristics

Symbol

Parameter

REF_CLK Frequency

REF_CLK Duty Cycle

TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER

Data Hold from REF_CLK

Rising Edge

Min

Typ

50

Max

Unit

MHz

%

ns

35

4

2

65

t_SU

t_H

Unused RMII Pins

Input Pins

TXD[2:3] and TXER are pull-down to GND.

RXD[2:3] and RXC are no connect. Note that the RMII pin needs to be pulled up to enable RMII mode.

Output Pins

RMII Transmit Timing

20ns

REF_CLK

t

1

t

2

TXD[1:0]

TXEN

TXER

Parameter

REF_CLK Frequency

TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge

TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge

Min

Typ

50

Max

Units

MHz

ns

4

2

ns

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RMII Receive Timing

20ns

REF_CLK

RXD[1:0]

RXDV

RXER

t

od

Parameter

REF_CLK Frequency

RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge

Min

Typ

50

Max

Units

MHz

ns

2.8

10

Auto-Crossover (Auto-MDI/MDI-X)

Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The

assignment of pinouts for a 10BASE-T/100BASE-TX crossover function cable is shown below.

This feature eliminates the confusion in applications by allowing the use of both straight and crossover cables. This feature

is controlled by register 1f:13. See the “Register 1fh–100BASE-TX PHY Controller” section for details.

10/100 Ethernet

Media Dependent Interface

1

Transmit Pair

2

Receive Pair

2

Straight

Cable

3

4

Receive Pair

5

Transmit Pair

5

6

7

8

6

7

8

Modular Connector

(RJ-45)

Modular Connector

(RJ-45)

NIC

HUB

(Repeater or Switch)

Figure 1. Straight Through Cable

10/100 Ethernet

Media Dependent Interface

1

Crossover

Cable

Receive Pair

2

Receive Pair

2

3

4

Transmit Pair

5

Transmit Pair

5

6

7

8

6

7

8

Modular Connector (RJ-45)

HUB

Modular Connector (RJ-45)

HUB

(Repeater or Switch)

Figure 2. Crossover Cable

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Power Management

The KS8721CL offers the following modes for power management:

• Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low.

• Power-Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721CL turns off everything

except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8721CL shuts

down most of the internal circuits to save power if there is no link. Power-saving mode is in the most effective state

when auto-negotiation mode is enabled.

100BT FX Mode

Please contact your local field application engineer (FAE) for a reference schematic on fiber connection.

100BT FX mode is activated when FXSD/FXEN is higher than 0.6V (this pin has a default pull down). Under this mode, the

auto-negotiation and auto-MDI-X features are disabled.

In fiber operation, the FXSD pin should connect to the signal detect (SD) output of the fiber module. The internal threshold of

FXSD is around 1/2 V ±50mV (1.25V ±0.05V). Above this level, the fiber signal is considered detected. The operation is

DD

summarized in the following table:

FXSD/FXEN

Condition

Less than 0.6V

100TX mode

Less than 1.25V,

FX mode

but greater than 0.6V

No signal detected

FEF generated

Greater than 1.25

FX mode

Signal detected

Table 1. 100BT FX Mode

To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is

recommended to adjust the SD voltage range.

FEF, repetition of a special pattern which consists of 84-one and 1-zero, is generated under “FX mode with no signal detected.”

The purpose of FEF is to notify the sender of a faulty link. When receiving an FEF, the LINK will go down to indicate a fault,

evenwithfibersignaldetected. ThetransmitterisnotaffectedbyreceivinganFEFandstillsendsoutitsnormaltransmitpattern

from MAC. FEF can be disabled by strapping pin 27 low. Refer to the “Strapping Options” section.

Media Converter Operation

The KS8721CL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode as indicated

in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high). One part is operating

in TX mode and the other is operating in FX mode. Both parts can share a common 50MHz oscillator.

Under this operation, auto-negotiation on the TX side prohibits 10BASE-T link-up. Additional options can be implemented

under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to do this, RXD2

and TXD2 pins need to be connected via inverter. When TXD2 pin is high in both the copper and fiber operation, it is disabled

transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indicate if a line signal is detected.

TXD3 should be tied low and RXD3 allowed to float. Please contact your Micrel FAE for a media converter reference design.

V_CC

21 22

+/-

Rx

RxD

TxD

KS8721CL

Tx +/-

TxC/

Ref_CLK

OSC

50MHz

TxC/

FTx

Ref_CLK

TxD

KS8721CL

(Fiber Mode)

FR

x

RxD

34

21 22

To the SD Pin of the

Fiber Module

V_CC

Figure 3. Fiber Module

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Circuit Design Reference for Power Supply

Micrel’s integrated built-in, voltage regulator technology allows the user to save BOM costs on both existing and future designs

with the use of the new KS8721CL single supply, single port, 10/100 Ethernet PHY.

Ferrite Bead

+2.5VPLL

Ferrite Bead

+2.5VA

+3.3V

+2.5V

10µF

13

47

42

31

38

VDDC

VDDPLL

7

VDDI/O

IN

OUT

Voltage

24

Regulator

VDDI/O

GND

KS8721CL

12 23 35 36 39 43 44

8

Figure 4. Circuit Design

The circuit design in Figure 4 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input power

source and the 2.5V at VDDRCV, pin 38, is the output of the voltage regulator that needs to supply through the rest of the 2.5V

VDD pins via the 2.5V power plane.

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Register Map

Register No.

Description

0h

1h

Basic Control Register

Basic Status Register

2h

PHY Identifier I

3h

PHY Identifier II

4h

5h

6h

7h

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Register

Link Partner Next Page Ability

RXER Counter Register

8h

15h

1bh

1fh

Interrupt Control/Status Register

100BASE-TX PHY Control Register

Address

Name

Description

Mode⁽¹⁾

Default

Register 0h - Basic Control

0.15

0.14

0.13

Reset

Loop-Back

Speed Select (LSB)

1 = software reset. Bit is self-clearing.

1 = loop-back mode; 0 = normal operation.

RW/SC

RW

0

1 = 100Mbps; 0 = 10Mbps.

Set by

Ignored if Auto-Negotiation is enabled (0.12 = 1).

SPD100

0.12

Auto-Negotiation Enable

1 = enable auto-negotiation process (override 0.13 and 0.8). RW

Set by

0 = disable auto-negotiation process.

NWAYEN

0.11

0.10

Power Down

Isolate

1 = power-down mode; 0 = normal operation.

RW

0

1 = electrical isolation of PHY from MII and TX+/TX-.

Set by ISO

0 = normal operation.

0.9

0.8

Restart Auto-Negotiation

Duplex Mode

1 = restart auto-negotiation process.

RW/SC

RW

0

0 = normal operation. Bit is self-clearing.

1 = full-duplex; 0 = half-duplex.

Set by

DUPLEX

0.7

0.6:1

0.0

Collision Test

Reserved

1 = enable COL test; 0 = disable COL test.

RW

RO

R/W

0

Disable

0 = enable transmitter.

1 = disable transmitter.

Transmitter

Register 1h - Basic Status

1.15

1.14

100BASE-T4

1 = T4 capable; 0 = not T4 capable.

RO

0

1

100BASE-TX Full-Duplex 1 = capable of 100BASE-X full-duplex.

0 = not capable of 100BASE-X full-duplex.

1.13

1.12

1.11

100BASE-TX Half-Duplex 1 = capable of 100BASE-X half-duplex.

0 = not capable of 100BASE-X half-duplex.

RO

1

10BASE-T Full-Duplex

1 = 10Mbps with full-duplex.

0 = no 10Mbps with full-duplex capability.

10BASE-T Half-Duplex

1 = 10Mbps with half-duplex.

0 = no 10Mbps with half-duplex capability.

Note:

1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping

Options.”

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Address Name

1.10:7

1.6

Description

Mode⁽¹⁾

RO

Default

Reserved

No Preamble

0

1

0

1 = preamble suppression; 0 = normal preamble.

1.5

Auto-Negotiation Complete 1 = auto-negotiation process completed.

RO

0 = auto-negotiation process not completed.

1.4

1.3

Remote Fault

Auto-Negotiation Ability

1 = remote fault; 0 = no remote fault.

RO/LH

RO

0

1

1 = capable to perform auto-negotiation.

0 = unable to perform auto-negotiation.

1.2

1.1

1.0

Link Status

Jabber Detect

Extended Capability

1 = link is up; 0 = link is down.

1 = jabber detected; 0 = jabber not detected. Default is low. RO/LH

1 = supports extended capabilities registers. RO

RO/LL

0

1

Register 2h - PHY Identifier 1

2.15:0 PHY ID Number

Assigned to the 3rd through 18th bits of the organizationally. RO

unique identifier (OUI). Micrel’s OUI is 0010A1 (hex).

0022h

Register 3h - PHY Identifier 2

3.15:10

PHY ID Number

Assigned to the 19th through 24th bits of the organizationally RO

unique identifier (OUI). Micrel’s OUI is 0010A1 (hex).

000101

3.9:4

3.3:0

Model Number

Revision Number

Six bit manufacturer’s model number.

Four bit manufacturer’s model number.

RO

100001

1001

Register 4h - Auto-Negotiation Advertisement

4.15

4.14

4.13

Remote Fault

1 = next page capable; 0 = no next page capability.

RW

RO

RW

RO

RW

RO

RW

0

1 = remote fault supported; 0 = no remote fault.

4.12 : 11 Reserved

4.10

4.9

Pause

100BASE-T4

1 = pause function supported; 0 = no pause function.

1 = T4 capable; 0 = no T4 capability.

4.8

100BASE-TX Full-Duplex 1 = TX with full-duplex; 0 = no TX full-duplex capability.

Set by

SPD100 &

DUPLEX

4.7

4.6

100BASE-TX

1 = TX capable; 0 = no TX capability.

RW

Set by

SPD100

10BASE-T Full-Duplex

1 = 10Mbps with full-duplex.

Set by

0 = no 10Mbps full-duplex capability.

DUPLEX

4.5

4.4:0

10BASE-T

Selector Field

1 = 10Mbps capable; 0 = no 10Mbps capability.

[00001] = IEEE 802.3.

RW

1

00001

Register 5h - Auto-Negotiation Link Partner Ability

5.15

5.14

1 = next page capable; 0 = no next page capability.

RO

0

1 = link code word received from partner.

0 = link code word not yet received.

5.13

5.12

Remote Fault

Reserved

1 = remote fault detected; 0 = no remote fault.

RO

0

Note:

1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping

Options.”

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Address Name

Description

Mode⁽¹⁾

Default

5.11:10

Pause

5.10 5 .11

RO

0

No PAUSE

0

1

Asymmetric PAUSE (link partner)

1

0

Symmetric PAUSE

1

Symmetric & Asymmetric PAUSE (local device)

5.9

5.8

5.7

5.6

100 BASE-T4

1 = T4 capable; 0 = no T4 capability.

RO

0

100BASE-TX Full-Duplex 1 = TX with full-duplex; 0 = no TX full-duplex capability.

100BASE-TX

10BASE-T Full-Duplex

1 = TX capable; 0 = no TX capability.

1 = 10Mbps with full-duplex.

0 = no 10Mbps full-duplex capability.

5.5

5.4:0

10BASE-T

Selector Field

1 = 10Mbps capable; 0 = no 10Mbps capability.

[00001] = IEEE 802.3.

RO

0

00001

Register 6h - Auto-Negotiation Expansion

6.15:5

6.4

Reserved

Parallel Detection Fault

RO

RO/LH

0

1 = fault detected by parallel detection.

0 = no fault detected by parallel detection.

6.3

6.2

Link Partner Next

Page Able

Next Page Able

1 = link partner has next page capability.

RO

0

1

0 = link partner does not have next page capability.

1 = local device has next page capability.

0 = local device does not have next page capability.

6.1

6.0

Page Received

1 = new page received; 0 = new page not yet received.

RO/LH

RO

0

Link Partner

1 = link partner has auto-negotiation capability.

Auto-Negotiation Able

0 = link partner does not have auto-negotiation capability.

Register 7h - Auto-Negotiation Next Page

7.15

7.14

7.13

7.12

Message Page

Acknowledge 2

1 = additional next page(s) will follow; 0 = last page.

RW

RO

RW

0

1

0

1 = message page; 0 = unformatted page.

1 = will comply with message.

0 = cannot comply with message.

7.11

Toggle

1 = previous value of the transmitted link code word.

RO

0

equaled logic One; 0 = logic Zero.

7.10:0

Message Field

11-bit wide field to encode 2048 messages.

RW

001

Register 8h - Link Partner Next Page Ability

8.15

8.14

1 = additional next page(s) will follow; 0 = last page.

RO

0

1 = successful receipt of link word.

0 = no successful receipt of link word.

8.13

8.12

Message Page

Acknowledge 2

1 = Message Page; 0 = unformatted page.

RO

0

1 = able to act on the information.

0 = not able to act on the information.

8.11

Toggle

1 = previous value of transmitted link code word equal

to logic zero; 0 = previous value of transmitted link code

word equal to logic one.

RO

0

8.10:0

Message Field

RO

0

Note:

1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping

Options.”

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Address Name

Description

Mode⁽¹⁾

Default

Register 15h - RXER Counter

15.15:0

RXER Counter

RX Error counter for the RX_ER in each package.

RO

0000

Register 1bh - Interrupt Control/Status Register

1b.15

1b.14

Jabber Interrupt Enable

1 = Enable jabber interrupt; 0 = Disable jabber interrupt.

RW

0

Receive Error

1 = Enable receive error interrupt.

Interrupt Enable

0 = Disable receive error interrupt.

1b.13

1b.12

1b.11

1b.10

1b.9

1b.8

1b.7

1b.6

1b.5

1b.4

1b.3

1b.2

1b.1

1b.0

Page Received

1 = Enable page received interrupt.

0 = Disable page received interrupt.

RW

0

Interrupt Enable

Parallel Detect Fault

Interrupt Enable

1 = Enable parallel detect fault interrupt.

RW

0 = Disable parallel detect fault interrupt.

Link Partner Acknowledge 1 = Enable link partner acknowledge interrupt.

RW

Interrupt Enable

0 = Disable link partner acknowledge interrupt.

Link Down

1 = Enable link down interrupt.

RW

Interrupt Enable

0 = Disable link down interrupt.

Remote Fault

1 = Enable remote fault interrupt.

0 = Disable remote fault interrupt.

RW

Interrupt Enable

Link Up Interrupt Enable

1 = Enable link up interrupt.

RW

0 = Disable link up interrupt.

Jabber Interrupt

1 = Jabber interrupt occurred.

RO/SC

0 = Jabber interrupt has not occurred.

Receive Error Interrupt

Page Receive Interrupt

1 = Receive error occurred.

0 = Receive error has not occurred.

1 = Page receive occurred.

0 = Page receive has not occurred.

Parallel Detect

Fault Interrupt

1 = Parallel detect fault occurred.

0 = Parallel detect fault has not occurred.

Link Partner

1 = Link partner acknowledge occurred.

Acknowledge Interrupt

0 = Link partner acknowledge has not occurred.

Link Down Interrupt

Remote Fault Interrupt

Link Up Interrupt

1 = Link down occurred.

0 = Link down has not occurred.

1 = Remote fault occurred.

0 = Remote fault has not occurred.

1 = Link up interrupt occurred.

0 = Link up interrupt has not occurred.

Register 1fh - 100BASE-TX PHY Controller

1f.15:14

1f:13

1f.12

Reserved

Pairswap Disable

Energy Detect

1 = Disable MDI/MDI-X; 0 = Enable MDI/MDI-X.

R/W

RO

0

1 = Presence of signal on RX+/RX- analog wire pair.

0 = No signal detected on RX+/RX-.

1f.11

Force Link

1 = Force link pass; 0 = Normal link operation.

This bit bypasses the control logic and allow transmitter

to send pattern even if there is no link.

R/W

0

1f.10

1f.9

1f.8

1f.7

Power-Saving

Interrupt Level

Enable Jabber

1 = Enable power-saving; 0 = Disable.

1 = Interrupt pin active high; 0 = Active low.

1 = Enable jabber counter; 0 = Disable.

RW

1

0

1

0

Auto-Negotiation Complete 1 = Auto-Negotiation complete; 0 = Not complete.

Note:

1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping

Options.”

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Address Name

Description

Mode⁽¹⁾

Default

1f.6

Enable Pause

1 = Flow control capable; 0 = No flow control.

RO

0

(Flow-Control Result)

PHY Isolate

1f.5

1 = PHY in isolate mode; 0 = Not isolated.

RO

0

1f.4:2

Reserved

1f.1

1f.0

Enable SQE Test

Disable Data Scrambling 1 = Disable scrambler; 0 = Enable.

1 = Enable SQE test; 0 = Disable.

RW

0

Note:

1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping

Options.”

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Micrel, Inc.

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

Supply Voltage

Storage Temperature (T ) ....................... –55°C to +150°C

S

(V

, V

V

)........+2.5V

Supply Referenced to GND ........................ –0.5V to +4.0V

DD_PLL DD_TX DD_RXC DD_RCV, DDC

) ...................................................................+3.3V

DDIO

All Pins ........................................................ –0.5V to +4.0V

Ambient Temperature (T )

A

Important: Please read the Notes at the bottom of the

page.

Commercial ................................................ 0°C to +70°C

Industrial................................................. –40°C to +85°C

(3)

Package Thermal Resistance

LQFP (θ )

JA

No Airflow ...................................................83.56°C/W

Electrical Characteristics⁽⁴⁾

V_DD= 3.3V ±10%

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

Total Supply Current (including TX output driver current)⁽⁵⁾

I_DD1

I_DD2

Normal 100BASE-TX

Including 43mA output current

Including 103mA output current

116

151

mA

Normal 10BASE-T (independent of

utilization)

I_DD3

I_DD5

Power-Saving Mode 1

Power-Down Mode

Auto-Negotiation is Enable

47

4

mA

TTL Inputs

V_IH

Input High Voltage

1/2V (I/O)

V

DD

+0.2

V_IL

I_IN

Input Low Voltage

Input Current

0.8

10

V

µA

V_IN= GND ~ V_DD

–10

TTL Outputs

V_OH

Output High Voltage

I_OH= –4mA

I_OL= 4mA

1/2V (I/O)

+^D0^D.6

V

V_OL

Output Low Voltage

Output Tri-State Leakage

0.4

10

V

µA

|I_OZ

|

100BASE-TX Receive

R_IN

RX+/RX– Differential Input

8

kΩ

Resistance

Propagation Delay

From magnetics to RDTX

50

110

ns

100BASE-TX Transmit (measured differentially after 1:1 transformer)

V_O

V_IMB

t_r, t_t

Peak Differential Output Voltage

Output Voltage Imbalance

50Ω from each output to V_DD

0.95

1.05

2

V

%

Rise/Fall Time

3

0

5

ns

Rise/Fall Time Imbalance

0.5

ns

Notes:

1. Exceeding the absolute maximum rating(s) may cause permanent damage to the device. Operating at maximum conditions for extended periods may

affect device reliability.

2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground

to V ).

DD

3. No HS (heat spreader) in package.

4. Specification for packaged product only.

5. There is 100% data transmission in full-duplex mode and a minimum IPG with a 130-meter cable.

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Symbol

Parameter

Condition

Min

Typ

Max

Units

100BASE-TX Transmit (measured differentially after 1:1 transformer)

Duty Cycle Distortion

Overshoot

±0.5

5

ns

%

V_SET

Reference Voltage of ISET

Propagation Delay

Jitters

0.75

45

0.7

V

ns

ns_(pp)

from TDTX to magentics

60

1.4

10BASE-TX Receive

R_IN

RX+/RX– Differential

8

kW

mV

Input Resistance

V_SQ

Squelch Threshold

5MHz square wave

400

10BASE-TX Transmit (measured differentially after 1:1 transformer)

V_P

Peak Differential Output Voltage

Jitters Added

50W from each output to V_DD

2.2

2.8

±3.5

V

ns

t_r, t_t

Rise/Fall Time

25

ns

Clock Outputs

X1, X2

RXC₁₀₀

RXC₁₀

Crystal Oscillator

25

2.5

3.0

25

2.5

1.8

MHZ

ns_(pp)

MHZ

ns_(pp)

Receive Clock, 100TX

Receive Clock, 10T

Receive Clock Jitters

Transmit Clock, 100TX

Transmit Clock, 10T

Transmit Clock Jitters

TXC₁₀₀

TXC₁₀

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Timing Diagrams

TXC

t_HD2

t_HD1

t_SU2

t_SU1

TXEN

TXD[3:0]

CRS

t_CRS1

t_CRS2

Valid

Data

TXP/TXM

t_LAT

SQE Timing

TXC

TXEN

COL

t_SQE

t_SQEP

Figure 5. 10BASE-T MII Transmit Timing

Symbol

t_SU1

t_SU2

Parameter

TXD [3:0] Set-Up to TXC High

TXEN Set-Up to TXC High

TXD [3:0] Hold After TXC High

Min

10

0

Typ

Max

Units

ns

t_HD1

ns

t_HD2

TXEN Hold After TXC High

0

ns

t_CRS1

t_CRS2

t_LAT

t_SQE

t_SQEP

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

TXEN High to TXP/TXM Output (TX Latency)

COL (SQE) Delay After TXEN De-Asserted

COL (SQE) Pulse Duration

4

8

4

2.5

1.0

BT⁽¹⁾

BT

µs

Table 2. 10BASE-T MII Transmit Timing Parameters

Note:

1. BT = bit time.

1BT = 10ns @ 100BT.

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TXC

t_HD2

t_HD1

t_SU2

TXEN

t_SU1

TXD[3:0],

TXER

Data

In

t_CRS2

t_CRS1

t_LAT

CRS

Symbol

Out

TX+/TX-

Figure 6. 100BASE-T MII Transmit Timing

Symbol

t_SU1

t_SU2

t_HD1

t_HD2

Parameter

TXD [3:0] Set-Up to TXC High

TXEN Set-Up to TXC High

TXD [3:0] Hold After TXC High

TXER Hold After TXC High

Min

10

0

Typ

Max

Units

ns

0

t_HD3

TXEN Hold After TXC High

0

ns

t_CRS1

t_CRS2

t_LAT

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

TXEN High to TX+/TX– Output (TX Latency)

4

9

BT

Table 3. 100BASE-T MII Transmit Timing Parameters

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Start of

Stream

End of

RX+/RX-

CRS

Stream

t_CRS1

t_CRS2

RXDV

t_RLAT

t_HD

RXD[3:0]

RXER

t_SU

t_WH

^WLt_P

RXC

t

Figure 7. 100BASE-T MII Receive Timing

Symbol

t_P

Parameter

RXC Period

Min

Typ

40

Max

Units

ns

t_WL

t_WH

RXC Pulse Width

20

ns

t_SU

t_HD

t_RLAT

t_CRS1

t_CRS2

RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC

RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC

CRS to RXD Latency, 4B or 5B Aligned

“Start of Stream” to CSR Asserted

“End of Stream” to CSR De-Asserted

20

6

ns

BT

ns

106

154

138

186

Table 4. 100BASE-T MII Receive Timing Parameters

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FLP

Burst

TX+/TX-

t_FLPW

t_BTB

Clock

Pulse

Data

Clock

Pulse

Data

Pulse

t_PW

t_CTD

t_CTC

Figure 8. Auto-Negotiation/Fast Link Pulse Timing

Symbol

t_BTB

t_FLPW

t_PW

Parameter

FLP Burst to FLP Burst

FLP Burst Width

Clock/Data Pulse Width

Min

8

Typ

16

2

Max

24

Units

ms

ns

100

t_CTD

Clock Pulse to Data Pulse

69

µs

t_CTC

Clock Pulse to Clock Pulse

136

µs

Number of Clock/Data Pulses per Burst

17

33

µs

Table 5. Auto-Negotiation/Fast Link Pulse Timing

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t_P

MDC

t_MD1

t_MD2

MDI O

Valid

Data

(Into Chip)

Data

t_MD3

MDI O

Valid

Data

(Out ofChip)

Figure 9. Serial Management Interface Timing

Symbol

t_P

Parameter

MDC Period

Min

Typ

400

Max

Units

ns

t_MD1

t_MD2

t_MD3

MDIO Set-Up to MDC (MDIO as Input)

MDIO Hold After MDC (MDIO as Input)

MDC to MDIO Valid (MDIO as Output)

10

ns

222

Table 6. Serial Management Interface Timing

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Supply

Voltage

tsr

RST_N

Strap-In

Value

Figure 10. Reset Timing

Symbol

t_sr

Parameter

Stable Supply Voltages to Reset High

Min

50

Typ

Max

Units

µs

Table 7. Reset Timing Parameters

Reference Circuit for Strapping Option Configuration

Figure 10 shows the reference circuit for strapping option pins.

Reset Circuit Diagram

Micrel recommendeds the following discrete reset circuit as shown in Figure 11 when powering up the KS8721CL device. For

theapplicationwheretheresetcircuitsignalcomesfromanotherdevice(e.g.,CPU,FPGA,etc),werecommendtheresetcircuit

as shown in Figure 12.

VCC

R

D1

10k

KS8721CL

RST

CPU/FPGA

RST_OUT_n

D2

C

10µF

D1, D2: 1N4148

Figure 11. Recommended Reset Circuit.

VCC

D1: 1N4148

R

D1

10k

KS8721CL

RST

C

10µF

Figure 12. Recommended Circuit for Interfacing with CPU/FPGA Reset

Atpower-on-reset, R, C, andD1providethenecessaryramprisetimetoresettheMicreldevice. TheresetoutfromCPU/FPGA

provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage.

At worst case, the both VDD core and VDDIO voltages should come up at the same time.

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3.3V

220Ω

Pull-Up

10kΩ

LED pin

KS8721CL

3.3V

220Ω

Pull-down

LED pin

KS8721CL

1kΩ

Reference circuits for unmanaged programming through LED ports

Figure 13. Reference Circuit, Strapping Option Pins

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Selection of Isolation Transformer⁽¹⁾

One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode

chokeisrecommendedforexceedingFCCrequirements. Thefollowingtablegivesrecommendedtransformercharacteristics.

Characteristic

Value

Test Condition

Turns Ratio

1 CT : 1 CT

350µH

0.4µH

12pF

0.9Ω

1.0dB

1500Vrms

Open-Circuit Inductance (min.)

Leakage Inductance (max.)

Inter-Winding Capacitance (max.)

D.C. Resistance (max.)

Insertion Loss (max.)

HIPOT (min.)

100mV, 100kHz, 8mA

1MHz (min.)

0MHz to 65MHz

Note:

1. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can

be compensated or by increasing the line drive current by means of reducing the ISET resistor value. Please select the transformer that supports

auto-MDI/MDI-X.

Selection of Reference Crystal

An oscillator or crystal with the following typical characteristics is recommended.

Characteristic

Frequency

Frequency Tolerance (max.)

Load Capacitance (max.)

Series Resistance (max.)

Value

25.00000

±100

20

Units

MHz

ppm

pF

40

Ω

Single Port

Number

of Ports

Magnetic Manufacturer

Part Number

H1102

S558-5999-U7

PH163112

HB726

LF8505

LF-H41S

Auto-MDI-X

Yes

Pulse

Bel Fuse

YCL

Transpower

Delta

LanKom

1

Yes

Intergrated Transformers

Pulse

J0011D21

J00-0061

Yes

1

Pulse

Table 8. Qualified Transformer List

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Package Information

48-pin LQFP (LQ)

MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s

use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

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