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    产品型号L6565D的Datasheet PDF文件预览

    L6565  
    QUASI-RESONANT SMPS CONTROLLER  
    ■ QUASI-RESONANT (QR) ZERO-VOLTAGE-  
    SWITCHING (ZVS) TOPOLOGY  
    ■ LINE FEED FORWARD TO DELIVER  
    CONSTANT POWER vs. MAINS CHANGE  
    ■ FREQUENCY FOLDBACK FOR OPTIMUM  
    STANDBY EFFICIENCY  
    ■ PULSE-BY-PULSE & HICCUP-MODE OCP  
    ■ ULTRA-LOW START-UP (< 70µA) AND  
    QUIESCENT CURRENT (< 3.5mA)  
    ■ DISABLE FUNCTION (ON/OFF CONTROL)  
    DIP8(Minidip)  
    ORDERING NUMBERS:  
    SO-8  
    ■ 1% PRECISION (@ T = 25°C) INTERNAL  
    j
    L6565N  
    L6565D  
    REFERENCE VOLTAGE  
    ■ ±400mA TOTEM POLE GATE DRIVER WITH  
    UVLO PULL-DOWN  
    ■ BLUE ANGEL, ENERGY STAR, ENERGY  
    DESCRIPTION  
    2000 COMPLIANT  
    The L6565 is a current-mode primary controller IC,  
    specifically designed to build offline Quasi-resonant  
    ZVS (Zero Voltage Switching at switch turn-on) fly-  
    back converters.  
    APPLICATIONS  
    ■ TV/MONITOR SMPS  
    ■ AC-DC ADAPTERS/CHARGERS  
    ■ DIGITAL CONSUMER  
    Quasi-resonant operation is achieved by means of a  
    transformer demagnetization sensing input that trig-  
    gers MOSFET's turn-on.  
    ■ PRINTERS, FAX MACHINES,  
    PHOTOCOPIERS AND SCANNERS  
    BLOCK DIAGRAM  
    COMP  
    VFF  
    3
    2
    1
    INV  
    -
    LINE VOLTAGE  
    FEEDFORWARD  
    +
    40K  
    4
    2.5V  
    CS  
    2 V  
    VOLTAGE  
    5pF  
    -
    +
    -
    +
    REGULATOR  
    8
    VCC  
    Hiccup-mode  
    OCP  
    CC  
    V
    INTERNAL  
    SUPPLY  
    R
    S
    Q
    Q
    20V  
    R1  
    7
    GD  
    +
    UVLO  
    DRIVER  
    -
    R2  
    REF2  
    V
    Blanking  
    START  
    Starter  
    STOP  
    ZERO CURRENT  
    DETECTOR  
    +
    -
    STARTER  
    BLANKING  
    2.1V  
    1.6V  
    Hiccup-mode  
    OCP  
    DISABLE  
    6
    5
    GND  
    ZCD  
    January 2003  
    1/17  
    L6565  
    DESCRIPTION (continued)  
    Converter's power capability variations with the mains voltage are compensated by line voltage feedforward.  
    At light load the device features a special function that automatically lowers the operating frequency still main-  
    taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this  
    feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com-  
    pliant.  
    The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref-  
    erence voltage for primary regulation and an effective two-level overcurrent protection.  
    PIN CONNECTION (Top view, Minidip and SO8)  
    INV  
    COMP  
    VFF  
    Vcc  
    GD  
    GND  
    ZCD  
    CS  
    PIN DESCRIPTION  
    N°  
    Name  
    Function  
    1
    INV  
    Inverting input of the error amplifier. The information on the output voltage is fed into the pin  
    through either a resistor divider (primary regulation) or an optocoupler (secondary feedback).  
    This pin can be grounded in some secondary feedback schemes (see pin 2).  
    2
    3
    4
    COMP Output of the error amplifier. Typically, a compensation network is placed between this pin and  
    the INV pin to achieve stability and good dynamic performance of the voltage control loop. With  
    secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by  
    modulating the current sunk from the pin (with the INV pin grounded).  
    VFF  
    Line voltage feedforward. The information on the converter’s input voltage is fed into the pin  
    through a resistor divider and is used to change the setpoint of the pulse-by-pulse current  
    limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will  
    be grounded and the current limitation setpoint will be maximum.  
    CS  
    Input to the PWM comparator. The primary current is sensed through a resistor, the resulting  
    voltage is applied to this pin and compared with an internal reference to determine MOSFET’s  
    turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current  
    limitation setpoint, depending on the voltage at pin VFF. If the signal at the pin CS exceeds 2 V,  
    the gate driver will be disabled (Hiccup-mode OCP).  
    5
    ZCD  
    Transformer’s demagnetization sensing input for Quasi-Resonant operation. Alternately,  
    synchronization input for an external signal. A negative-going edge triggers MOSFET’s turn-on.  
    The trigger circuit is blanked for a minimum of 3.5 µs after MOSFET turn-off, for safe operation  
    under short circuit conditions and frequency foldback. If the pin is grounded the IC will be  
    disabled.  
    6
    7
    GND  
    GD  
    Ground. Current return for both the signal part of the IC and the gate driver.  
    Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s  
    with a peak current of 400 mA (source and sink).  
    8
    Vcc  
    Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is  
    connected between this pin and ground. A resistor connected from this pin to the converter’s  
    input bulk capacitor will be typically used to start up the device.  
    2/17  
    L6565  
    THERMAL DATA  
    Symbol  
    Parameter  
    Max. Thermal Resistance, Junction-to-ambient  
    SO8  
    Minidip  
    Unit  
    R
    150  
    100  
    °C/W  
    th j-amb  
    ABSOLUTE MAXIMUM RATINGS  
    Symbol  
    Pin  
    Parameter  
    Value  
    Unit  
    I
    8
    I
    + I  
    Z
    30  
    mA  
    Vcc  
    CC  
    I
    7
    Output Totem Pole Peak Current (2 µs)  
    ±700  
    mA  
    V
    GD  
    INV, COMP,  
    VFF, CS  
    1, 2, 3 4 Analog Inputs & Outputs  
    -0.3 to 7  
    I
    5
    Zero Current Detector  
    50 (source)  
    -10 (sink)  
    mA  
    W
    ZCD  
    P
    Power Dissipation @T  
    = 50°C  
    (Minidip)  
    (SO8)  
    1
    0.65  
    amb  
    tot  
    T
    Junction Temperature Operating range  
    Storage Temperature  
    -40 to 150  
    -55 to 150  
    °C  
    °C  
    j
    T
    stg  
    ELECTRICAL CHARACTERISTCS  
    (T = -25 to 125°C, V = 12V, C = 1nF; unless otherwise specified)  
    j
    CC  
    o
    Symbol  
    Parameter  
    Test Condition  
    Min.  
    Typ.  
    Max.  
    Unit  
    SUPPLY VOLTAGE  
    V
    Operating range  
    Turn-on threshold  
    Turn-off threshold  
    Hysteresis  
    After turn-on  
    10.3  
    12.5  
    8.7  
    18  
    14.5  
    10.3  
    4.3  
    cc  
    V
    V
    13.5  
    9.5  
    4
    V
    V
    V
    V
    CCOn  
    CCOff  
    Hys  
    3.65  
    18  
    V
    Zener Voltage  
    I
    = 25 mA  
    cc  
    20  
    22  
    Z
    SUPPLY CURRENT  
    Start-up Current  
    Quiescent Current  
    I
    45  
    2.3  
    3.5  
    70  
    µA  
    Before turn-on, V  
    After turn-on  
    @ 70 kHz  
    = 12V  
    start-up  
    CC  
    I
    q
    3.5  
    5
    mA  
    mA  
    mA  
    mA  
    I
    Operating Supply Current  
    Quiescent Current  
    CC  
    I
    I
    During Hiccup-mode OCP  
    1.6  
    3.5  
    2.1  
    q
    q
    Quiescent Current  
    V
    < V , V >V  
    CCOff  
    1.4  
    ZCD  
    VFF  
    DIS  
    CC  
    LINE FEEDFORWARD  
    I
    Input Bias Current  
    Operating Range  
    Gain  
    V
    = 0 to 3 V  
    -1  
    µA  
    V
    VFF  
    V
    0 to 3  
    0.16  
    VFF  
    K
    V
    = 1.5V, V = 4V  
    COMP  
    VFF  
    ERROR AMPLIFIER  
    V
    Voltage Feedback Input  
    Threshold  
    T
    = 25°C  
    2.465  
    2.44  
    2.5  
    2.535  
    V
    INV  
    amb  
    12V < V < 18V  
    2.56  
    5
    CC  
    Line Regulation  
    Vcc = 12 to 18V  
    2
    mV  
    µA  
    I
    Input Bias Current  
    -0.1  
    -1  
    INV  
    3/17  
    L6565  
    ELECTRICAL CHARACTERISTCS (continued)  
    (T = -25 to 125°C, V = 12V, C = 1nF; unless otherwise specified)  
    j
    CC  
    Parameter  
    Voltage Gain  
    o
    Symbol  
    Test Condition  
    Open loop  
    Min.  
    Typ.  
    80  
    Max.  
    Unit  
    dB  
    G
    V
    60  
    GB  
    Gain-Bandwidth Product  
    Source Current  
    1
    MHz  
    mA  
    I
    V
    V
    = 4V, V  
    = 4V, V  
    = 2.4 V  
    = 2.6 V  
    -2  
    2.5  
    5
    -3.5  
    -5  
    COMP  
    COMP  
    COMP  
    INV  
    Sink Current  
    4.5  
    5.5  
    mA  
    V
    INV  
    V
    Upper Clamp Voltage  
    Lower Clamp Voltage  
    I
    I
    = 0.5 mA  
    SOURCE  
    COMP  
    = 0.5 mA  
    2.25  
    2.55  
    V
    SINK  
    CURRENT SENSE COMPARATOR  
    I
    Input Bias Current  
    V
    = 0  
    -0.05  
    200  
    1.4  
    0.7  
    0
    -1  
    450  
    1.5  
    µA  
    ns  
    V
    CS  
    CS  
    t
    Delay to Output  
    d(H-L)  
    V
    Current Sense Reference Clamp  
    V
    = Upper clamp, V  
    = 0V  
    = 1.5V  
    1.28  
    0.62  
    CSx  
    COMP  
    COMP  
    VFF  
    V
    = Upper clamp, V  
    0.78  
    0.2  
    VFF  
    V
    COMP  
    = Upper clamp, V  
    = 3V  
    VFF  
    V
    CSdis  
    Hiccup-mode OCP level  
    1.85  
    2.0  
    2.2  
    V
    ZERO CURRENT DETECTOR/ SYNCHRONIZATION  
    V
    Upper Clamp Voltage  
    Lower Clamp Voltage  
    I
    I
    = 3mA  
    4.7  
    0.3  
    5.2  
    0.65  
    2.1  
    6.1  
    1
    V
    V
    V
    ZCDH  
    ZCD  
    ZCD  
    V
    = - 3mA  
    ZCDL  
    ZCDA  
    (1)  
    V
    Arming Voltage  
    (positive-going edge)  
    V
    Triggering Voltage  
    (negative-going edge)  
    1.6  
    2
    V
    ZCDT  
    ZCDb  
    I
    Input Bias Current  
    V
    = 1 to 4.5 V  
    µA  
    mA  
    mA  
    mV  
    µA  
    ZCD  
    I
    Source Current Capability  
    Sink Current Capability  
    Disable Threshold  
    -3  
    3
    -10  
    10  
    ZCDsrc  
    I
    ZCDsnk  
    V
    150  
    -70  
    200  
    -150  
    3.5  
    250  
    -230  
    DIS  
    I
    Restart Current After Disable  
    V
    V
    V
    < V  
    , Vcc > Vcc  
    DIS off  
    ZCDr  
    ZCD  
    T
    Blanking time after pin 7 high-to-  
    low transition  
    ≥ 3.2 V  
    µs  
    BLANK  
    COMP  
    COMP  
    = 2.5 V  
    18  
    START TIMER  
    Start Timer period  
    GATE DRIVER  
    t
    250  
    400  
    550  
    µs  
    V
    START  
    V
    OL  
    Dropout Voltage  
    I
    I
    I
    I
    = 200mA  
    = 20mA  
    1.2  
    0.7  
    2
    1
    GDsource  
    GDsource  
    V
    OH  
    = 200mA  
    = 20mA  
    2
    V
    GDsink  
    GDsink  
    0.3  
    100  
    100  
    t
    Current Fall Time  
    Current Rise Time  
    40  
    40  
    10  
    ns  
    ns  
    f
    t
    r
    I
    I
    sink current  
    Vcc = 4 V, V  
    GD  
    = 1 V  
    5
    mA  
    GDoff  
    GD  
    (1) Parameters guaranteed by design, not tested in production.  
    4/17  
    L6565  
    Figure 1. Supply current vs. Supply voltage  
    Figure 4. Line feedforward characteristics  
    ICC  
    (mA)  
    Vcsx [V]  
    1.5  
    Upper clamp  
    10  
    5
    5.0 V  
    1
    0.5  
    0
    1
    4.5 V  
    4.0 V  
    3.5 V  
    0.5  
    0.1  
    0.05  
    CL = 1nF  
    f = 70KHz  
    TA = 25°C  
    3.0 V  
    0.01  
    0.005  
    0
    VCOMP = 2.5V  
    0
    0.5  
    1
    1.5  
    2
    2.5  
    3
    3.5  
    VVFF [V]  
    CC  
    V
    0
    5
    10  
    15  
    20  
    (V)  
    Figure 2. Start-up & UVLO vs. Temperature  
    Figure 5. Pin 2 (COMP) V-I characteristics  
    VCOMP [V]  
    14  
    6
    V
    CC-ON  
    Tj = 25 °C  
    Vpin1 = 0  
    (V)  
    13  
    5
    4
    12  
    11  
    10  
    3
    Regulation  
    range  
    2
    1
    0
    V
    CC-OFF  
    (V)  
    9
    0
    1
    2
    3
    4
    -25  
    0
    25  
    50  
    75  
    100  
    125  
    ICOMP [mA]  
    T (°C)  
    Figure 3. Feedback reference vs. Temperature  
    Figure 6. ZCD blanking time vs. COMP voltage  
    D94IN048A  
    V
    (V)  
    REF  
    TBLANK [µs]  
    20  
    Tj = 25 °C  
    15  
    10  
    5
    2.50  
    2.48  
    2.46  
    0
    2
    3
    4
    5
    6
    T (°C)  
    VCOMP [V]  
    -50  
    0
    50  
    100  
    5/17  
    L6565  
    Figure 7. Gate-drive output saturation  
    Figure 10. Zener voltage at Vcc pin vs. Tj  
    Vpin7 [V]  
    Vz [V]  
    22  
    2.5  
    Tj = 25 °C  
    Vcc = 14.5 V  
    SINK  
    2
    21  
    20  
    1.5  
    1
    19  
    0.5  
    0
    18  
    -50  
    0
    50  
    100  
    150  
    0
    100  
    200  
    300  
    400  
    500  
    Tj [°C]  
    IGD [mA]  
    Figure 11. Start-up timer period vs. Tj  
    Figure 8. Gate-drive output saturation  
    Vpin7 [V]  
    TSTART [µs]  
    450  
    Vcc - 0.5  
    Vcc=12V  
    Tj = 25 °C  
    Vcc = 14.5 V  
    SOURCE  
    Vcc - 0.5  
    400  
    350  
    Vcc - 1.0  
    Vcc - 1.5  
    300  
    Vcc - 2.0  
    Vcc - 0.5  
    250  
    0
    100  
    200  
    300  
    400  
    500  
    -50  
    0
    50  
    100  
    150  
    IGD [mA]  
    Tj [°C]  
    Figure 9. IC consumption vs. temperature  
    Icc [mA]  
    5
    Vcc=12V  
    2
    Quiescent  
    1
    0.5  
    0.2  
    0.1  
    Before Start-up  
    0.05  
    0.02  
    -50  
    0
    50  
    100  
    150  
    Tj [°C]  
    6/17  
    L6565  
    APPLICATION INFORMATION  
    Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transform-  
    er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the  
    transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple  
    interface, just one resistor.  
    Variable frequency operation - as a result of different operating conditions in terms of input voltage and output  
    current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis-  
    continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op-  
    eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).  
    Detailed Device Description  
    Internal Supply Block (see fig. 12)  
    A linear voltage regulator supplied by V (pin 8) generates an internal 7V rail used for supplying the entire IC,  
    cc  
    except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise  
    internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed-  
    back technique.  
    In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the  
    chip as long as the Vcc voltage is high enough to ensure a reliable operation.  
    Figure 12. L6565 internal supply block  
    +Vin  
    Vcc  
    8
    -
    +
    UVLO  
    LIN.  
    REG.  
    REF.  
    2.5V  
    7V bus  
    7/17  
    L6565  
    Zero Current Detection and Triggering Block (see fig. 13):  
    The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling be-  
    low 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must  
    be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding  
    2.1 V.  
    This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the  
    ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can  
    be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the  
    device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g.  
    monitor SMPS).  
    The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals:  
    first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the  
    ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).  
    Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks  
    COMP  
    INV  
    -
    L6565  
    E/A  
    +
    2.5V  
    +Vin  
    ZCD  
    R
    5
    PWM  
    to line  
    FFWD  
    BLANKING  
    TIME  
    5.2V  
    ZCD  
    blanking  
    START  
    7
    R
    S
    GD  
    -
    Q
    DRIVER  
    MONO  
    STABLE  
    +
    1.6V  
    2.1V  
    starter STOP  
    Q
    STARTER  
    -
    DISABLE  
    0.2V  
    0.3V  
    +
    A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin.  
    This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET.  
    To minimize the external interface with the synchronization source (either the auxiliary winding or an external  
    clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal dia-  
    gram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at  
    one V above ground. The interface will then be made by just one resistor that has to limit the current sourced  
    BE  
    by and sunk from the pin within the rated capability of the internal clamps.  
    Disable Block (see fig. 13):  
    The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the de-  
    vice will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal  
    lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation,  
    the pull-down on the pin must be released.  
    Frequency Foldback Block (see fig. 13):  
    To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation,  
    8/17  
    L6565  
    the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of  
    the ZCD circuit as mentioned before. The duration of the blanking time (3.5µs min.) is a function of the error  
    amplifier output VCOMP, as shown in the diagram of figure 6.  
    If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking  
    time of 3.5µs, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated  
    schematically in figure 14.  
    Figure 14. Frequency foldback: ringing cycle skipping as the load is progressively reduced  
    VDS  
    VDS  
    VDS  
    t
    t
    t
    TFW  
    TV  
    TBLANKmin  
    TBLANK  
    TBLANK  
    Pin = Pin'  
    (limit condition)  
    Pin = Pin'' < Pin'  
    Pin = Pin''' < Pin''  
    In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that  
    the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for  
    cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compen-  
    sated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is  
    no appreciable effect on the performance of the converter or on its output voltage.  
    Figure 15. Frequency Foldback: qualitative  
    frequency dependence on power  
    throughput  
    Voltage Feedforward block (see fig. 17b):  
    The power that QR flyback converters with a fixed  
    overcurrent setpoint (like fixed-frequency systems)  
    are able to deliver changes with the input voltage  
    considerably. With wide-range mains, at maximum  
    line it can be more than twice the value at minimum  
    line, as shown by the upper curve in the diagram of  
    figure 16. The L6565 has the Line Feedforward func-  
    tion available to solve this issue.  
    fsw  
    without frequency foldback  
    Vin fixed  
    Figure 16. Typical power capability change vs.  
    input voltage in ZVS QR flyback  
    converters  
    with frequency foldback  
    2.5  
    system not  
    Pin  
    compensated  
    2
    Further load reductions involve lower values for  
    VCOMP, which increases the blanking time. There-  
    fore, more and more ringing cycles will be skipped.  
    When the load is low enough, so many ringing cycles  
    need to be skipped that their amplitude becomes  
    very small and they can no longer trigger the ZCD cir-  
    cuit. In that case the internal starter of the IC will be  
    activated, resulting in burst-mode operation: a series  
    of few switching cycles spaced out by long periods  
    where the MOSFET is in OFF state.  
    1.5  
    1
    system optimally  
    compensated  
    0.5  
    1
    1.5  
    2
    2.5  
    3
    3.5  
    4
    Vin  
    Vinmin  
    9/17  
    L6565  
    It acts on the clamp level of the control voltage V , that is on the overcurrent setpoint, so that it is a function  
    csx  
    of the converter's input voltage sensed through a dedicated pin (#3, VFF): the higher the input voltage, the lower  
    the setpoint. This is illustrated in the diagram of figure 17a that shows the relationship between the voltage at  
    the pin VFF and V (with the error amplifier saturated high in the attempt of keeping output voltage regulation).  
    csx  
    The schematic in figure 17b shows also how the function is included in the control loop. With a proper selection  
    of the external divider R1-R2 it is possible to achieve the optimum compensation described by the lower curve  
    in the diagram of figure 16.  
    In applications where this function is not wanted, e.g. because of a narrow input voltage range, the VFF pin can  
    be simply grounded, thus saving the resistor divider. The overcurrent setpoint will be then fixed at the maximum  
    value of about 1.4V (1.5V max.).  
    Line Feedforward is also beneficial to other characteristics of quasi-resonant converters: it improves their input  
    ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage.  
    Figure 17. a) Overcurrent setpoint vs. VFF voltage; b) Line Feedforward function block  
    Vcsx [V]  
    1.5  
    VCOMP = Upper clamp  
    1
    a)  
    0.5  
    0
    0
    0.5  
    1
    1.5  
    2
    2.5  
    3
    3.5  
    VVFF [V]  
    +Vin  
    R1  
    R2  
    Rs  
    COMP  
    2
    VFF  
    CS  
    4
    ZCD  
    5
    starter STOP  
    3
    STARTER  
    S
    ZCD  
    +
    7
    INV  
    VOLTAGE  
    FEED  
    FORWARD  
    Q
    R
    DRIVER  
    1
    -
    GD  
    PWM  
    -
    E/A  
    (reset-dominant)  
    +
    +
    DISABLE  
    2.5V  
    Hiccup  
    -
    2 V  
    L6565  
    b)  
    10/17  
    L6565  
    Error Amplifier Block (see fig. 17b):  
    The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the volt-  
    age generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regu-  
    lation (see "Application Ideas", fig. 24). With secondary feedback (typically using a TL431 at the secondary side  
    and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the  
    E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Ap-  
    plication Ideas", fig. 23).  
    The E/A output is used typically for control loop compensation, realized with an RC network connected to the  
    inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded  
    optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Ap-  
    plication Ideas").  
    Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b):  
    The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the  
    programming signal delivered by the feedforward block, determines the exact time when the external MOSFET  
    is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the  
    noise generated ("double-pulse suppression").  
    A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin  
    exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on  
    the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is  
    the Vcc voltage must fall below the UVLO threshold.  
    When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming  
    from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time.  
    Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior  
    will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.  
    Gate Driver (see fig. 18):  
    A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a  
    high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to  
    prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative.  
    An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the ex-  
    ternal MOSFET cannot be turned on accidentally (e.g. at power-on).  
    Figure 18. Gate driver with UVLO pull-down  
    Vcc  
    8
    L6565  
    7
    GD  
    Q
    DRIVER  
    UVLO  
    6
    GND  
    11/17  
    L6565  
    TYPICAL APPLICATIONS  
    Figure 19. 50W Wide Range Mains SMPS for 14" TV  
    C6 4700pF/ 4KV  
    C7 4700pF/ 4KV  
    F1  
    2A fuse  
    NTC1  
    16R  
    D1  
    1N4148  
    R9  
    R10  
    4.7M  
    4.7M  
    C22  
    100 pF  
    C25  
    1nF  
    B1 2KBP04M  
    3
    Vin  
    88 to  
    264 Vac  
    T1  
    C23  
    100nF  
    C24  
    100nF  
    105 V  
    0.35 A  
    C1  
    R1  
    75k  
    C8  
    C2  
    N1  
    L1  
    15mH  
    µ
    150  
    F
    R5  
    100 k  
    8.2 nF 180 pF  
    250 V 630V  
    C9  
    400 V  
    D5  
    BYT01-400  
    C26  
    1nF  
    µ
    220  
    F
    R2  
    75k  
    8
    160 V  
    1
    D6  
    BYW98-100  
    N2  
    N3  
    14 V  
    1 A  
    D3 STTA106  
    9
    R8 22  
    4
    C10  
    µ
    470  
    F
    C4  
    47µF  
    25V  
    25 V  
    D4  
    1N4148  
    Naux  
    10  
    R20 22 k  
    5
    ZCD  
    5
    7
    R6 100  
    D2  
    GD  
    R3  
    3 M  
    Q1  
    STP7NB80FI  
    IC1  
    R7 10 1N4148  
    CS  
    L6565  
    4
    8
    VFF  
    Vcc  
    3
    R11  
    0.47  
    2
    1
    6
    C27  
    220nF  
    +5 V  
    50 mA  
    COMP  
    INV  
    GND  
    1
    2
    IC4  
    R4  
    C3  
    1 nF  
    L7805  
    16 K  
    C12  
    100 µF 25V  
    R15  
    1.8 k  
    C11  
    47 µF  
    25V  
    3
    IC3 PC817  
    R12  
    47 k  
    1
    4
    R14  
    1.5 k  
    DZ1  
    15 V  
    R13  
    3.3 k  
    P1  
    100 k  
    C5  
    2.2 nF  
    R16  
    220 k  
    3
    2
    R18  
    150 k  
    C13  
    100 nF  
    1
    TRANSFORMER SPECS:  
    CORE: ETD29x16x10, N67 material or equivalent  
    1 mm air gap for a primary inductance of 285 µH  
    N1: 48 T (24T+24T series connected), 2xAWG28 ( 0.37 mm)  
    N2: 31 T, AWG28  
    3
    IC2 TL431  
    ≈
    R17  
    4.7 k  
    2
    N3: 5 T, AWG28  
    Naux: 5 T, AWG32 ( 0.24 mm)  
    Figure 20. 40W Wide Range Mains SMPS for inkjet printer  
    2200pF 4KV  
    16R  
    2A fuse  
    1N4148  
    1nF  
    2KBP04M  
    BYW100-200  
    Vin  
    88 to  
    264 Vac  
    100nF  
    100nF  
    28V / 0.7A  
    µ
    F
    2 x 470  
    35V  
    10 nF  
    250V  
    Ω
    Ω
    75 k  
    15mH  
    N2  
    N3  
    BYW98-100  
    2 x 1000µF  
    Ω
    2 W  
    56 k  
    12V / 1.5A  
    GND  
    1nF  
    N1  
    75 k  
    STTA106  
    16V  
    BYW100-50  
    Ω
    10  
    Ω
    47 k  
    5V / 0.5A  
    µ
    F
    47  
    1N4148  
    µ
    470 F  
    N5  
    N4  
    16V  
    5
    8
    Ω
    3 M  
    STP4NA80FP  
    Ω
    10  
    7
    4
    Ω
    220  
    L6565  
    3
    10 nF  
    PC817A  
    100 nF  
    Ω
    16 k  
    Ω
    Ω
    270 k  
    3.9 k  
    2
    1
    6
    0.39 Ω  
    1/2 W  
    Ω
    5.1 k  
    PC817  
    TL431  
    3.3 nF  
    Ω
    2.7 k  
    TRANSFORMER SPECS:  
    CORE: ETD29x16x10, 3C85 material or equivalent  
    ≈
    1 mm air gap for a primary inductance of 700 µH  
    N1: 75 T, AWG25 ( 0.51 mm)  
    N2: 8 T, AWG25  
    N3: 7 T, AWG20 ( 0.89 mm)  
    N4: 3 T, AWG25  
    N5: 7 T, AWG32 ( 0.24 mm)  
    12/17  
    L6565  
    APPLICATION IDEAS  
    Here follows a series of ideas/suggestions aimed at either improving performance or solving common applica-  
    tion issues of L6565-based power supplies.  
    Figure 21. Enhanced turn-off for big MOSFET's drive  
    Vcc  
    8
    7
    GD  
    Q
    DRIVER  
    BC327  
    Rs  
    6
    L6565  
    GND  
    Figure 22. Latched shutdown on: a) feedback disconnection; b) overload or short circuit  
    Vcc  
    Vcc  
    8
    8
    L6565  
    L6565  
    2
    2
    COMP  
    COMP  
    BC327  
    1N4148  
    BC327  
    1N4148  
    BC337  
    BC337  
    a)  
    b)  
    Figure 23. Secondary Feedback loop configurations  
    Vout  
    Vout  
    Vout  
    L6565  
    2
    1
    Vcc  
    8
    INV  
    COMP  
    L6565  
    2
    1
    Vcc  
    INV  
    COMP  
    8
    R
    A
    R
    B
    ICOMP  
    L6565  
    TL431  
    TL431  
    TL431  
    4
    1
    CS  
    Roff  
    Rs  
    INV  
    a)  
    b)  
    c)  
    13/17  
    L6565  
    Figure 24. Primary Feedback loop configurations  
    Vcc  
    Vcc  
    8
    COMP  
    COMP  
    8
    2
    1
    2
    1
    H
    H
    R
    R
    R
    R
    -
    -
    to VFF  
    block  
    to VFF  
    block  
    INV  
    INV  
    E/A  
    E/A  
    +
    +
    L
    L
    2.5V  
    2.5V  
    GND  
    GND  
    6
    6
    L6565  
    L6565  
    a)  
    b)  
    Figure 25. Protection against secondary  
    Figure 27. Remote ON/OFF control  
    feedback disconnection by primary  
    regulation take-over  
    L6565  
    5
    Vcc  
    15 V  
    ZCD  
    8
    1
    INV  
    OFF  
    L6565  
    BC337  
    2
    ON  
    COMP  
    2.2 kΩ  
    Figure 28. Low-consumption start-up circuit  
    Figure 26. Leading edge blanking circuit for  
    enhanced primary regulation  
    +Vin  
    Vac  
    BC327 1N4148  
    R
    CSTART  
    1N4148  
    Vcc  
    Vcc  
    CSUPPLY  
    8
    470 pF  
    L6565  
    1N4148  
    L6565  
    Ω
    2.7 k  
    6
    GND  
    GND  
    RELATED DOCUMENTATION  
    [1] "L6565, QUASI-RESONANT CONTROLLER” (AN1326)  
    [2] “25W QUASI-RESONANT FLYBACK CONVERTER FOR SET-TOP BOX APPLICATIONS USING THE  
    L6565” (AN1376)  
    [3] “EVAL6565N, 30W AC-DC ADAPTER WITH THE L6565 QUASI-RESONANT PWM CONTROLLER”  
    (AN1439).  
    14/17  
    L6565  
    mm  
    inch  
    DIM.  
    OUTLINE AND  
    MECHANICAL DATA  
    MIN.  
    TYP. MAX. MIN.  
    3.32  
    TYP. MAX.  
    0.131  
    A
    a1  
    B
    0.51  
    1.15  
    0.020  
    1.65 0.045  
    0.55 0.014  
    0.304 0.008  
    10.92  
    0.065  
    0.022  
    b
    0.356  
    0.204  
    b1  
    D
    E
    0.012  
    0.430  
    7.95  
    9.75 0.313  
    2.54  
    0.384  
    e
    0.100  
    e3  
    e4  
    F
    7.62  
    0.300  
    7.62  
    0.300  
    6.6  
    0.260  
    I
    5.08  
    0.200  
    L
    3.18  
    3.81 0.125  
    1.52  
    0.150  
    Minidip  
    Z
    0.060  
    15/17  
    L6565  
    mm  
    inch  
    DIM.  
    OUTLINE AND  
    MECHANICAL DATA  
    MIN. TYP. MAX. MIN. TYP. MAX.  
    A
    a1  
    a2  
    a3  
    b
    1.75  
    0.069  
    0.010  
    0.065  
    0.033  
    0.019  
    0.010  
    0.020  
    0.1  
    0.25 0.004  
    1.65  
    0.65  
    0.35  
    0.19  
    0.25  
    0.85 0.026  
    0.48 0.014  
    0.25 0.007  
    b1  
    C
    0.5  
    0.010  
    c1  
    D (1)  
    E
    45° (typ.)  
    4.8  
    5.8  
    5.0  
    6.2  
    0.189  
    0.228  
    0.197  
    0.244  
    e
    1.27  
    3.81  
    0.050  
    0.150  
    e3  
    F (1)  
    L
    3.8  
    0.4  
    4.0  
    0.15  
    0.157  
    0.050  
    0.024  
    1.27 0.016  
    0.6  
    M
    SO8  
    S
    8° (max.)  
    (1) D and F do not include mold flash or protrusions. Mold flash or  
    potrusions shall not exceed 0.15mm (.006inch).  
    16/17  
    L6565  
    Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
    of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
    by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
    to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
    authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
    The ST logo is a registered trademark of STMicroelectronics  
    © 2003 STMicroelectronics - All Rights Reserved  
    STMicroelectronics GROUP OF COMPANIES  
    Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco -  
    Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.  
    http://www.st.com  
    17/17  

      L6565A相关文章


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