low-side FET turns on allowing the inductor current to ramp
down until the next switching cycle. For each sequential over-
current event, the reference voltage is decremented and
PWM pulses are skipped resulting in a current limit that does
not aggressively fold back for brief over-current events, while
at the same time providing frequency and voltage foldback
protection during hard short circuit conditions.
Operation Description
GENERAL
The LM20145 switching regulator features all of the functions
necessary to implement an efficient low voltage buck regula-
tor using a minimum number of external components. This
easy to use regulator features two integrated switches and is
capable of supplying up to 5A of continuous output current.
The regulator utilizes peak current mode control with nonlin-
ear slope compensation to optimize stability and transient
response over the entire output voltage range. Peak current
mode control also provides inherent line feed-forward, cycle-
by-cycle current limiting and easy loop compensation. The
switching frequency can be varied from 250 kHz to 750 kHz.
The device can operate at high switching frequency allowing
use of a small inductor while still achieving high efficiency.
The precision internal voltage reference allows the output to
be set as low as 0.8V. Fault protection features include: cur-
rent limiting, thermal shutdown, over voltage protection, and
shutdown capability. The device is available in the
eTSSOP-16 package featuring an exposed pad to aid thermal
dissipation. The LM20145 can be used in numerous applica-
tions to efficiently step-down from a 5V or 3.3V bus. The
typical application circuit for the LM20145 is shown in Figure
2 in the design guide.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set
the start up time or track an external voltage source. The start
up or Soft-Start time can be adjusted by connecting a capac-
itor from the SS/TRK pin to ground. The Soft-Start feature
allows the regulator output to gradually reach the steady state
operating point, thus reducing stresses on the input supply
and controlling start up current. If no Soft-Start capacitor is
used the device defaults to the internal Soft-Start circuitry re-
sulting in a start up time of approximately 1 ms. For applica-
tions that require a monotonic start up or utilize the PGOOD
pin, an external Soft-Start capacitor is recommended. The
SS/TRK pin can also be set to track an external voltage
source. The tracking behavior can be adjusted by two external
resistors connected to the SS/TRK pin as shown in Figure 7.
in the design guide.
PRE-BIAS START UP CAPABILITY
The LM20145 is in a pre-biased state when the device starts
up with an output voltage greater than zero. This often occurs
in many multi-rail applications such as when powering an FP-
GA, ASIC, or DSP. In these applications the output can be
pre-biased through parasitic conduction paths from one sup-
ply rail to another. Even though the LM20145 is a syn-
chronous converter it will not pull the output low when a
prebias condition exists. During start up the LM20145 will not
sink current until the Soft-Start voltage exceeds the voltage
on the FB pin. Since the device can not sink current it protects
the load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.18V (typical). The EN pin has 66 mV of hys-
teresis and will disable the output when the enable voltage
falls below 1.11V (typical). If the EN pin is not used, it should
be connected to VIN. Since the enable pin has a precise turn-
on threshold it can be used along with an external resistor
divider network from VIN to configure the device to turn-on at
a precise input voltage. The precision enable circuitry will re-
main active even when the device is disabled.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
PEAK CURRENT MODE CONTROL
The LM20145 has built in under and over voltage compara-
tors that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
part will terminate the present on-pulse, turn-on the low-side
FET, and pull the PGOOD pin low. The low-side FET will re-
main on until either the FB voltage falls back into regulation
or the zero cross detection is triggered which in turn tri-states
the FETs. If the output reaches the UVP threshold the part will
continue switching and the PGOOD pin will be asserted and
go low. Typical values for the PGOOD resistor are on the or-
der of 100 kΩ or less. To avoid false tripping during transient
glitches the PGOOD pin has 16 µs of built in deglitch time to
both rising and falling edges.
In most cases, the peak current mode control architecture
used in the LM20145 only requires two external components
to achieve a stable design. The compensation can be select-
ed to accommodate any capacitor type or value. The external
compensation also allows the user to set the crossover fre-
quency and optimize the transient performance of the device.
For duty cycles above 50% all current mode control buck
converters require the addition of an artificial ramp to avoid
sub-harmonic oscillation. This artificial linear ramp is com-
monly referred to as slope compensation. What makes the
LM20145 unique is the amount of slope compensation will
change depending on the output voltage. When operating at
high output voltages the device will have more slope com-
pensation than when operating at lower output voltages. This
is accomplished in the LM20145 by using a non-linear
parabolic ramp for the slope compensation. The parabolic
slope compensation of the LM20145 is much better than the
traditional linear slope compensation because it optimizes the
stability of the device over the entire output voltage range.
UVLO
The LM20145 has a built-in under-voltage lockout protection
circuit that keeps the device from switching until the input
voltage reaches 2.7V (typical). The UVLO threshold has 45
mV of hysteresis that keeps the device from responding to
power-on glitches during start up. If desired the turn-on point
of the supply can be changed by using the precision enable
pin and a resistor divider network connected to VIN as shown
in Figure 6. in the design guide.
CURRENT LIMIT
The precise current limit of the LM20123 is set at the factory
to be within 10% over the entire operating temperature range.
This enables the device to operate with smaller inductors that
have lower saturation currents. When the peak inductor cur-
rent reaches the current limit threshold, an over current event
is triggered and the internal high-side FET turns off and the
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction tem-
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