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产品型号LM3475的Datasheet PDF文件预览

October 2004

LM3475

Hysteretic PFET Buck Controller

General Description

Features

n Easy to use control methodology

n 0.8V to V_INadjustable output range

n High Efficiency (90% typical)

The LM3475 is a hysteretic P-FET buck controller designed

to support a wide range of high efficiency applications in a

very small SOT23-5 package. The hysteretic control scheme

has several advantages, including simple system design

with no external compensation, stable operation with a wide

range of components, and extremely fast transient re-

sponse. Hysteretic control also provides high efficiency op-

eration, even at light loads. The PFET architecture allows for

low component count as well as 100% duty cycle and ultra-

low dropout operation.

0.9% ( 1.5% over temp) feedback voltage

n 100% duty cycle capable

n Maximum operating frequency up to 2MHz

n Internal Soft-Start

n Enable pin

n SOT23-5 package

Applications

n TFT Monitor

n Auto PC

n Vehicle Security

n Navigation Systems

n Notebook Standby Supply

n Battery Powered Portable Applications

n Distributed Power Systems

Typical Application Circuit

20070101

DS200701

www.national.com

Connection Diagram

Top View

20070102

5 Lead Plastic SOT23-5

NS package Number MF05A

Package Marking and Ordering Information

Order Number

Package Type

Package Marking

Supplied As:

LM3475MF

SOT23-5

S65B

1000 units on Tape and Reel

3000 units on Tape and Reel

LM3475MFX

SOT23-5

S65B

Pin Description

Pin Name

Pin Number

Description

Feedback input. Connect to a resistor divider between the output

and GND.

GND

Ground.

Enable. Pull this pin above 1.5V (typical) for normal operation.

When EN is low, the device enters shutdown mode.

Power supply input.

VIN

PGATE

Gate drive output for the external PFET.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Lead Temperature

Vapor Phase (60 sec.)

Infared (15 sec.)

215˚C

220˚C

V_IN

−0.3V to 16V

−0.3V to 5V

−0.3V to 16V

−65˚C to 150˚C

440mW

PGATE

Operating Ratings (Note 1)

Supply Voltage

Operating Junction

Temperature

2.7V to 10V

−40˚C to +125˚C

Storage Temperature

Power Dissipation (Note 2)

ESD Susceptibilty

Human Body Model (Note 3)

2.5kV

Electrical Characteristics

Specifications in Standard type face are for T_J= 25˚C, and in bold type face apply over the full Operating Temperature

Range (T_J= −40˚C to +125˚C). Unless otherwise specified, V_IN= EN = 5.0V. Datasheet min/max specification limits are guar-

anteed by design, test, or statistical analysis.

Symbol

Parameter

Conditions

EN = V_IN(PGATE

Open)

Min

170

Typ

Max

320

Unit

I_Q

Quiescent Current

260

µA

EN = 0V

V_FB

Feedback Voltage

Line Regulation

Comparator

0.788

0.8

0.812

%∆V_FB/∆V_IN

2.7V V_IN10V

0.01

%/V

V_HYST

I_FB

Vth_EN

I_EN

2.7V V_IN10V

Hysteresis

−40˚C to +125˚C

FB Bias Current

Enable Threshold

Voltage

600

Increasing

1.2

1.5

365

.025

1.8

Hysteresis

µA

Enable Leakage

Current

EN = 10V

Source

2.8

1.8

I_SOURCE= 100mA

Sink

R_PGATE

Driver Resistance

Ω

I_Sink= 100mA

Source

V_PGATE= 3.5V

C_PGATE= 1nF

Sink

0.475

1.0

I_PGATE

Driver Output Current

Soft-Start Time

V_PGATE= 3.5V

C_PGATE= 1nF

2.7V V_IN10V

T_SS

(EN Rising)

T_ONMIN

V_UVD

Minimum On-Time

Under Voltage

Detection

PGATE Open

Measured at the FB

180

0.56

0.487

0.613

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Electrical Characteristics (Continued)

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to

be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, T

, the junction-to-ambient thermal resistance, θ and

J_MAX

the ambient temperature, T . The maximum allowable power dissipation at any ambient temperature is calculated using:

= (T

- T )/θ . The maximum power dissipation of 0.44W is determined using T = 25˚C, θ = 225˚C/W, and T

= 125˚C.

J_MAX

D_MAX

J_MAX

Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

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Typical Performance Characteristics Unless specified otherwise, all curves taken at V_IN= 5V,

V_OUT= 2.5V, L = 10 µH, C_OUT= 100 µF, ESR = 100mΩ, and T_A= 25˚C.

Quiescent Current vs Input Voltage

Feedback Voltage vs Temperature

20070122

20070123

Hysteresis Voltage vs Input Voltage

Hysteresis Voltage vs Temperature

20070124

20070125

Efficiency vs Input Voltage

I_OUT= 2A

Efficiency vs Load Current

20070126

20070127

www.national.com

Typical Performance Characteristics Unless specified otherwise, all curves taken at V_IN= 5V, V_OUT

= 2.5V, L = 10 µH, C_OUT= 100 µF, ESR = 100mΩ, and T_A= 25˚C. (Continued)

Start Up

Output Ripple Voltage

20070128

20070129

Load Transient Response with External Ramp

Load Transient Response

(Circuit from Figure 3)

(Typical Application Circuit from Figure 5)

20070131

20070132

www.national.com

Block Diagram

20070103

Operation Description

OVERVIEW

The LM3475 is a buck (step-down) DC-DC controller that

uses a hysteretic control architecture, which results in Pulse

Frequency Modulated (PFM) regulation. The hysteretic con-

trol scheme does not utilize an internal oscillator. Switching

frequency depends on external components and operating

conditions. Operating frequency decreases at light loads,

resulting in excellent efficiency compared to PWM architec-

tures. Because switching is directly controlled by the output

conditions, hysteretic control provides exceptional load tran-

sient response.

HYSTERETIC CONTROL CIRCUIT

The LM3475 uses a comparator-based voltage control loop.

The voltage on the feedback pin is compared to a 0.8V

reference with 21mV of hysteresis. When the FB input to the

comparator falls below the reference voltage, the output of

the comparator goes low. This results in the driver output,

PGATE, pulling the gate of the PFET low and turning on the

PFET.

20070104

FIGURE 1. Hysteretic Waveforms

With the PFET on, the input supply charges C_OUTand

supplies current to the load through the PFET and the induc-

tor. Current through the inductor ramps up linearly, and the

output voltage increases. As the FB voltage reaches the

upper threshold (reference voltage plus hysteresis) the out-

put of the comparator goes high, and the PGATE turns the

PFET off. When the PFET turns off, the catch diode turns on,

and the current through the inductor ramps down. As the

output voltage falls below the reference voltage, the cycle

repeats. The resulting output, inductor current, and switch

node waveforms are shown in Figure 1.

The LM3475 operates in discontinuous conduction mode at

light load current and continuous conduction mode at heavy

load current. In discontinuous conduction mode, current

through the inductor starts at zero and ramps up to the peak,

then ramps down to zero. The next cycle starts when the FB

voltage reaches the reference voltage. Until then, the induc-

tor current remains zero. Operating frequency is low, as are

switching losses. In continuous conduction mode, current

always flows through the inductor and never ramps down to

zero.

SOFT-START

The LM3475 includes an internal soft-start function to protect

components from excessive inrush current and output volt-

age overshoot. As V_INrises above 2.7V (typical), the internal

bias circuitry becomes active. When EN goes high, the

www.national.com

MINIMUM ON/OFF TIME

Operation Description (Continued)

To ensure accurate comparator switching, the LM3475 im-

poses a blanking time after each comparator state change.

This blanking time is 180ns typically. Immediately after the

comparator goes high or low, it will be held in that state for

the duration of the blanking time. This helps keep the hys-

teretic comparator from improperly responding to switching

noise spikes (See Reducing Switching Noise) and ESL

spikes (See Output Capacitor Selection) at the output.

device enters soft-start. During soft-start, the reference volt-

age is ramped up to the nominal value of 0.8V in approxi-

mately 4ms. Duty cycle and output voltage will increase as

the reference voltage is ramped up.

UNDER VOLTAGE DETECTION

When the output voltage falls below 70% (typical) of the

normal voltage, as measured at the FB pin, the device turns

off PFET and restarts a new soft-start cycle. In short circuit,

the PFET is always on, and the converter is effectively a

resistor divider from input to output to ground. Whether the

part restarts depends on the power path resistance and the

short circuit resistance. This feature should not be consid-

ered as overcurrent protection or output short circuit protec-

tion.

At very low or very high duty cycle operation, maximum

frequency will be limited by the blanking time. The maximum

operating frequency can be determined by the following

equations:

F_MAX= D / ton_min

F_MAX= (1-D) / toff_min

Where D is the duty cycle, defined as V_OUT/V_IN, and ton_min

and toff_minis the sum of the blanking time, the propagation

delay time and the PFET delay time (see Figure 1).

PGATE

During switching, the PGATE pin swings from V_IN(off) to

ground (on). As input voltage increases, the time it takes to

slew the gate of the PFET on and off also increases. Also, as

the PFET gate voltage approaches V_IN, the PGATE current

driving capability decreases. This can cause a significant

additional delay in turning the switch off when using a PFET

with a low threshold voltage. These two effects will increase

power dissipation and reduce efficiency. Therefore, a PFET

with relatively high threshold voltage and low gate capaci-

tance is recommended.

ENABLE PIN (EN)

The LM3475 provides a shutdown function via the EN pin to

disable the device. The device is active when the EN pin is

pulled above 1.5V (typ) and in shutdown mode when EN is

below 1.135V (typ). In shutdown mode, total quiescent cur-

rent is less than 10µA. The EN pin can be directly connected

to V_INfor always-on operation.

www.national.com

Design Information

SETTING OUTPUT VOLTAGE

Where delay is the sum of the LM3475 propagation delay

time and the PFET delay time. The propagation delay is

90ns typically.

The output voltage is programmed using a resistor divider

between V_OUTand GND as shown in Figure 2. The feedback

resistors can be calculated as follows:

Minimum output ripple voltage can be determined using the

following equation:

V_{OUT_PP}= V_HYST( R1 + R2 ) / R2

USING A FEED-FORWARD CAPACITOR

The operating frequency and output ripple voltage can also

be significantly influenced using a speed up capacitor, C_ff, as

shown in Figure 2. C_ffis connected in parallel with the high

side feedback resistor, R1. The output ripple causes a cur-

rent to be sourced or sunk through this capacitor. This cur-

rent is essentially a square wave. Since the input to the

feedback pin (FB) is a high impedance node, the bulk of the

current flows through R2. This superimposes a square wave

ripple voltage on the FB node. The end result is a reduction

in output ripple and an increase in operating frequency.

When adding C_ff, calculate the formula above with α= 1. The

value of C_ffdepends on the desired operating frequency and

the value of R2. A good starting point is 1nF ceramic at

100kHz decreasing linearly with increased operating fre-

quency. Also note that as the output voltage is programmed

below 1.6V, the effect of C_ffwill decrease significantly.

Where Vfb is 0.8V typically.

The feedback resistor ratio, α = (R1+R2) / R2, will also be

used below to calculate output ripple and operating fre-

quency.

INDUCTOR SELECTION

The most important parameters for the inductor are the

inductance and the current rating. The LM3475 operates

over a wide frequency range and can use a wide range of

inductance values. Minimum inductance can be calculated

using the following equation:

20070115

Where D is the duty cycle, defined as V_OUT/V_IN, and ∆I is the

allowable inductor ripple current.

FIGURE 2. Hysteretic Window

Maximum allowable inductor ripple current should be calcu-

lated as a function of output current (I_OUT) as shown below:

∆I_max= I_OUTx 0.3

The inductor must also be rated to handle the peak current

(I_PK) and RMS current given by:

SETTING OPERATING FREQUENCY AND OUTPUT

RIPPLE

Although hysteretic control is a simple control scheme, the

operating frequency and other performance characteristics

depend on external conditions and components. If the induc-

tance, output capacitance, ESR, V_IN, or C_ffis changed, there

will be a change in the operating frequency and possibly

output ripple. Therefore, care must be taken to select com-

ponents which will provide the desired operating range. The

best approach is to determine what operating frequency is

desirable in the application and then begin with the selection

of the inductor and output capacitor ESR. The design pro-

cess usually involves a few iterations to select appropriate

standard values that will result in the desired frequency and

ripple.

I_PK= (I_OUT+ ∆I/2) x 1.1

The inductance value and the resulting ripple is one of the

key parameters controlling operating frequency.

OUTPUT CAPACITOR SELECTION

Once the desired operating frequency and inductance value

are selected, ESR must be selected based on the equation

in the Setting Operating Frequency and Output Ripple. This

process may involve a few iterations to select standard ESR

and inductance values.

Without the feedforward capacitor (C_ff), the operating fre-

quency (F) can be approximately calculated using the for-

mula:

In general, the ESR of the output capacitor and the inductor

ripple current create the output ripple of the regulator. How-

ever, the comparator hysteresis sets the first order value of

this ripple. Therefore, as ESR and ripple current vary, oper-

ating frequency must also vary to keep the output ripple

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Capacitors with high ESL (equivalent series inductance) val-

ues should not be used. As shown in Figure 1, the output

ripple voltage contains a small step at both the high and low

peaks. This step is caused by and is directly proportional to

the output capacitor’s ESL. A large ESL, such as in an

electrolytic capacitor, can create a step large enough to

cause abnormal switching behavior.

Design Information (Continued)

voltage regulated. The hysteretic control topology is well

suited to using ceramic output capacitors. However, ceramic

capacitors have a very low ESR, resulting in a 90˚ phase

shift of the output voltage ripple. This results in low operating

frequency and increased output ripple. To fix this problem a

low value resistor could be added in series with the ceramic

output capacitor. Although counter intuitive, this combination

of a ceramic capacitor and external series resistance provide

highly accurate control over the output voltage ripple. An-

other method is to add an external ramp at the FB pin as

shown in Figure 3. By proper selection of R1 and C2, the FB

pin sees faster voltage change than the output ripple can

cause. As a result, the switching frequency is higher while

the output ripple becomes lower. The switching frequency is

approximately:

INPUT CAPACITOR SELECTION

A bypass capacitor is required between V_INand ground. It

must be placed near the source of the external PFET. The

input capacitor prevents large voltage transients at the input

and provides the instantaneous current when the PFET turns

on. The important parameters for the input capacitor are the

voltage rating and the RMS current rating. Follow the manu-

facturer’s recommended voltage de-rating. RMS current and

power dissipation (PD) can be calculated with the equations

below:

Other types of capacitor, such as Sanyo POSCAP, OS-CON,

and Nichicon ’NA’ series are also recommended and may be

used without additional series resistance. For all practical

purposes, any type of output capacitor may be used with

proper circuit verification.

20070120

FIGURE 3. External Ramp

DIODE SELECTION

P-CHANNEL MOSFET SELECTION

The catch diode provides the current path to the load during

the PFET off time. Therefore, the current rating of the diode

must be higher than the average current through the diode,

which be calculated as shown:

The PFET switch should be selected based on the maximum

Drain-Source voltage (VDS), Drain current rating (I_D), maxi-

mum Gate-Source voltage (VGS), on resistance (R_DSON),

and Gate capacitance. The voltage across the PFET when it

is turned off is equal to the sum of the input voltage and the

diode forward voltage. The VDS must be selected to provide

some margin beyond the sum of the input voltage and Vd.

I_{D_AVE}= I_OUTx (1 − D)

The peak voltage across the catch diode is approximately

equal to the input voltage. Therefore, the diode’s peak re-

verse voltage rating should be greater than 1.3 times the

input voltage.

Since the current flowing through the PFET is equal to the

current through the inductor, I_Dmust be rated higher than the

maximum I_PK. During switching, PGATE swings the PFET’s

gate from V_INto ground. Therefore, A PFET must be se-

lected with a maximum VGS larger than V_IN. To insure that

the PFET turns on completely and quickly, refer to the

PGATE section.

A Schottky diode is recommended, since a low forward

voltage drop will improve efficiency.

For high temperature applications, diode leakage current

may become significant and require a higher reverse voltage

rating to achieve acceptable performance.

www.national.com

resistor in series with PGATE. However, this resistor will

increase the switching losses in the PFET and will lower

efficiency. Therefore it should be kept as small as possible

and only used when necessary. Another method to reduce

switching noise (other than good PCB layout, see Layout

section) is to use a small RC filter or snubber. The snubber

should be placed in parallel with the catch diode, connected

close to the drain of the PFET, as shown in Figure 4. Again,

the snubber should be kept as small as possible to limit its

impact on system efficiency. A typical range is a 10Ω-100Ω

resistor and a 470pF to 2.2nF ceramic capacitor.

Design Information (Continued)

The power loss in the PFET consists of switching losses and

conducting losses. Although switching losses are difficult to

precisely calculate, the equation below can be used to esti-

mate total power dissipation. Increasing R_DSONwill increase

power losses and degrade efficiency. Note that switching

losses will also increase with lower gate threshold voltages.

PD_switch= R_DSONx (I_OUT)²x D + F x I_OUTx V_INx (t_on+ t_off)/2

where:

t_on= FET turn on time

t_off= FET turn off time

A value of 10ns to 50ns is typical for ton and toff. Note that

the R_DSONhas a positive temperature coefficient. At 100˚C,

the R_DSONmay be as much as 150% higher than the value

at 25˚C.

The Gate capacitance of the PFET has a direct impact on

both PFET transition time and the power dissipation in the

LM3475. Most of the power dissipated in the LM3475 is used

to drive the PFET switch. This power can be calculated as

follows:

The amount of average gate driver current required during

switching (I_G) is:

I_G= Q_gx F

And the total power dissipated in the device is:

I_qV_IN+ I_GV_IN

20070105

Where I_qis typically 260µA as shown in the Electrical Char-

acteristics table. As gate capacitance increases, operating

frequency may need to be reduced, or additional heat sink-

ing may be required to lower the power dissipation in the

device.

FIGURE 4. PGATE Resistor and Snubber

Layout

PC board layout is very important in all switching regulator

designs. Poor layout can cause EMI problems, excess

switching noise and poor operation.

In general, keeping the gate capacitance below 2000pF is

recommended to keep transition times (switching losses),

and power losses low.

As shown in Figure 6 and Figure 7, place the ground of the

input capacitor as close as possible to the anode of the

diode. This path also carries a large AC current. The switch

node, the node connecting the diode cathode, inductor, and

PFET drain, should be kept as small as possible. This node

is one of the main sources for radiated EMI.

REDUCING SWITCHING NOISE

Although the LM3475 employs internal noise suppression

circuitry, external noise may continue to be excessive. There

are several methods available to reduce noise and EMI.

MOSFETs are very fast switching devices. The fast increase

in PFET current coupled with parasitic trace inductance can

create unwanted noise spikes at both the switch node and at

V_IN. Switching noise will increase with load current and input

voltage. This noise can also propagate through the ground

plane, sometimes causing unpredictable device perfor-

mance. Slowing the rise and fall times of the PFET can be

very effective in reducing this noise. Referring to Figure 4,

the PFET can be slowed down by placing a small (1Ω-10Ω)

The feedback pin is a high impedance node and is therefore

sensitive to noise. Be sure to keep all feedback traces away

from the inductor and the switch node, which are sources of

noise. Also, the resistor divider should be placed close to the

FB pin. The gate pin of the external PFET should be located

close to the PGATE pin.

Using a large, continuous ground plane is also recom-

mended, particularly in higher current applications.

www.national.com

Layout (Continued)

20070101

FIGURE 5.

Bill of Materials

Designator

Description

10µF, 16V, X5R

100µF, 6V, Ta

1nF, 25V, X7R

Schottky, 20V, 2A

10µH, 3.1A

Part Number

Vendor

TAIYO YUDEN

AVX

C_IN

EMK325BJ106MN

TPSY107M006R0100

VJ1206Y102KXXA

CMSH2-20L

C_OUT

C_FF

Vishay

Central Semiconductor

Sumida

CDRH103R100

Si2343

30V, 2.5A

Vishay

R_FB2

R_FB1

1kΩ, 0805, 1%

2.15kΩ, 0805, 1%

CRW08051001F

CRCW08052151F

Vishay

20070106

FIGURE 6. Top Layer (Standard Board)

(2:1 Scale)

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Layout (Continued)

20070107

FIGURE 7. Top Layer (with External Ramp)

(2:1 Scale)

20070130

FIGURE 8. Bottom Layer

(2:1 Scale)

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Physical Dimensions inches (millimeters) unless otherwise noted

5 Lead Plastic SOT23-5

NS package Number MF05A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship

Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned

Substances’’ as defined in CSP-9-111S2.

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LM3475相关文章

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LM3475MF产品参数

型号:	LM3475MF
Brand Name：	Texas Instruments
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOT-23
包装说明：	LSSOP, TSOP5/6,.11,37
针数：	5
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.27
Samacsys Description：	Sync. Sw. Controller 3V:6V,LM3475MF
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	HYSTERETIC CURRENT MODE
最大输入电压：	10 V
最小输入电压：	2.7 V
标称输入电压：	5 V
JESD-30 代码：	R-PDSO-G5
JESD-609代码：	e0
长度：	2.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	5
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	1 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP
封装等效代码：	TSOP5/6,.11,37
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.45 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	2000 kHz
温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.95 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	1.6 mm

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