LM78CCVF各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

February 2000

LM78

Microprocessor System Hardware Monitor

General Description

Features

n Temperature sensing

The LM78 is a highly integrated Data Acquisition system for

hardware monitoring of servers, Personal Computers, or

virtually any microprocessor based system. In a PC, the

LM78 can be used to monitor power supply voltages, tem-

peratures, and fan speeds. Actual values for these inputs

can be read at any time, and programmable WATCHDOG

limits in the LM78 activate a fully programmable and

maskable interrupt system with two outputs.

n 5 positive voltage inputs

n 2 op amps for negative voltage monitoring

n 3 fan speed monitoring inputs

n Input for additional temperature sensors

n Chassis Intrusion Detector input

n WATCHDOG comparison of all monitored values

n POST code storage RAM

The LM78 has an on-chip temperature sensor, 5 positive

analog inputs, two inverting inputs (for monitoring negative

voltages), and an 8-bit ADC. An input is provided for the

overtemperature outputs of additional temperature sensors

and this is linked to the interrupt system. The LM78 provides

inputs for three fan tachometer outputs. Additional inputs are

provided for Chassis Intrusion detection circuits, VID monitor

inputs, and chainable interrupt. The LM78 provides both ISA

and Serial Bus interfaces. A 32-byte auto-increment RAM is

provided for POST (Power On Self Test) code storage.

2

™

n ISA and I C Serial Bus interfaces

Key Specifications

j

Voltage monitoring

accuracy

±

1% (max)

j

Temperature Accuracy

−10˚C to +100˚C

±

3˚C (max)

5V

j

Supply Voltage

Supply Current

Operating:

Shutdown:

1 mA typ

10 µA typ

8 Bits

Applications

n System Hardware Monitoring for Servers and PCs

n Office Electronics

j

ADC Resolution

n Electronic Test Equipment and Instrumentation

Typical Application

DS012873-1

# indicates Active Low (”Not“)

2

C^®is a registered trademark of the Phillips Corporation.

I

DS012873

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Ordering Information

Connection Diagram

Temperature Range

Package

−10˚C ≤ T_A≤ +100˚C

Order Number

Device Marking

LM78CCVF-J

LM78CCVF

VGZ44A

DS012873-2

Block Diagram

DS012873-3

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2

Pin Descriptions

Number

Type

Description

Name(s)

Number

of Pins

IORD

1

2

3

1

Digital Input

An active low standard ISA bus I/O Read Control.

An active low standard ISA bus I/O Write Control.

IOWR

SYSCLK

The reference clock for the ISA bus. Typically ranges from 4.167 MHz to

8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.

D7–D0

4–11

12

8

1

Digital I/O

POWER

Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,

with D7 the high order bit.

V_CC(+5V)

+5V V_CCpower. Bypass with the parallel combination of 10 µF

(electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.

GNDD

13

14

1

GROUND

Internally connected to all digital circuitry.

SMI__IN

Digital Input

Chainable SMI (System Management Interrupt) Input. This is an active

low input that propagates the SMI signal to the SMI output of the LM78

via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration

Register.

Chassis

Intrusion

15

16

1

Digital I/O

An active high input from an external circuit which latches a Chassis

Intrusion event. This line can go high without any clamping action

regardless of the powered state of the LM78. The LM78 provides an

internal open drain on this line, controlled by Bit 7 of NMI Mask Register

2, to provide a minimum 20 ms reset of this line.

Power

Switch

Bypass

Digital Output

An active low push-pull output intended to drive an external P-channel

power MOSFET for software power control.

FAN3–FAN1

SCL

17–19

20

3

1

Digital Input

Digital I/O

0V to +5V amplitude fan tachometer input.

Serial Bus Clock.

SDA

21

Serial Bus bidirectional Data.

RESET

22

Digital Output

Master Reset, 5 mA driver (open drain), active low output with a 20 ms

minimum pulse width. Available when enabeld via Bit 7 in SMI Mask

Register 2.

NTEST

GNDA

−IN6

FB6

23

24

25

26

27

28

1

Test Output

GROUND

NAND Tree totem-pole output that provides board-level connectivity

testing. Refer to Section 11.0 on NAND Tree testing.

Internally connected to all analog circuitry. The ground reference for all

analog inputs.

Analog Input

Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG

INPUTS”.

Analog Output Output of inverting op amp for Input 6. Refer to section 4.0, “ANALOG

INPUTS”.

FB5

Analog Output Output of inverting op amp for Input 5. Refer to section 4.0, “ANALOG

INPUTS”.

−IN5

Analog Input

Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG

INPUTS”.

IN4–IN0

29–33

34–37

5

4

Analog Input

Digital Input

0V to 4.096V FSR Analog Inputs.

VID3–VID0

Voltage Supply readouts from P6. This value is read in the VID/Fan

Divisor Register.

BTI

38

39

1

Digital Input

Board Temperature Interrupt driven by O.S. outputs of additional

temperature sensors such as LM75. Provides internal pull-up of 10 kΩ.

NMI/IRQ

Digital Output

Non-Maskable Interrupt (open source)/Interrupt Request (open drain).

The mode is selected with Bit 5 of the Configuration Register and the

output is enabled when Bit 2 of the Configuration Register is set to 1.

The default state is disabled and IRQ mode.

SMI

40

1

Digital Output

System Management Interrupt (open drain). This output is enabled when

Bit 1 in the Configuration Register is set to 1. The default state is

disabled.

3

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Pin Descriptions (Continued)

Number

of Pins

3

Type

Description

Name(s)

Number

41–43

A2–A0

Digital Input

The three lowest order bits of the 16-bit ISA Address Bus. A0

corresponds to the lowest order bit.

CS

44

1

Digital Input

Chip Select input from an external decoder which decodes high order

address bits on the ISA Address Bus. This is an active low input.

TOTAL PINS

44

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Vapor Phase (60 seconds)

Infrared (15 seconds)

215˚C

220˚C

Storage Temperature

−65˚C to +150˚C

Operating Ratings(Notes 1, 2)

Positive Supply Voltage (V_CC

)

6.5V

Voltage on Any Input or Output Pin

Ground Difference (GNDD–GNDA)

Input Current at any Pin (Note 3)

Package Input Current (Note 3)

−0.3V to (V_CC+0.3V)

Operating Temperature Range

T_MIN≤ T_A≤ T_MAX

±

300 mV

LM78

−55˚C ≤ T_A≤ +125˚C

T_MIN≤ T_A≤ T_MAX

±

5 mA

Specified Temperature Range

LM78

±

20 mA

−10˚C ≤ T_A≤ +100˚C

Maximum Junction Temperature

(T_Jmax)

Junction to Ambient Thermal Resistance (θ_JA(Note 4) )

NS Package ID: VGZ44A 62˚C/W

150˚C

ESD Susceptibility(Note 5)

Human Body Model

Machine Model

Supply Voltage (V_CC

)

+4.25V to +5.75V

2000V

175V

Ground Difference

(IGNDD–GNDAI)

≤100 mV

Soldering Information

PQFP Package (Note 6) :

V_INVoltage Range

−0.05V to V_CC+ 0.05V

DC Electrical Characteristics(Note 7)

The following specifications apply for +4.25 V_DC≤V_CC≤ +5.75 V_DC, f_SYSCLK= 8.33 MHz, R_S= 25Ω, unless otherwise speci-

fied. Boldface limits apply for T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25˚C.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

POWER SUPPLY CHARACTERISTICS

I_CCSupply Current

Interface Inactive

Shutdown Mode

TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS

1.0

10

2

mA (max)

µA

±

Accuracy

−10˚C ≤ T_A≤ +100˚C

3

˚C (max)

˚C (min)

Resolution

1

ANALOG-TO-DIGITAL CONVERTER CHARACTERISTICS

Resolution (8 bits with full-scale at 4.096V)

16

mV

% (max)

LSB

±

TUE

DNL

PSS

t_C

Total Unadjusted Error

(Note 10)

1

Differential Non-Linearity

Power Supply Sensitivity

Total Monitoring Cycle Time

±

1

%/V

(Note 11)

1.0

1.5

sec (max)

OP AMP CHARACTERISTICS

Output Current (Sourcing)

Input Offset Voltage

50

µA

mV

nA

±

I_OUT= 50 µA

1

±

Input Bias Current

0.1

PSRR

60

70

dB

DC Open Loop Gain

dB

Gain Bandwidth Product

MULTIPLEXER/ADC INPUT CHARACTERISTICS

On Resistance

500

kHz

400

2000

Ω (max)

nA

±

Off Channel Leakage Current

Input Current (On Channel Leakage Current)

FAN RPM-TO-DIGITAL CONVERTER

Accuracy

0.1

±

nA

±

+25˚C ≤ T_A≤ +75˚C

−10˚C ≤ T_A≤ +100˚C

10

15

% (max)

(max)

Full-scale Count

255

5

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DC Electrical Characteristics(Note 7) (Continued)

The following specifications apply for +4.25 V_DC≤V_CC≤ +5.75 V_DC, f_SYSCLK= 8.33 MHz, R_S= 25Ω, unless otherwise speci-

fied. Boldface limits apply for T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25˚C.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

FAN RPM-TO-DIGITAL CONVERTER

FAN1 and FAN2 Nominal Input

RPM (See Section 6.0)

Divisor = 1, Fan Count = 153

(Note 12)

8800

4400

2200

1100

RPM

Divisor = 2, Fan Count = 153

(Note 12)

Divisor = 3, Fan Count = 153

(Note 12)

Divisor = 4, Fan Count = 153

(Note 12)

FAN3 Design Nominal Input RPM

Internal Clock Frequency

Fan Count = 153 (Note 12)

4400

22.5

RPM

+25˚C ≤ T_A≤ +75˚C

20.2

24.8

19.1

25.9

kHz (min)

kHz (max)

kHz (min)

kHz (max)

−10˚C ≤ T_A≤ +100˚C

22.5

DIGITAL OUTPUTS (Power Switch Bypass, NTEST, NMI/IRQ)

±

V_OUT(1)Logical “1” Output Voltage

V_OUT(0)Logical “0” Output Voltage

ISA D0–D7 DIGITAL OUTPUTS

V_OUT(1)Logical “1” Output Voltage

V_OUT(0)Logical “0” Output Voltage

I_OUT

=

5.0 mA

2.4

0.4

V (min)

V (max)

±

I_OUT

=

12.0 mA

2.4

0.4

1

V (min)

V (max)

µA (max)

µA (min)

I_OUT

TRI-STATE^®Output Current

V_OUT= 0 V_DC

V_OUT= V_CC

0.005

−0.005

−1

OPEN DRAIN DIGITAL OUTPUTS (SDA, RESET, SMI, Chassis Intrusion)

V_OUT(0)Logical “0” Output Voltage

I_OUT= −5.0 mA

V_OUT= V_CC

0.4

100

20

V (min)

µA (max)

ms (min)

I_OH

High Level Output Current

RESET and Chassis Intrusion

Pulse Width

0.1

45

DIGITAL INPUTS: SMI__IN, VID0–VID3, BTI, CS, A0, A1, A2, Mode Control and Interface Inputs (IORD, IOWR, SYSCLK),

Data Lines (D0–D7), Chassis Intrusion, and Tach Pulse Logic Inputs (FAN1, FAN2, FAN3)

V_IN(1)

V_IN(0)

Logical “1” Input Voltage

Logical “0” Input Voltage

2.0

0.8

V (min)

V (max)

SERIAL BUS DIGITAL INPUTS (SCL, SDA)

V_IN(1)

V_IN(0)

Logical “1” Input Voltage

Logical “0” Input Voltage

0.7 x V_CC

0.3 x V_CC

V (min)

V (max)

ALL DIGITAL INPUTS EXCEPT FOR BTI

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

V_IN= V_CC

−0.005

0.005

20

−1

1

µA (min)

µA (max)

pF

V_IN= 0 V_DC

BIT DIGITAL INPUT

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Current

V_IN= V_CC

1

10

µA (max)

pF

Logical “0” Input Current

Digital Input Capacitance

V_IN= 0 V_DC

−500

20

−2000

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AC Electrical Characteristics(Note 13) The following specifications apply for +4.25 V_DC≤ V_CC

≤

=

+5.75 V_DCunless otherwise specified. Boldface limits apply for T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J

25˚C.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

ISA TIMING CHARACTERISTICS

f_SYSCLK

_CS(setup)

t_CS(hold)

_SA(setup)

System Clock (SYSCLK) Input Frequency

CS Active to IORD/IOWR Active

8.33

MHz

t

10

30

10

ns (min)

IORD/IOWR Inactive to CS Inactive

Address Valid to IORD/IOWR Active

IORD/IOWR Inactive to Address Invalid

t

t_SA(hold)

ISA WRITE TIMING

t

_SDWR(setup)

t_SDWR(hold)

_WR(setup)

Data Valid to IOWR Active

5

ns (min)

IOWR Inactive to Data Invalid

IOWR Active to Rising Edge of SYSCLK

t

20

DS012873-4

The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not

occur unintentionally. (See Section 3.2 ‘Resets’ )

FIGURE 1. ISA Bus Write Timing Diagram

7

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AC Electrical Characteristics(Note 13) The following specifications apply for +4.25 V_DC≤ V_CC≤ +5.75 V_DC

unless otherwise specified. Boldface limits apply for T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25˚C. (Continued)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

ISA READ TIMING

t_SDRD(setup)

Data Valid to IORD Inactive

120

5

ns (min)

ns (max)

t_SDRD(hold)

IORD Inactive to Data Invalid

t_RD(setup)

IORD Active to Rising Edge of SYSCLK

20

t_RS(delay)

Rising Edge of SYSCLK number 1 to Data

Valid

With 8.33

MHz

360

SYSCLK

DS012873-5

The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not

occur unintentionally. (SeeSection 3.2‘Resets’ )

FIGURE 2. ISA Bus Read Timing Diagram

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AC Electrical Characteristics(Note 13) The following specifications apply for +4.25 V_DC≤ V_CC≤ +5.75 V_DC

unless otherwise specified. Boldface limits apply for T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25˚C. (Continued)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

SERIAL BUS TIMING CHARACTERISTICS

t₁

t₂

t₃

t₄

t₅

SCL (Clock) Period

2.5

100

0

µs (min)

ns (min)

Data In Setup Time to SCL High

Data Out Stable After SCL Low

SDA Low Setup Time to SCL Low (start)

SDA High Hold Time After SCL High (stop)

100

DS012873-6

FIGURE 3. Serial Bus Timing Diagram

9

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Electrical Characteristics (Continued)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified

<

>

V

CC

Note 3: When the input voltage (V ) at any pin exceeds the power supplies (V

(GNDD or GNDA) or V

), the current at that pin should be limited to 5 mA.

IN

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T max, θ and the ambient temperature, T . The maximum

J

JA

A

allowable power dissipation at any temperature is P = (T max−T )/θ .

JA

D

J

A

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin.

Note 6: See the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount

devices.

Note 7: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above

V

or 0.3V below GND will not damage the LM78. There are parasitic diodes that exist between the inputs and the power supply rails. Errors in the ADC conversion

CC

can occur if these diodes are forward biased by more than 50 mV. As an example, if V

conversions.

is 4.50 V , input voltage must be ≤ 4.55 V , to ensure accurate

DC DC

CC

DS012873-7

An x indicates that the diode exists.

Pin Name

D1 D2 D3

Pin Name

IORD

D1 D2 D3

FAN1–FAN3

SCL

x

IOWR

SDA

x

SYSCLK

D0–D7

RESET

NTEST

x

SMI__IN

Chassis Intrusion

x

Power Switch

Bypass

Pin Name

BTI

D1

x

D2

D3

Pin Name

−IN6

D1

D2

D3

x

NMI/IRQ

SMI

x

FB6

x

FB5

A0–A2

CS

−IN5

IN4–IN0

VID3–VID0

x

FIGURE 4. ESD Protection Input Structure

Note 8: Typicals are at T =T =25˚C and represent most likely parametric norm.

J

A

Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 10: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC and any error introduced by the amplifiers as shown in the circuit of

Figure 13 .

Note 11: Total Monitoring Cycle Time includes temperature conversion, 7 analog input voltage conversions and 3 tachometer readings. Each temperature and input

voltage conversion takes 100 ms typical and 112 ms maximum. Fan tachometer readings take 20 ms typical, at 4400 rpm, and 200 ms max.

Note 12: The total fan count is based on 2 pulses per revolution of the fan tachometer output.

Note 13: Timing specifications are tested at the TTL logic levels, V =0.4V for a falling edge and V =2.4V for a rising edge. TRI-STATE output voltage is forced

IL

IH

to 1.4V.

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10

Test Circuit

DS012873-8

FIGURE 5. Digital Output Load Circuitry

•

Serial Bus Address Register: Contains the Serial Bus

address. At power on it assumes the default value of

0101101 binary, and can be altered via the ISA or Serial

Bus interface.

Functional Description

1.0 GENERAL DESCRIPTION

The LM78 provides 7 analog inputs, a temperature sensor, a

Delta-Sigma ADC (Analog-to-Digital Converter), 3 fan speed

counters, WATCHDOG registers, and a variety of inputs and

outputs on a single chip. Interfaces are provided for both the

ISA parallel bus or Serial Bus. The LM78 performs power

supply, temperature, and fan monitoring for personal com-

puters.

•

Chip Reset/ID Register: Allows reseting of all the reg-

isters to the default power-on reset value. Provides a bit

for identification between the current version of this de-

vice and an older version which does not have this reset

capability.

•

POST RAM: FIFO RAM to store up to 32 bytes of 8-bit

POST codes. Overflow of the POST RAM will set an

Interrupt. The POST RAM, located at base address x0h

and x4h, allows for easy decoding to address 80h and

84h, the normal addresses for outputting of POST codes.

Interrupt will only be set when writing to port x0h or x4h.

The POST RAM can be read via ports 85h and 86h.

The LM78 continuously converts analog inputs to 8-bit digital

words with a 16 mV LSB (Least Significant Bit) weighting,

yielding input ranges of from 0V to 4.096V. The two negative

analog inputs provide inverting op amps, with their

non-inverting input referred to ground. With additional exter-

nal feedback components, these inputs provide measure-

ments of negative voltages (such as -5V and -12V power

supplies). The analog inputs are useful for monitoring sev-

eral power supplies present in a typical computer. Tempera-

ture is converted to an 8-bit two’s-complement digital word

with a 1˚C LSB.

Value RAM: The monitoring results: temperature, volt-

ages, fan counts, and WATCHDOG limits are all con-

tained in the Value RAM. The Value RAM consists of a

total of 64 bytes. The first 11 bytes are all of the results,

the next 19 bytes are the WATCHDOG limits, and are

located at 20h-3Fh, including two unused bytes in the

upper locations. The next 32 bytes, located at 60h-7Fh,

mirror the first 32 bytes with identical contents. The only

difference in the upper bytes are that they auto-increment

the LM78 Internal Address Register when read from or

written to via the ISA bus (auto-increment is not available

for Serial Bus communications).

Fan inputs measure the period of tachometer pulses from

the fans, providing a higher count for lower fan speeds. The

fan inputs are digital inputs with an acceptable range of 0V to

5V and a transition level of approximately 1.4V. Full scale fan

counts are 255 (8-bit counter) and this represents a stopped

or very slow fan. Nominal speeds, based on a count of 153,

are programmable from 1100 to 8800 RPM on FAN1 and

FAN2, with FAN3 fixed at 4400 RPM. Signal conditioning

circuitry is included to accommodate slow rise and fall times.

When the LM78 is started, it cycles through each measure-

ment in sequence, and it continuously loops through the

sequence approximately once every second. Each mea-

sured value is compared to values stored in WATCHDOG, or

Limit registers. When the measured value violates the pro-

grammed limit the LM78 will set a corresponding Interrupt in

the Interrupt Status Registers. Two hardware Interrupt lines,

SMI and NMI/IRQ, are fully programmable with separate

masking of each Interrupt source, and masking of each

output. In addition, the Configuration Register has control

bits to enable or disable the hardware Interrupts.

The LM78 provides a number of internal registers, as de-

tailed in Figure 6. These include:

•

Configuration Register:

figuration.

Provides control and con-

Interrupt Status Registers:

status of each WATCHDOG limit or Interrupt event.

Two registers to provide

Interrupt Mask Registers: Allows masking of indi-

vidual Interrupt sources, as well as separate masking for

each of both hardware Interrupt outputs.

Additional digital inputs are provided for chaining of SMI

(System Management Interrupt), outputs of multiple external

LM75 temperature sensors via the BTI (Board Temperature

Interrupt) input, and a Chassis Intrusion input. The Chassis

Intrusion input is designed to accept an active high signal

from an external circuit that latches when the case is re-

moved from the computer.

•

VID/Fan Divisor Registers: A register to read the sta-

tus of the VID input lines. The high bits of this register

contain the divisor bits for FAN1 and FAN2 inputs.

11

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A typical application designed to utilize the POST RAM

would decode the LM78 to the address space starting at

80h, which is where POST codes are output to. Otherwise,

the LM78 can be decoded into a different desired address

space.

Functional Description (Continued)

2.0 INTERFACE

The LM78 only decodes the three lowest address bits on the

ISA bus. Referring to the ISA bus timing diagrams in Figure

1 and Figure 2, the Chip Select Input, CS, should be taken

low by external address decoder circuitry to access the

LM78. The LM78 decodes the following base addresses:

To communicate with an LM78 Register, first write the ad-

dress of that Register to Port x5h. Read or write data from or

to that register via Port x6h. A write will take IOWR low, while

a read will take IORD low.

-Port x0h: Power On Self Test codes from ISA bus.

-Port x4h: Power On Self Test codes from ISA bus.

-Port x5h: The LM78s Internal Address Register

-Port x6h: Data Register

If the Serial Bus Interface and ISA bus interface are used

simultaneously there is the possibility of collision. To prevent

this from occurring in applications where both interfaces are

used, read port x5h and if the Most Significant Bit, D7, is

high, ISA communication is limited to reading port x5h only

until this bit is low. A Serial Bus communication occurring

while ISA is active will not be a problem, since even a single

bit of Serial Bus communication requires 10 microseconds,

in comparison to less than a microsecond for an entire ISA

communication.

IORD is the standard ISA bus signal that indicates to the

LM78 that it may drive data on to the ISA data bus.

IOWR is the standard ISA command to the LM78 that it may

latch data from the ISA bus.

SYSCLK is the standard ISA SYSCLK, typically 8.33 MHz.

This clock is used only for timing of the ISA interface of the

LM78. All other clock functions within LM78 such as the ADC

and fan counters are done with a separate asynchronous

internal clock.

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Functional Description (Continued)

DS012873-9

FIGURE 6. LM78 Register Structure

13

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Functional Description (Continued)

2.1 Internal Registers of the LM78

TABLE 1. The internal registers and their corresponding internal LM78 address is as follows:

Register

LM78 Internal Hex

Address

Power on

Value

Notes

(This is the data to be

written to Port x5h)

40h

Configuration Register

0000 1000

0000 0000

Interrupt Status Register 1

41h

Auto-increment to the address of Interrupt Status

Register 2 after a read or write to Port x6h.

Interrupt Status Register 2

SMI Mask Register 1

42h

43h

0000 0000

Auto-increment to the address of SMI Mask

Register 2 after a read or write to Port x6h.

SMI Mask Register 2

NMI Mask Register 1

44h

45h

0000 0000

Auto-increment to the address of NMI Mask

Register 2 after a read or write to Port x6h.

NMI Mask Register 2

46h

47h

0100 0000

0101 XXXX

VID/Fan Divisor Register

The first four bits set the divisor for Fan

Counters 1 and 2. The lower four bits reflect the

state of the VID inputs.

Serial Bus Address Register

Chip Reset/ID Register

POST RAM

48h

49h

0010 1101

0100 0000

00h-1Fh

Auto-increment when written to from Port x0h or

x4h. Auto-increment after a read or write to Port

x6h, with a separate pointer. Auto-incrementing

stops when address 1Fh is reached.

Value RAM

20h-3Fh

60h-7Fh

Auto-increment after a read or write to Port x6h.

Auto-incrementing stops when address 7Fh is

reached.

A typical communication with the LM78 would consist of:

1. Write to Port x5h the LM78 Internal Address (from col-

umn 2 above) of the desired register. Alternatively, when

both ISA and Serial Bus interfaces are used, the first

step in a communication may be to read Port x5h to

ascertain the state of the Busy bit to avoid contention

with an Serial Bus communication.

2. Read or write the corresponding registers data with

reads/writes from Port x6h.

The LM78 Internal Address latches, and does not have to be written if it is already pointing at the desired register. The LM78

Internal Address Register is read/write (Bit 7 is read only).

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Functional Description (Continued)

2.2 Serial Bus Interface

DS012873-10

(a) Serial Bus Write to the Internal Address Register followed by the Data Byte

DS012873-11

(b) Serial Bus Write to the Internal Address Register Only

DS012873-12

(c) Serial Bus Read from a Register with the Internal Address Register Preset to Desired Location

FIGURE 7. Serial Bus Timing

When using the Serial Bus Interface a write will always

consist of the LM78 Serial Bus Interface Address byte, fol-

lowed by the Internal Address Register byte, then the data

byte. There are two cases for a read:

Auto-Increment does not operate. When writing to or reading

from a Register which Auto-Increments with ISA communi-

cations, the Register must be manually incremented for

Serial Bus communications.

1. If the Internal Address Register is known to be at the

desired Address, simply read the LM78 with the Serial

Bus Interface Address byte, followed by the data byte

read from the LM78.

The default power on Serial Bus address for the LM78 is:

0101101 binary. This address can be changed by writing any

desired value to the Serial Bus address register, which can

be done either via the ISA or Serial Bus. During and Serial

Bus communication on the BUSY bit (bit 7) in the address

register at x5h will be high, and any ISA activity in that

situation should be limited to reading port x5h only.

2. If the Internal Address Register value is unknown, write

to the LM78 with the Serial Bus Interface Address byte,

followed by the Internal Address Register byte. Then

restart the Serial Communication with a Read consisting

of the Serial Bus Interface Address byte, followed by the

data byte read from the LM78.

All of these communications are depicted in the Serial Bus

Interface Timing Diagrams as shown in Figure 7.

In all other respects the LM78 functions identically for Serial

Bus communications as it does for ISA communications.

15

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ing loop and puts the LM78 in shutdown mode, reducing

power consumption. ISA and Serial Bus communication is

possible with any register in the LM78 although activity on

these lines will increase shutdown current, up to as much as

maximum rated supply current, while the activity takes place.

Taking Bit 0 high starts the monitoring loop, described in

more detail subsequently.

Functional Description (Continued)

3.0 USING THE LM78

3.1 Power On

When power is first applied, the LM78 performs a “power on

reset” on several of its registers. The power on condition of

registers in shown in Table I. Registers whose power on

values are not shown have power on conditions that are

indeterminate (this includes the value RAM and WATCH-

DOG limits). The ADC is inactive. In most applications, usu-

ally the first action after power on would be to write WATCH-

DOG limits into the Value RAM.

Bit 1 of the Configuration Register enables the SMI Interrupt

hardwire output when this bit is taken high. Similarly, Bit 2 of

the Configuration Register enables the NMI/IRQ Interrupt

hardwire output when taken high. The NMI/IRQ mode is

determined by Bit 5 in the Configuration Register. When Bit

5 is low the output is an active low IRQ output. Taking Bit 5

high inverts this output to provide an active high NMI output.

3.2 Resets

The Power Switch Bypass provides an active low at the

Power Switch Bypass output when set high. This is intended

for use in software power control by activating an external

power control MOSFET.

Configuration Register INITIALIZATION accomplishes the

same function as power on reset on most registers. The

POST RAM, Value RAM conversion results, and Value RAM

WATCHDOG limits are not Reset and will be indeterminate

immediately after power on. If the Value RAM contains valid

conversion results and/or Value RAM WATCHDOG limits

have been previously set, they will not be affected by a

Configuration Register INITIALIZATION. Power on reset, or

Configuration Register INITIALIZATION, clear or initialize

the following registers (the initialized values are shown on

Table I):

3.4 Starting Conversion

The monitoring function (Analog inputs, temperature, and

fan speeds) in the LM78 is started by writing to the Configu-

ration Register and setting INT__Clear (Bit 3), low, and Start

(bit 0), high. The LM78 then performs a “round-robin” moni-

toring of all analog inputs, temperature, and fan speed inputs

approximately once a second. The sequence of items being

monitored corresponds to locations in the Value RAM and is:

•

Configuration Register

Interrupt Status Register 1

Interrupt Status Register 2

SMI Mask Register 1

SMI Mask Register 2

NMI Mask Register 1

NMI Mask Register 2

VID/Fan Divisor Register

1. Temperature

2. IN0

3. IN1

4. IN2

5. IN3

6. IN4

7. -IN5

Serial Bus Address Register (Power on reset only, not

reset by Configuration Register INITIALIZATION)

8. -IN6

9. Fan 1

10. Fan 2

11. Fan 3

Configuration Register INITIALIZATION is accomplished by

setting Bit 7 of the Configuration Register high. This bit

automatically clears after being set.

The LM78-J allows the user to perform an unconditional

complete Power-on reset by writing a one to Bit 5 of the Chip

Reset/ID Register. The LM78-J can be differentiated from

the LM78 without the J suffix by reading Chip Reset/ID

Register Bit 6. A high would indicate that the LM78-J is being

used. The LM78-J allows an unconditional complete

Power-on reset to be initiated by taking the IOWR and IORD

signal lines low simultaneously, for at least 50 ns, while CS is

high. The delay between consecutive IORD and IOWR

pulses should be greater than 50 ns to ensure that an

Power-on reset does not occur unintentionally.

3.5 Reading Conversion Results

The conversion results are available in the Value RAM.

Conversions can be read at any time and will provide the

result of the last conversion. Because the ADC stops, and

starts a new conversion whenever it is read, reads of any

single value should not be done more often then once every

120 ms. When reading all values, allow at least 1.5 seconds

between reading groups of values. Reading more frequently

than once every 1.5 seconds can also prevent complete

updates of Interrupt Status Registers and Interrupt Output’s.

A typical sequence of events upon power on of the LM78

would consist of:

In systems where the serial bus is only being used it may be

advantageous to take both IOWR and IORD to the system

reset pulse. In this way whenever the system is reset the

LM78-J will also be reset to a known state.

1. Set WATCHDOG Limits

2. Set Interrupt Masks

3. Start the LM78 monitoring process

3.3 Using the Configuration Register

4.0 ANALOG INPUTS

The Configuration Register provides all control over the

LM78. At power on, the ADC is stopped and INT__Clear is

asserted, clearing the SMI and NMI/IRQ hardwire outputs.

The Configuration Register starts and stops the LM78, en-

ables and disables interrupt outputs and modes, and pro-

vides the Reset function described in Section 3.2.

The 8-bit ADC has a 16 mV LSB, yielding a 0V to 4.08V

(4.096–1LSB) input range. This is true for all analog inputs.

In PC monitoring applications these inputs would most often

be connected to power supplies. The 2.5V and 3.3V supplies

can be directly connected to the inputs. The 5V and 12V

inputs should be attenuated with external resistors to any

desired value within the input range.

Bit 0 of the Configuration Register controls the monitoring

loop of the LM78. Setting Bit 0 low stops the LM78 monitor-

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16

0 to V_CC. In the event these inputs are supplied from fan

outputs which exceed 0 to V_CC, either resistive division or

diode clamping must be included to keep inputs within an

acceptable range, as shown in Figure 9. R2 is selected so

that it does not develop excessive voltage due to input

leakage. R1 is selected based on R2 to provide a minimum

input of 2V and a maximum of V_CC. R1 should be as low as

possible to provide the maximum possible input up to V_CCfor

best noise immunity. Alternatively, use a shunt reference or

zener diode to clamp the input level.

Functional Description (Continued)

A typical application, such as is shown in Figure 8, might

select the input voltage divider to provide 3V at the analog

inputs of the LM78. This is sufficiently high for good resolu-

tion of the voltage, yet leaves headroom for upward excur-

sions from the supply of about 25%. To simplify the process

of resistor selection, set the value of R2 first. Select a value

for R2 between 10 kΩ and 100 kΩ. This is low enough to

avoid errors due to input leakage currents yet high enough to

both protect the inputs under overdrive conditions as well as

minimize loading of the source. Then select R1 to provide a

3V input according to:

If fans can be powered while the power to the LM78 is off,

the LM78 inputs will provide diode clamping. Limit input

current to the Input Current at Any Pin specification shown in

the ABSOLUTE MAXIMUM RATINGS section. In most

cases, open collector outputs with pull-up resistors inher-

ently limit this current. If this maximum current could be

exceeded, either a larger pull up resistor should be used or

resistors connected in series with the fan inputs.

The negative inputs provide inverting op amps with

non-inverting inputs connected to ground. The output of

these op amps are designed to only drive the input of the

LM78 and their associated feedback loops. Avoid heavy

loading, long lines, and capacitive loading with these op

amps. Additional loading may cause oscillations and thus

erroneous readings. The optimum feedback resistor (resistor

from Feedback to -IN pin) value is approximately 60 kΩ,

based on the op amp nominal output current rating of 50 µA

at an output voltage of 3V. Locate the feedback resistors as

close as possible to the LM78. The recommended range for

R_INis from 30 kΩ to 300 kΩ.

The Fan Inputs gate an internal 22.5 kHz oscillator for one

period of the Fan signal into an 8-bit counter (maximum

count = 255). The default divisor, located in the VID/Fan

Divisor Register, is set to 2 (choices are 1, 2, 4, and 8)

providing a nominal count of 153 for a 4400 rpm fan with two

pulses per revolution. Typical practice is to consider 70% of

normal RPM a fan failure, at which point the count will be

219.

Determine the fan count according to:

Select R_INaccording to:

Note that Fan 1 and Fan 2 Divisors are programmable via

the VID/Fan Divisor Register. Fan 3 is not adjustable, and its

Divisor is always set to 2.

The analog inputs have internal diodes that clamp inputs

exceeding the power supply and ground. Exceeding any

analog input has no detrimental effect on other channels.

The input diodes will also clamp voltages appearing at the

inputs of an un-powered LM78. External resistors should be

included to limit input currents to the values given in the

ABSOLUTE MAXIMUM RATINGS for Input Current At Any

Pin. Inputs with the attenuator networks will usually meet

these requirements. If it is possible for inputs without attenu-

ators (such as the 2.5V or 3.3V supplies) to be turned on

while LM78 is powered off, additional resistors of about 10

kΩ should be added in series with the inputs to limit the input

current.

Fans that provide only one pulse per revolution would re-

quire a divisor set twice as high as fans that provide two

pulses, thus maintaining a nominal fan count of 153. There-

fore, the divisor should be set to 4 for a fan that provides 1

pulse per revolution with a nominal RPM of 4400.

5.0 LAYOUT AND GROUNDING

Analog inputs will provide best accuracy when referred to the

AGND pin. A separate, low-impedance ground plane for

analog ground, which provides a ground point for the voltage

dividers and analog components, will provide best perfor-

mance but is not mandatory. Analog components such as

voltage dividers and feedback resistors should be located

physically as close as possible to the LM78.

The power supply bypass, the parallel combination of 10 µF

(electrolytic or tantalum) and 0.1 µF (ceramic) bypass ca-

pacitors connected between pin 12 and ground, should also

be located as close as possible to the LM78.

6.0 FAN INPUTS

Inputs are provided for signals from fans equipped with

tachometer outputs. These are logic-level inputs with an

approximate threshold of 1.4V. Signal conditioning in the

LM78 accommodates the slow rise and fall times typical of

fan tachometer outputs. The maximum input signal range is

17

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Functional Description (Continued)

Voltage Measurements (V_S)

R1 or R_IN

R2 or R_F

NONE

10 kΩ

60 kΩ

Voltage at Analog Inputs

+2.50V

+3.30V

+5V

0

+2.50V

+3.30V

+2.98V

+3.00V

0

6.8 kΩ

30 kΩ

240 kΩ

100 kΩ

+12V

−12V

−5V

DS012873-13

FIGURE 8. Input Examples. Resistor Values Shown Provide Approximately 3V at the Analog Inputs

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Functional Description (Continued)

DS012873-14

(a) Fan with Tach Pull-Up to +5V

DS012873-15

(b) Fan with Tach Pull-Up to +12V, or Totem-Pole

Output and Resistor Attenuator

DS012873-16

DS012873-17

(c) Fan with Tach Pull-Up to +12V and Diode Clamp

(d) Fan with Strong Tach Pull-Up or Totem Pole Output

and Diode Clamp

FIGURE 9. Alternatives for Fan Inputs

Counts are based on 2 pulses per revolution tachometer outputs.

RPM

Time per Revolution

Counts for “Divide by 2”

(Default) in Decimal

153 counts

Comments

4400

3080

2640

13.64 ms

19.48 ms

22.73 ms

Typical RPM

70% RPM

60% RPM

219 counts

255 counts

(maximum counts)

Nominal

Counts for the

70%

Time per Revolution

Mode Select

Time per Revolution

RPM

Given Speed in Decimal

for 70% RPM

9.74 ms

Divide by 1

Divide by 2

Divide by 4

Divide by 8

8800

4400

2200

1100

6.82 ms

13.64 ms

27.27 ms

54.54 ms

153

6160

3080

1540

770

19.48 ms

38.96 ms

77.92 ms

19

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7.1 Temperature Data Format

Functional Description (Continued)

Temperature data can be read from the Temperature, T_OISet

Point, and T_HYSTSet Point registers; and written to the T_OI

Set Point, and T_HYSTSet Point registers. Temperature data

is represented by an 8-bit, two’s complement word with an

LSB (Least Significant Bit) equal to 1.0˚C:

7.0 TEMPERATURE MEASUREMENT SYSTEM

The LM78 bandgap type temperature sensor and ADC per-

form 8-bit two’s-complement conversions of the tempera-

ture. A digital comparator is also incorporated that compares

the readings to the user-programmable Overtemperature

setpoint and Hysteresis values.

Temperature

Digital Output

Binary

Hex

7Dh

19h

01h

00h

FFh

E7h

C9h

+125˚C

+25˚C

+1.0˚C

+0˚C

0111 1101

0001 1001

0000 0001

0000 0000

1111 1111

1110 0111

1100 1001

−1.0˚C

−25˚C

−55˚C

7.2 Temperature Interrupts

The normal mode for temperature interrupts in the LM78 is

an “Interrupt”mode operating in the following way: Exceeding

T_OIcauses an interrupt that will remain active indefinitely

until reset by reading Interrupt Status Register 1. Once an

interrupt event has occurred by crossing T_OI, then reset, an

interrupt will only occur again by the temperature going

below T_HYST. Again, it will remain active indefinitely until

being reset by reading Interrupt Status Register 1.

A “Comparator” mode for temperature interrupts can be

made available by setting the T_HYSTlimit to 127˚C. This

results in a simple “thermostat” type of function where an

interrupt will be set whenever the temperature exceeds the

T_OIlimit. Reading Interrupt Status Register 1 will clear the

interrupt as usual, but the interrupt will set again after the

completion of another measurement cycle. It will remain set

until the temperature goes below the T_OIlimit (allow up to

two measurement cycles for clearing after descending below

T_OIwhile in Comparator mode).

DS012873-18

FIGURE 10. Temperature-to-Digital Transfer Function

(Non-Linear Scale for Clarity)

DS012873-19

DS012873-20

*

Note: Interrupt resets occur only when interrupt Status Register 1 is read.

Interrupt resets occur when Interrupt Status Register 1 is read but will set

again when monitoring cycle continues (as long as temperature exceeds

(a) Interrupt Mode

T

). When temperature descends below T allow up to two monitoring

OI

loops before the Temperature Interrupt resets.

(b) Comparator Mode

FIGURE 11. Temperature Interrupt Response Diagram

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Functional Description (Continued)

8.0 THE LM78 INTERRUPT STRUCTURE

DS012873-21

FIGURE 12. Interrupt Structure

Figure 12 depicts the Interrupt Structure of the LM78. The

LM78 can generate Interrupts as a result of each of its

internal WATCHDOG registers on the analog, temperature,

and fan inputs. Overflow of the POST RAM (greater than 32

bytes written to POST RAM) will also cause an Interrupt.

ceeds a programmed threshold. Up to 8 LM75’s can be

connected to a single Serial Bus bus with their O.S.

output’s wire or’d to the BTI input of the LM78. If the

temperature of any LM75 exceeds its programmed limit,

it drives BTI low. This generates an Interrupt to notify the

host of a possible overtemperature condition. Provides

an internal pull-up of 10 kΩ.

External Interrupts can come from the following three

sources. While the labels suggest a specific type or source

of Interrupt, these labels are not restrictions of their usage,

and they could come from any desired source:

•

BTI: This is an active low Interrupt intended to come

from the O.S. output of LM75 temperature sensors. The

LM75 O.S. output goes active when its temperature ex-

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POST RAM auto-increments the internal pointer of the

LM78. Up to 32 bytes may be stored. An excess of 32 bytes

will generate an Interrupt and stop incrementing.

Functional Description (Continued)

•

Chassis Intrusion: This is an active high interrupt from

any type of device that detects and captures chassis

intrusion violations. This could be accomplished me-

chanically, optically, or electrically, and circuitry external

to the LM78 is expected to latch the event. The design of

the LM78 allows this input to go high even with no power

applied to the LM78, and no clamping or other interfer-

ence with the line will occur. This line can also be pulled

low for at least 20 ms by the LM78 to reset a typical

Chassis Intrusion circuit. Accomplish this reset by setting

Bit 7 of NMI Mask Register 2 high. The bit in the Register

is self-clearing.

The POST RAM is read as like any other register at Ports

x5h and x6h, with the POST RAM located at the LM78

Internal Address from 00h to 1Fh. Reading the POST RAM

via x6h will also auto-increment, but this is a separate pointer

than the one used for ports 80h and 84h.

11.0 NAND TREE TESTS

A NAND tree is provided in the LM78 for Automated Test

Equipment (ATE) board level connectivity testing. NAND tree

tests are accomplished in either power on reset or Configu-

ration Register reset state, with the Start Bit, Bit 0 of the

Configuration Register low, and the INT__Clear (Bit 3) high.

In this mode, forcing the SMI output low takes all pins except

Power Switch Bypass, RESET, -IN5, -IN6, V_CC, GNDA, and

GNDD to a high impedance (either TRI-STATE or open

drain) state. All high impedance pins can be taken to 0 and

V_CCto accomplish NAND tree tests.

•

SMI__IN:

This active low Interrupt merely provides a

way to chain the SMI Interrupt from other devices through

the LM78 to the processor.

All Interrupts are indicated in the two Interrupt Status Reg-

isters. The NMI/IRQ and SMI outputs have individual mask

registers, and individual masks for each Interrupt. As de-

scribed in Section 3.3, these two hardware Interrupt lines

can also be enabled/disabled in the Configuration Register.

The Configuration Register is also used to set the mode of

the NMI/IRQ Interrupt line.

To perform a NAND tree test all pins included in the NAND

tree should be driven to 1. Each individual pin (excluding the

aforementioned exceptions) can be toggled and the resulting

toggle observed on the NTEST pin. Allow for a typical propa-

gation delay of 200 ns.

8.1 Interrupt Clearing

Reading the Interrupt Status Register will output the con-

tents of the Register, and reset the Register. A subsequent

read done before the analog “round-robin” monitoring loop is

complete will indicate a cleared Register. Allow at least 1.5

seconds to allow all Registers to be updated between reads.

In summary, the Interrupt Status Register clears upon being

read, and requires at least 1.5 seconds to be updated. When

the Interrupt Status Register clears, the hardware interrupt

line will also clear until the Registers are updated by the

monitoring loop.

The hardware Interrupt lines are cleared with the INT__Clear

bit, which is Bit 3 of the Configuration Register. When this bit

is high, the LM78 monitoring loop will stop. It will resume

when the bit is low.

9.0 RESET AND Power Switch Bypass OUTPUTS

In PC applications the Power Switch Bypass provides a gate

drive signal to an external P-channel MOSFET power switch.

This external MOSFET then would keep power turned on

regardless of the state of front panel power switches when

software power control is used. In any given application this

signal is not limited to the function described by its label. For

example, since the LM78 incorporates temperature sensing,

the Power Switch Bypass output could also be utilized to

control power to a cooling fan. Take Power Switch Bypass

active low by setting Bit 6 in the Configuration Register high.

RESET is intended to provide a master reset to devices

connected to this line. SMI Mask Register 2, Bit 7, must be

set high to enable this function. Setting Bit 4 in the Configu-

ration Register high outputs a least 20 ms low on this line, at

the end of which Bit 4 in the Configuration Register automati-

cally clears. Again, the label for this pin is only its suggested

use. In applications where the RESET capability is not

needed it can be used for any type of digital control that

requires a 20 ms active low open drain output.

10.0 POST RAM

The POST RAM is located at address x0h and x4h, which

typical address decoders will decode to 80h or 84h, where

the BIOS will output Power On Self Test codes. A write to the

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Functional Description (Continued)

12.0 FAN MANUFACTURERS

Manufacturers of cooling fans with tachometer outputs are

listed below:

NMB Tech

9730 Independence Ave.

Chatsworth, California 91311

818 341-3355

818 341-8207

Model Num-

ber

Frame Size

Airflow

CFM

2408NL

2.36 in sq. X 0.79 in

(60 mm sq. X 20 mm)

2.36 in sq. X 0.98 in

(60 mm sq. X 25 mm)

3.15 in sq. X 0.79 in

(80 mm sq. X 20 mm)

3.15 in sq. X 0.98 in

(80 mm sq. X 25 mm)

9-16

2410ML

3108NL

3110KL

14-25

25-42

25-40

Mechatronics Inc.

P.O. Box 20

Mercer Island, WA 98040

800 453-4569

Various sizes available with tach output option.

Sanyo Denki America, Inc.

468 Amapola Ave.

Torrance, CA 90501

310 783-5400

Model Number

109P06XXY601

109R06XXY401

109P08XXY601

109R08XXY401

Frame Size

Airflow

CFM

2.36 in sq. X 0.79 in

(60 mm sq. X 20 mm)

2.36 in sq. X 0.98 in

(60 mm sq. X 25 mm)

3.15 in sq. X 0.79 in

(80 mm sq. X 20 mm)

3.15 in sq. X 0.98 in

(80 mm sq. X 25 mm)

11-15

13-28

23-30

21-42

23

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Functional Description (Continued)

REGISTERS AND RAM

13.1 Address Register (Port x5h)

The main register is the ADDRESS Register located at Port x5h. The bit designations are as follows:

Bit

6-0

7

Name

Read/

Write

Description

Address

Pointer

Busy

Read/Write

Address of RAM and Registers. See the tables below for detail.

Read

Only

A one indicates the device is busy because of a Serial Bus transaction or another ISA

bus transaction. With checking this bit, multiple ISA drivers can use LM78 without

interfering with each other or a Serial Bus driver.

It is the user’s responsibility not to have a Serial Bus and ISA bus operations at the

same time.

This bit is:

Set: with a write to Port x5h or when a Serial Bus transaction is in progress.

Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the

Serial Bus transaction is finished.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Busy

Address Pointer (Power On default 00h)

(Power On default 0)

A6

A5

A4

A3

A2

A1

A0

Address Pointer Index (A6–A0)

Registers and RAM

A6–A0 in

Hex

Power On Value of

Registers:

Notes

<

>

7:0 in Binary

Configuration Register

40h

41h

0000 1000

0000 0000

Interrupt Status Register 1

Auto-increment to the address of Interrupt

Status Register 2 after a read or write to

Port x6h.

Interrupt Status Register 2

SMI Mask Register 1

42h

43h

0000 0000

Auto-increment to the address of SMI Mask

Register 2 after a read or write to Port x6h.

SMI Mask Register 2

NMI Mask Register 1

44h

45h

0000 0000

Auto-increment to the address of NMI Mask

Register 2 after a read or write to Port x6h.

NMI Mask Register 2

46h

47h

0100 0000

<

>

7:4 = 0101;

VID/Fan Divisor Register

>

3:0 = VID3–VID0

Serial Bus Address Register

Chip Reset/ID Register

POST RAM

48h

0010 1101

0100 0000

49h

00–1Fh

Auto-increment to the next location after a

read or write to Port x6h and stop at 1Fh.

Value RAM

20–3Fh

60–7Fh

Auto-increment to the next location after a

read or write to Port x6h and stop at 7Fh.

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Functional Description (Continued)

13.2 Data Register (Port x6h)

<

>

Power on default 7:0 = 00h

Bit

Name

Read/

Write

Description

7–0

Data

Read/Write Data to be read from or to be written to RAM and Register.

13.3 Configuration Register—Address 40h

<

>

Power on default 7:0 = 00001000 binary

Bit

Name

Start

Read/

Write

Description

0

Read/Write

A one enables startup of monitoring operations, a zero puts the part in standby mode.

Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this

location after an interrupt has occurred unlike “INT__Clear” bit.

1

2

SMI Enable

Read/Write

A one enables the SMI Interrupt output.

NMI/IRQ

Enable

A one enables the NMI/IRQ Interrupt output.

3

INT__Clear

Read/Write

A one disables the SMI and NMI/IRQ outputs without affecting the contents of Interrupt

Status Registers. The device will stop monitoring. It will resume upon clearing of this

bit.

< >

= 1 in SMI

4

5

6

7

RESET

Read/Write

A one outputs at least a 20 ms active low reset signal at RESET if

7

Mask Register 2. This bit is cleared once the pulse has gone inactive.

NMI/IRQ

Select

A one selects NMI, and a zero selects IRQ.

Power Switch

Bypass

A one in this bit drives a zero on Power Switch Bypass pin.

INITIALIZATION

A one restores power on default value to all registers except the Serial Bus Address

register. This bit clears itself since the power on default is zero.

25

www.national.com

Functional Description (Continued)

13.4 Interrupt Status Register 1—Address 41h

<

>

Power on default 7:0 = 00h

Bit

0

Name

IN0

Read/Write

Read Only

Description

A one indicates a High or Low limit has been exceeded.

1

IN1

IN2

IN3

2

3

4

Temperature Read Only

5

BTI

Read Only

A one indicates an interrupt has occurred from the Board Temperature Interrupt (BTI)

input (O.S. output of multiple LM75 chips).

6

7

FAN1

FAN2

Read Only

A one indicates the fan count limit has been exceeded.

13.5 Interrupt Status Register 2—Address 42h

<

>

Power on default 7:0 = 00h

Bit Name Read/Write

Description

0

1

2

3

4

5

IN4

Read Only

A one indicates a High or Low limit has been exceeded.

A one indicates the fan count limit has been exceeded.

A one indicates Chassis Intrusion has gone high.

-IN5

-IN6

FAN3

Chassis Intrusion

FIFO Overflow

A one indicates an overflow in FIFO (POST RAM) i.e. 32nd location in FIFO has

been written via Port x0h or x4h.

6

7

SMI__IN

Reserved

Read Only

A one indicates SMI__IN has gone low.

13.6 SMI Mask Register 1—Address 43h

<

>

Power on default 7:0 = 00h

Bit

Name

Read/

Description

Write

0

1

2

3

4

5

6

7

IN0

Read/Write

A one disables the corresponding interrupt status bit for SMI interrupt.

IN1

IN2

IN3

Temperature Read/Write

BTI

Read/Write

FAN1

FAN2

www.national.com

26

Functional Description (Continued)

13.7 SMI Mask Register 2—Address 44h

<

>

Power on default 7:0 = 00h

Bit Name Read/

Description

Write

0

1

2

3

4

5

6

7

IN4

Read/Write

A one disables the corresponding interrupt status bit for SMI interrupt.

-IN5

-IN6

FAN3

Chassis Intrusion

FIFO Overflow

SMI__IN

< >

RESET Enable

7

= 1 in SMI Mask Register 2 enables the RESET in the Configuration Register.

13.8 NMI Mask Register 1—Address 45h

<

>

Power on default 7:0 = 00h

Bit

Name

Read/

Description

Write

0

1

2

3

4

5

6

7

IN0

Read/Write

A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.

IN1

IN2

IN3

Temperature Read/Write

BTI

Read/Write

FAN1

FAN2

13.9 NMI Mask Register 2—Address 46h

<

>

Power on 7:0 = 01000000 binary

Bit

Name

Read/

Description

Write

0

1

2

3

4

5

6

IN4

Read/Write

A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.

Note: The Power on default is 1 for this bit.

-IN5

-IN6

FAN3

Chassis Intrusion

FIFO Overflow

SMI__IN

7

Chassis Clear

Read/Write

A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The

register bit self clears after the pulse has been output.

27

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Functional Description (Continued)

13.10 VID/Fan Divisor Register—Address 47h

<

>

<

>

<

>

Power on – 7:4 is 0101, and 3:0 is mapped to VID 3:0

Bit

3-0

5-4

Name

Read/Write

Read Only

Read/Write

Description

<

>

<

>

VID 3:0

The VID 3:0 inputs

FAN1 RPM

Control

FAN1 Speed Control.

<

>

5:4 = 00 - divide by 1;

>

5:4 = 01 - divide by 2;

>

5:4 = 10 - divide by 4;

>

5:4 = 11 - divide by 8.

7-6

FAN2 RPM

Control

Read/Write

FAN2 Speed Control.

<

>

7:6 = 00 - divide by 1;

>

7:6 = 01 - divide by 2;

>

7:6 = 10 - divide by 4;

>

7:6 = 11 - divide by 8.

13.11 Serial Bus Address Register—Address 48h

<

>

< >

Power on default Serial Bus address 6:0 = 0101101 and 7 = 0 binary

Bit

Name

Serial Bus

Read/Write

Description

< >

Serial Bus address 6:0

6-0

Read/Write

Address

7

Reserved

Read Only

13.12 Chip Reset/ID Register Address 49h

<

>

Power on default for the LM78-J 7:0 = 0100 0000; Power

<

>

on default for LM78 7:0 = 0000 0000.

Bit

0-4

5

Name

Read/Write

Read Only

Read/Write

Read Only

Description

Reserved

Chip Reset

Device ID

A one will reset all the registers of the LM78 to the power on default state.

6

When set the latest version of the LM78 the LM78-J is being used. When cleared

designates the old version of LM78.

7

Reserved

Read Only

13.13 POST RAM—Address 00h–1Fh

The address pointer for the POST RAM auto-increments when written to at Port x0h or x4h. Once the address pointer reaches

1Fh, a FIFO overflow interrupt will be generated and the FIFO will stop incrementing. Normal reads via Port x5h and x6h

auto-increment a separate pointer, and will not cause a FIFO overflow interrupt.

13.14 Value RAM—Address 20h–3Fh or 60h–7Fh (auto-increment)

Address A6–A0 with

Address A6–A0

Description

Auto-Increment

20h

21h

22h

23h

24h

25h

26h

27h

28h

60h

61h

62h

63h

64h

65h

66h

67h

68h

IN0 reading

IN1 reading

IN2 reading

IN3 reading

IN4 reading

-IN5 reading

-IN6 reading

Temperature reading

FAN1 reading

www.national.com

28

Functional Description (Continued)

Address A6–A0 with

Address A6–A0

Description

Auto-Increment

Note: This location stores the number of counts of the internal clock per

revolution.

29h

2Ah

69h

6Ah

FAN2 reading

Note: This location stores the number of counts of the internal clock per

revolution.

FAN3 reading

Note: This location stores the number of counts of the internal clock per

revolution.

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

IN0 High Limit

IN0 Low Limit

IN1 High Limit

IN1 Low Limit

IN2 High Limit

IN2 Low Limit

IN3 High Limit

IN3 Low Limit

IN4 High Limit

IN4 Low Limit

-IN5 High Limit

-IN5 Low Limit

-IN6 High Limit

-IN6 Low Limit

Over Temperature Limit (High)

Temperature Hysteresis Limit (Low)

FAN1 Fan Count Limit

Note: It is the number of counts of the internal clock for the Low Limit of

the fan speed.

3Ch

3Dh

7Ch

7Dh

FAN2 Fan Count Limit

Note: It is the number of counts of the internal clock for the Low Limit of

the fan speed.

FAN3 Fan Count Limit

Note: It is the number of counts of the internal clock for the Low Limit of

the fan speed.

3E–3Fh

7E–7Fh

Reserved

Note: Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when

voltages go below the low limits.

>

For voltage input high limits, the device is doing comparison. For low limits, however, it is doing ≤ comparison.

29

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Typical Application

DS012873-22

FIGURE 13. In this PC application the LM78 monitors temperature, fan speed for 3 fans, and 7 power

supply voltages. It also monitors the O.S. Output of up to 8 LM75 digital temperature sensors as well

as an optical chassis intrusion detector.

www.national.com

30

Physical Dimensions inches (millimeters) unless otherwise noted

44-Lead (10 mm x 10 mm) Molded Plastic Quad Flatpak

Order Number LM78CCVF-J

NS Package Number VGZ44A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

型号:	LM78CCVF
生命周期：	Contact Manufacturer
IHS 制造商：	ROCHESTER ELECTRONICS LLC
包装说明：	QFP,
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.56
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-PQFP-G44
长度：	10 mm
功能数量：	1
端子数量：	44
最高工作温度：	100 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP
封装形状：	SQUARE
封装形式：	FLATPACK
座面最大高度：	2.45 mm
最大供电电压 (Vsup)：	5.75 V
最小供电电压 (Vsup)：	4.25 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
温度等级：	OTHER
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
宽度：	10 mm
Base Number Matches：	1

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