LTC2153CUJ-14#TRPBF中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

LTC2153-12

12-Bit 310Msps ADC

FeaTures

DescripTion

The LTC^®2153-12 is a 310Msps 12-bit A/D converter

designed for digitizing high frequency, wide dynamic

rangesignals.Itisperfectfordemandingcommunications

applications with AC performance that includes 67.6dB

SNR and 88dB spurious free dynamic range (SFDR). The

1.25GHz input bandwidth allows the ADC to undersample

high frequencies with good performance. The latency is

only six clock cycles.

n

67.6dBFS SNR

n

88dB SFDR

n

Low Power: 378mW Total

n

Single 1.8V Supply

n

DDR LVDS Outputs

n

1.32V Input Range

P-P

n

1.25GHz Full Power Bandwidth S/H

Optional Clock Duty Cycle Stabilizer

Low Power Sleep and Nap Modes

Serial SPI Port for Configuration

Pin-Compatible 12-Bit Versions

40-Lead (6mm × 6mm) QFN Package

DC specs include 0.6LSB INL (typ), 0.1LSB DNL (typ)

and no missing codes over temperature. The transition

noise is 0.6LSB

.

RMS

The digital outputs are double data rate (DDR) LVDS.

applicaTions

+

–

The ENC and ENC inputs can be driven differentially with

asinewave,PECL,LVDS,TTL,orCMOSinputs.Anoptional

clock duty cycle stabilizer allows high performance at full

speed for a wide range of clock duty cycles.

n

Communications

n

Cellular Basestations

n

Software Defined Radios

n

Medical Imaging

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

High Definition Video

n

Testing and Measurement Instruments

Typical applicaTion

LTC2153-12 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 310Msps

V

DD

0

OV

DD

–20

–40

D10_11

12-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

D0_1

–60

OGND

CLOCK/DUTY

CYCLE

CONTROL

–80

CLOCK

GND

–100

–120

215312 TA01a

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

215312 TA01b

215312fa

For more information www.linear.com/LTC2153-12

1

LTC2153-12

absoluTe MaxiMuM raTings pin conFiguraTion

(Notes 1, 2)

TOP VIEW

Supply Voltage

V , OV ................................................ –0.3V to 2V

DD

Analog Input Voltage

+

–

40 39 38 37 36 35 34 33 32 31

A

, A , PAR/SER,

IN

V

1

2

3

4

5

6

7

8

9

30

29

28

OV

DD

+

SENSE (Note 3)........................ –0.3V to (V + 0.2V)

DD

D6_7

Digital Input Voltage

–

GND

+

–

ENC , ENC (Note 3)................ –0.3V to (V + 0.3V)

+

–

DD

A

27 CLKOUT

IN

–

CS, SDI, SCK (Note 4)........................... –0.3V to 3.9V

41

GND

A

26 CLKOUT

+

IN

SDO (Note 4)............................................. –0.3V to 3.9V

GND

SENSE

VREF

25

D4_5

–

+

–

24 D4_5

23

Digital Output Voltage................ –0.3V to (OV + 0.3V)

DD

D2_3

22 D2_3

Operating Temperature Range

VCM

LTC2153C ................................................ 0°C to 70°C

LTC2153I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

GND 10

21

OGND

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

= 150°C, θ = 33°C/W

JA

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC2153CUJ-12#PBF

LTC2153IUJ-12#PBF

TAPE AND REEL

LTC2153CUJ-12#TRPBF LTC2153UJ-12

LTC2153IUJ-12#TRPBF LTC2153UJ-12

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

215312fa

For more information www.linear.com/LTC2153-12

2

LTC2153-12

converTer characTerisTics _{The l denotes the specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

–1.8

–0.7

–12

0.6

0.1

5

1.8

0.7

12

LSB

mV

Gain Error

Internal Reference

External Reference

1.5

1

%FS

l

–4

3

Offset Drift

20

µV/°C

Full-Scale Drift

Internal Reference

External Reference

30

10

ppm/°C

Transition Noise

0.6

LSB

RMS

analog inpuT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.74V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

V

Analog Input Range (A – A

)

1.32

V

P-P

IN

DD

+

–

l

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

V

– 20mV

V

CM

V + 20mV

CM

V

IN(CM)

SENSE

IN

CM

External Voltage Reference Applied to SENSE External Reference Mode

1.230

–1

1.250

1.270

V

µA

ns

+

–

I

t

Analog Input Leakage Current

0 < A , A < V , No Encode

1

IN1

IN

DD

PAR/SER Input Leakage Current

SENSE Input Leakage Current

0 < PAR/SER < V

–1

IN2

1.23V < SENSE < 1.27V

–1

IN3

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

1

AP

0.15

75

ps

RMS

JITTER

CMRR

BW-3B

dB

1250

MHz

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

65.8

70

TYP

MAX

UNITS

SNR

Signal-to-Noise Ratio

15MHz Input

70MHz Input

140MHz Input

67.6

67.1

67.0

dBFS

l

SFDR

Spurious Free Dynamic Range 2nd or 3rd

Harmonic

15MHz Input

70MHz Input

140MHz Input

88

85

80

dBFS

Spurious Free Dynamic Range 4th Harmonic

or Higher

15MHz Input

70MHz Input

140MHz Input

98

95

90

dBFS

80

S/(N+D) Signal-to-Noise Plus Distortion Ratio

15MHz Input

70MHz Input

140MHz Input

67.1

67.0

66.9

dBFS

65

215312fa

For more information www.linear.com/LTC2153-12

3

LTC2153-12

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

MAX

UNITS

V

CM

Output Voltage

I

0.439 •

– 18mV

0.439 •

V

OUT

V

DD

V

DD

V

+ 18mV

DD

V

Output Temperature Drift

Output Resistance

Output Voltage

37

4

ppm/°C

Ω

CM

–1mA < I

< 1mA

CM

OUT

I

= 0

1.225

1.250

30

1.275

V

REF

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400µA < I

< 1mA

7

OUT

1.74V < V < 1.9V

0.6

mV/V

DD

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

(Note 9)

MIN

1.74

TYP

1.8

MAX

1.9

UNITS

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Digital Supply Current

V

DD

OV

DD

(Note 9)

1.8

1.9

I

182

205

mA

VDD

OVDD

l

1.75mA LVDS Mode

3.5mA LVDS Mode

28

48.5

34

52

mA

l

P

Power Dissipation

Sleep Mode Power

Nap Mode Power

1.75mA LVDS Mode

3.5mA LVDS Mode

378

415

430

463

mW

DISS

SLEEP

NAP

Clock Disabled

<5

mW

Clocked at f

S(MAX)

Clocked at f

124

mW

S(MAX)

DigiTal inpuTs anD ouTpuTs ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

l

V

Differential Input Voltage

(Note 8)

0.2

1.1

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

1.5

R

Input Resistance

Input Capacitance

(See Figure 2)

(Note 8)

10

2

kΩ

pF

IN

C

IN

DIGITAL INPUTS (CS, SDI, SCK)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

= 1.8V

0.6

10

I

IN

= 0V to 3.6V

–10

µA

pF

C

Input Capacitance

(Note 8)

3

200

4

IN

SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

= 1.8V, SDO = 0V

DD

Ω

µA

pF

OL

l

I

SDO = 0V to 3.6V

(Note 8)

–10

10

OH

C

OUT

215312fa

For more information www.linear.com/LTC2153-12

4

LTC2153-12

DigiTal inpuTs anD ouTpuTs ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

DIGITAL DATA OUTPUTS

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

OD

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

mV

l

V

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

100

1.375

V

Ω

OS

R

Termination Enabled, OV = 1.8V

TERM

DD

TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

f

t

Sampling Frequency

ENC Low Time (Note 8)

(Note 9)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

10

1.5

1.2

310

50

MHz

ns

S

L

l

1.61

l

t

H

ENC High Time (Note 8)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

1.5

1.2

1.61

50

ns

DIGITAL DATA OUTPUTS

MIN

TYP

MAX

UNITS

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.7

2

2.3

ns

D

L

C = 5pF (Note 8)

L

1.3

0.3

6

1.6

0.4

2

0.55

6

ns

C

t – t (Note 8)

SKEW

D

C

Cycles

SPI Port Timing (Note 8)

l

t

SCK Period

Write Mode

Readback Mode C = 20pF, R

40

250

ns

SCK

= 2k

PULLUP

SDO

l

t

CS to SCK Set-Up Time

SCK to CS Hold Time

SDI Set-Up Time

5

ns

–

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Readback Mode, C

= 20pF, R

= 2k

125

SDO

PULLUP

+

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 5: V = OV = 1.8V, f

= 310MHz, differential ENC /ENC =

P-P

DD

SAMPLE

2V sine wave, input range = 1.32V with differential drive, unless

P-P

otherwise noted.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5LSB when the

output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s

complement output mode.

Note 3: When these pin voltages are taken below GND or above V , they

DD

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above V without latchup.

DD

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above V

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 8: Guaranteed by design, not subject to test.

Note 9: Recommended operating conditions.

DD

215312fa

For more information www.linear.com/LTC2153-12

5

LTC2153-12

Typical perForMance characTerisTics

LTC2153-12: Integral Nonlinearity

(INL)

LTC2153-12: Differential

Nonlinearity (DNL)

LTC2153-12: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 310Msps

0.50

0.25

0

2.0

1.5

0

–20

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.25

–0.50

–100

–120

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

4095

0

4095

OUTPUT CODE

215312 G02

215312 G01

215312 G03

LTC2153-12: 32K Point FFT,

f_IN= 70MHz, –1dBFS, 310Msps

LTC2153-12: 32K Point FFT,

f_IN= 150MHz, –1dBFS, 310Msps

LTC2153-12: 32K Point FFT,

f_IN= 185MHz, –1dBFS, 310Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

215312 G05

215312 G04

215312 G06

LTC2153-12: 32K Point FFT,

f_IN= 223MHz, –1dBFS, 310Msps

LTC2153-12: 32K Point FFT,

f_IN= 383MHz, –1dBFS, 310Msps

LTC2153-12: 32K Point FFT,

f_IN= 421MHz, –1dBFS, 310Msps

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

215312 G08

215312 G09

215312 G07

215312fa

For more information www.linear.com/LTC2153-12

6

LTC2153-12

Typical perForMance characTerisTics

LTC2153-12: 32K Point FFT,

f_IN= 907MHz, –1dBFS, 310Msps

LTC2153-12: 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 310Msps

LTC2153-12: 32K Point FFT,

f_IN= 567MHz, –1dBFS, 310Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

20 40 60 80 100 120 140

FREQUENCY (MHz)

20 40 60 80 100 120 140

FREQUENCY (MHz)

0

215312 G10

215312 G11

215312 G12

LTC2153-12: SNR vs Input Level,

f_IN= 70MHz, 1.32V Range,

310Msps

LTC2153-12: SFDR vs Input Level,

f_IN= 70MHz, 1.32V Range, 310Msps

LTC2153-12: Shorted Input Histogram

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

dBFS

120

100

80

60

40

20

0

70

60

50

40

30

20

10

0

dBFS

dBc

–50 –40 –30 –20 –10

0

–50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

–90 –80 –70 –60

–70 –60

2052

2056

2060

2064

AMPLITUDE (dBFS)

OUTPUT CODE

215312 G13

215312 G14

215312 G15

LTC2153-12: SFDR vs Input

Frequency, –1dBFS, 1.32V Range,

310Msps

LTC2153-12: SNR vs Input

Frequency, –1dBFS, 1.32V Range,

310Msps

75

90

80

70

60

50

40

30

20

10

0

70

65

60

55

50

45

40

0

200 300 400 500 600 700 800 900 1000

100

0

200 300 400 500 600 700 800 900 1000

100

INPUT FREQUENCY (MHz)

215312 G17

215312 G16

215312fa

For more information www.linear.com/LTC2153-12

7

LTC2153-12

Typical perForMance characTerisTics

LTC2153-12: I_OVDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2153-12: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2153-12: Frequency Response

200

190

180

170

160

150

140

130

60

55

50

45

40

35

30

25

20

15

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

LVDS CURRENT

3.5mA

LVDS CURRENT

1.75mA

62

124

186

248

310

50

100 150 200 250 300

0

100

1000

SAMPLE RATE (Msps)

INPUT FREQUENCY (MHz)

215312 G18

215312 G19

215312 G20

pin FuncTions

DD

ground with 0.1µF ceramic capacitor. Pins 1, 2 can share

a bypass capacitor.

–

V

(Pins 1, 2): 1.8V Analog Power Supply. Bypass to

ENC (Pin 12): Encode Complement Input. Conversion

starts on the falling edge.

NC (Pins 16, 17): Not Connected.

GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC

Power Ground. The exposed pad must be soldered to the

PCB ground.

OV (Pins 20, 30): 1.8V Output Driver Supply. Bypass

DD

eachpintogroundwithseparate0.1µFceramiccapacitors.

OGND (Pin 21): LVDS Driver Ground.

+

A

IN

A

IN

(Pin 4): Positive Differential Analog Input.

(Pin 5): Negative Differential Analog Input.

SDO (Pin 36): Serial Interface Data Output. In serial

programming mode, (PAR/SER = 0V), SDO is the optional

serialinterfacedataoutput. DataonSDOisreadbackfrom

themodecontrolregistersandcanbelatchedonthefalling

edge of SCK. SDO is an open-drain N-channel MOSFET

output that requires an external 2k pull-up resistor from

1.8V to 3.3V. If readback from the mode control registers

is not needed, the pull-up resistor is not necessary and

SDO can be left unconnected.

–

SENSE (Pin 7): Reference Programming Pin. Connecting

SENSE to V selects the internal reference and a 0.66V

DD

input range. An external reference between 1.23V and

1.27V applied to SENSE selects an input range of 0.528

• V

.

SENSE

V

(Pin 8): Reference Voltage Output. Bypass to ground

REF

with a 2.2µF ceramic capacitor. Nominally 1.25V.

SDI (Pin 37): Serial Interface Data Input. In serial pro-

gramming mode, (PAR/SER = 0V), SDI is the serial

interface data input. Data on SDI is clocked into the mode

control registers on the rising edge of SCK. In parallel

V

(Pin 9): Common Mode Bias Output; nominally equal

CM

to 0.439 • V . V should be used to bias the common

DD CM

mode of the analog inputs. Bypass to ground with a 0.1µF

ceramic capacitor.

programming mode (PAR/SER = V ), SDI selects 3.5mA

DD

+

ENC (Pin 11): Encode Input. Conversion starts on the

rising edge.

or 1.75mA LVDS output current (see Table 2).

215312fa

For more information www.linear.com/LTC2153-12

8

LTC2153-12

pin FuncTions

SCK (Pin 38): Serial Interface Clock Input. In serial

programming mode, (PAR/SER = 0V), SCK is the se-

rial interface clock input. In parallel programming mode

LVDS Outputs (DDR LVDS)

The following pins are differential LVDS outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDS output pair.

(PAR/SER = V ), SCK controls the sleep mode (see

DD

Table 2).

CS (Pin 39): Serial Interface Chip Select Input. In serial

programming mode, (PAR/SER = 0V), CS is the serial

interfacechipselectinput. WhenCSislow, SCKisenabled

for shifting data on SDI into the mode control registers.

–

+

–

+

D

0_1

/D

0_1

toD

/D

10_11

(Pins18/19,22/23,24/25,

10_11

28/29, 31/32, 33/34): Double-Data Rate Digital Outputs.

Two data bits are multiplexed onto each differential output

pair. The even data bits (D0, D2, D4, D6, D8, D10) appear

when CLKOUT is low. The odd data bits (D1, D3, D5, D7,

D9, D11) appear when CLKOUT is high.

In parallel programming mode (PAR/SER = V ), CS

+

DD

controls the clock duty cycle stabilizer (see Table 2).

+

PAR/SER (Pin 40): Programming Mode Selection Pin.

Connect to ground to enable the serial programming

mode. CS, SCK, SDI and SDO become a serial interface

–

+

CLKOUT , CLKOUT (Pins 26, 27): Data Output Clock.

The digital outputs normally transition at the same time

+

as the falling and rising edges of CLKOUT . The phase of

that control the A/D operating modes. Connect to V to

DD

+

CLKOUT canalsobedelayedrelativetothedigitaloutputs

enabletheparallelprogrammingmodewhereCS,SCKand

SDI become parallel logic inputs that control a reduced

set of the A/D operating modes. PAR/SER should be con-

by programming the mode control registers.

–

+

OF , OF (Pins 14, 15): Over/Underflow Digital Output.

OF is high when an overflow or underflow has occurred.

nected directly to ground or the V of the part and not

DD

+

This underflow is valid only when CLKOUT is low. In the

be driven by a logic signal.

second half clock cycle, the overflow is set to 0.

FuncTional block DiagraM

V

DD

OV

DD

D10_11

12-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

D0_1

V

CM

V

CM

0.1µF

OGND

BUFFER

GND

CLOCK

CS

CLOCK/DUTY

CYCLE CONTROL

SCK

SDI

SPI

SDO

PAR/SER

V

REF

2.2µF

1.25V

REFERENCE

GND

RANGE

SELECT

SENSE

215312 F01

Figure 1. Functional Block Diagram

215312fa

For more information www.linear.com/LTC2153-12

9

LTC2153-12

TiMing DiagraMs

Double Data Rate Output Timing, All Outputs Are Differential LVDS

t

AP

N

N + 3

N + 2

N + 1

t

H

t

L

–

+

ENC

+

–

CLKOUT

t

C

–

+

D0_1

D0

N-6

D1

N-6

D0

N-5

D1

D0

N-4

D1

N-4

N-5

t

D

–

+

D10_11

D10

N-6

D11

N-6

D10

D11

N-5

D10

N-4

D11

N-4

N-5

–

+

OF

N-6

INVALID OF

INVALID

N-5

N-4

OF

215312 TD01

t

SKEW

SPI Port Timing (Readback Mode)

t

S

t

DS

t

DH

t

H

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

215312 TD02

HIGH IMPEDANCE

215312fa

For more information www.linear.com/LTC2153-12

10

LTC2153-12

applicaTions inForMaTion

CONVERTER OPERATION

INPUT DRIVE CIRCUITS

Input Filtering

The LTC2153-12 is a 12-bit 310Msps A/D converter

powered by a single 1.8V supply. The analog inputs must

be driven differentially. The encode inputs should be

driven differentially for optimal performance. The digital

outputsaredoubledatarateLVDS. Additionalfeaturescan

be chosen by programming the mode control registers

through a serial SPI port.

If possible, there should be an RC lowpass filter right at

the analog inputs. This lowpass filter isolates the drive

circuitryfromtheA/Dsample-and-holdswitching,andalso

limits wide band noise from the drive circuitry. Figure 3

shows an example of an input RC filter. The RC compo-

nent values should be chosen based on the application’s

specific input frequency.

ANALOG INPUT

The analog input is a differential CMOS sample-and-

hold circuits (Figure 2). The inputs must be driven differ-

Transformer-Coupled Circuits

Figure 3 shows the analog input being driven by an RF

transformer with the common mode supplied through a

entially around a common mode voltage set by the V

CM

output pin, which is nominally 0.439 • V . For the 1.32V

DD

pair of resistors via the V pin.

CM

input range, the input should swing from V – 0.33V to

CM

At higher input frequencies a transmission line balun

transformer(Figures4and5)hasbetterbalance,resulting

in lower A/D distortion.

V

+ 0.33V. There should be 180° phase difference

CM

between the inputs.

10Ω

V

CM

0.1µF

10pF

LTC2153-12

+

0.1µF

T1

1:1

4.7Ω

LTC2153-12

IN

A

IN

V

DD

25Ω

R

ON

2pF

20Ω

0.1µF

4.7Ω

+

–

A

IN

–

2pF

IN

V

DD

T1: MACOM ETC1-1T

215312 F03

R

20Ω

ON

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

IN

V

DD

10Ω

V

CM

1.2V

10k

0.1µF

LTC2153-12

0.1µF

4.7Ω

+

IN

A

IN

+

–

ENC

45Ω

100Ω

ENC

0.1µF

4.7Ω

0.1µF

–

A

IN

215312 F02

T2: MABA

007159-000000

T1: WBC1-1L

215312 F04

Figure 2. Equivalent Input Circuit. Only One

of Two Analog Channels Is Shown

Figure 4. Recommended Front-End Circuit for

Input Frequencies from 15MHz to 150MHz

215312fa

For more information www.linear.com/LTC2153-12

11

LTC2153-12

applicaTions inForMaTion

Amplifier Circuits

V

CM

0.1µF

Figure 6 shows the analog input being driven by a high

speed differential amplifier. The output of the amplifier is

AC coupled to the A/D so the amplifier’s output common

mode voltage can be optimally set to minimize distortion.

10Ω

LTC2153-12

0.1µF

4.7Ω

+

IN

A

IN

45Ω

100Ω

0.1µF

At very high frequencies an RF gain block will often have

lower distortion than a differential amplifier. If the gain

block is single-ended, then a transformer circuit (Figures

3 and 5) should convert the signal to differential before

driving the A/D. The A/D cannot be driven single-ended.

0.1µF

4.7Ω

–

A

IN

T1: MABA

007159-000000

215312 F05

Figure 5. Recommended Front-End Circuit for

Input Frequencies from 150MHz to 900MHz

Reference

The LTC2153-12 has an internal 1.25V voltage reference.

For a 1.32V input range with internal reference, connect

SENSE to V . For a 1.32V input range with an external

DD

reference, apply a 1.25V reference voltage to SENSE

(Figure 7).

V

CM

0.1µF

Encode Input

50Ω

LTC2153-12

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board.

3pF

0.1µF

4.7Ω

+

INPUT

A

IN

3pF

0.1µF

4.7Ω

–

IN

The encode inputs are internally biased to 1.2V through

10k equivalent resistance (Figure 8). If the common mode

of the driver is within 1.1V to 1.5V, it is possible to drive

the encode inputs directly. Otherwise a transformer or

coupling capacitors are needed (Figures 9 and 10). The

maximum (peak) voltage of the input signal should never

215312 F06

Figure 6. Front-End Circuit Using a High

Speed Differential Amplifier

exceed V +0.1V or go below –0.1V.

DD

LTC2153-12

V

DD

LTC2153-12

5Ω

V

REF

1.25V

1.2V

2.2µF

10k

+

–

ENC

SCALER/

BUFFER

ADC

REFERENCE

SENSE

DETECTOR

215312 F07

215312 F08

Figure 8. Equivalent Encode Input Circuit

Figure 7. Reference Circuit

215312fa

For more information www.linear.com/LTC2153-12

12

LTC2153-12

applicaTions inForMaTion

Clock Duty Cycle Stabilizer

DIGITAL OUTPUTS

For good performance the encode signal should have a

50% ( 5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintainaconstant50%internaldutycycle.Thedutycycle

stabilizer is enabled via SPI Register A2 (see Table 3) or

by CS in parallel programming mode.

ThedigitaloutputsaredoubledatarateLVDSsignals.Two

data bits are multiplexed and output on each differential

+

output pair. There are six LVDS output pairs, D0_1 /

–

+

–

D0_1 through D10_11 /D10_11 . Overflow (OF /OF )

–

and the data output clock (CLKOUT /CLKOUT ) each have

an LVDS output pair.

By default the outputs are standard LVDS levels: 3.5mA

outputcurrentanda1.25Voutputcommonmodevoltage.

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. In

this case, care should be taken to make the clock a 50%

( 5%) duty cycle.

LTC2153-12

V

DD

1.2V

10k

0.1µF

50Ω

100Ω

0.1µF

50Ω

T1: MACOM

ETC1-1-13

215312 F09

Figure 9. Sinusoidal Encode Drive

LTC2153-12

V

DD

1.2V

10k

0.1µF

+

–

ENC

PECL OR

LVDS INPUT

100Ω

0.1µF

ENC

215312 F10

Figure 10. PECL or LVDS Encode Drive

215312fa

For more information www.linear.com/LTC2153-12

13

LTC2153-12

applicaTions inForMaTion

Programmable LVDS Output Current

bits. When CLKINV is set to 0 in the SPI register A2, the

+

OF signal is valid when CLKOUT is low, as shown in the

The default output driver current is 3.5mA. This current

can be adjusted by serially programming mode control

register A3 (see Table 3). Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

Timing Diagram.

Phase Shifting the Output Clock

To allow adequate set-up and hold time when latching the

+

Optional LVDS Driver Internal Termination

output data, the CLKOUT signal may need to be phase

shifted relative to the data output bits. Most FPGAs have

this feature; this is generally the best place to adjust the

timing.

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

beenabledbyseriallyprogrammingmodecontrolregister

A3. The internal termination helps absorb any reflections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is doubled to maintain the same output voltage swing.

+

Alternatively, the ADC can also phase shift the CLKOUT /

–

CLKOUT signals by serially programming mode control

register A2. The output clock can be shifted by 0°, 45°,

90°, or 135°. To use the phase shifting feature the clock

duty cycle stabilizer must be turned on. Another con-

+

trol register bit can invert the polarity of CLKOUT and

–

Overflow Bit

CLKOUT , independently of the phase shift. The combina-

tion of these two features enables phase shifts of 45° up

to 315° (Figure 11).

The overflow output bit (OF) outputs a logic high when

the analog input is either overranged or underranged.

The overflow bit has the same pipeline latency as the data

+

ENC

D0-D13, OF

MODE CONTROL BITS

PHASE

SHIFT

CLKINV

0

CLKPHASE1 CLKPHASE0

0°

0

1

0

1

0

1

0

1

0

1

0

1

45°

90°

0

1

135°

180°

225°

270°

315°

+

CLKOUT

215312 F11

Figure 11. Phase Shifting CLKOUT

215312fa

For more information www.linear.com/LTC2153-12

14

LTC2153-12

applicaTions inForMaTion

DATA FORMAT

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The LSB, OF and CLKOUT out-

puts are not affected. The output randomizer is enabled

by serially programming mode control register A4.

Table 1. Output Codes vs Input Voltage

+

–

A

– A

D11-D0

(OFFSET BINARY)

D11-D0

(2’s COMPLEMENT)

IN

(1.32V Range) OF

>0.66V

1

0

1

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

+0.66V

Alternate Bit Polarity

+0.6596777V

+0.0003222V

+0.000000V

–0.0003222V

–0.0006445V

–0.6596777V

–0.66V

Another feature that may reduce digital feedback on the

circuit board is the alternate bit polarity mode. When this

mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,

D11) are inverted before the output buffers. The even

bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not

affected. This can reduce digital currents in the circuit

board ground plane and reduce digital noise, particularly

for very small analog input signals.

< –0.66V

Digital Output Randomizer

The digital output is decoded at the receiver by inverting

the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit

polaritymodeisindependentofthedigitaloutputrandom-

izer—either both or neither function can be on at the same

time. The alternate bit polarity mode is enabled by serially

programming mode control register A4.

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

PC BOARD

CLKOUT

OF

FPGA

CLKOUT

OF

D11

D11/D0

D10/D0

LTC2153-12

D11

D10

D10/D0

D1/D0

D0

•

RANDOMIZER

ON

D1

D1/D0

D0

D1

D0

215312 F13

215312 F12

Figure 13. Decoding a Randomized Digital Output Signal

Figure 12. Functional Equivalent of Digital Output Randomizer

215312fa

For more information www.linear.com/LTC2153-12

15

LTC2153-12

applicaTions inForMaTion

Digital Output Test Patterns

Nap Mode

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes that force the A/D data

outputs (OF, D11 to D0) to known values:

In nap mode the A/D core is powered down while the

internal reference circuits stay active, allowing faster

wake-up. Recovering from nap mode requires at least

100 clock cycles.

All 1s: All outputs are 1

All 0s: All outputs are 0

Wake-up time from nap mode is guaranteed only if the

clock is kept running, otherwise sleep mode wake-up

conditions apply.

Alternating: Outputs change from all 1s to all 0s on

alternating samples

Nap mode is enabled by setting register A1 in the serial

programming mode.

Checkerboard: Outputs change from 1010101010101

to 0101010101010 on alternating samples.

DEVICE PROGRAMMING MODES

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes:

2’s complement, randomizer, alternate-bit polarity.

The operating modes of the LTC2153-12 can be pro-

grammed by either a parallel interface or a simple serial

interface. The serial interface has more flexibility and

can program all available modes. The parallel interface

is more limited and can only program some of the more

commonly used modes.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A3. All digital outputs includ-

ing OF and CLKOUT are disabled. The high impedance

disabled state is intended for long periods of inactivity,

it is not designed for multiplexing the data bus between

multiple converters.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to V . The CS, SCK and SDI pins are binary logic

DD

inputs that set certain operating modes. These pins can

be tied to V or ground, or driven by 1.8V, 2.5V, or 3.3V

DD

Sleep Mode

CMOS logic. Table 2 shows the modes set by CS, SCK

and SDI.

The A/D may be placed in sleep mode to conserve power.

In sleep mode the entire A/D converter is powered down,

resulting in < 5mW power consumption. If the encode

input signal is not disabled, the power consumption will

behigher(upto5mWat310Msps).Sleepmodeisenabled

by mode control register A1 (serial programming mode),

or by SCK (parallel programming mode).

Table 2. Parallel Programming Mode Control Bits (PAR/SER = V_DD

)

DESCRIPTION

CS

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

Power Down Control Bit

SCK

SDI

0 = Normal Operation

The amount of time required to recover from sleep mode

1 = Sleep Mode (entire ADC is powered down)

LVDS Current Selection Bit

depends on the size of the bypass capacitor on V . For

REF

the suggested value in Figure 1, the A/D will stabilize after

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

0.1ms + 2500 • t where t is the period of the sampling

p

clock.

215312fa

For more information www.linear.com/LTC2153-12

16

LTC2153-12

applicaTions inForMaTion

Serial Programming Mode

GROUNDING AND BYPASSING

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D control registers.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

The LTC2153-12 requires a printed circuit board with a

clean unbroken ground plane in the first layer beneath the

ADC. A multilayer board with an internal ground plane is

recommended. Layoutforthe printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first sixteen rising edges

of SCK. Any SCK rising edges after the first sixteen are

ignored.ThedatatransferendswhenCSistakenhighagain.

High quality ceramic bypass capacitors should be used at

theV ,OV ,V ,V pins.Bypasscapacitorsmustbe

DD

DD CM REF

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

located as close to the pins as possible. Size 0402 ceramic

capacitors are recommended. The traces connecting the

pins and bypass capacitors must be kept short and should

be made as wide as possible.

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the Timing

Diagrams). During a readback command the register is

not updated and data on SDI is ignored.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and readback is not needed,

then SDO can be left floating and no pull-up resistor is

needed.Table 3showsamapofthemodecontrolregisters.

HEAT TRANSFER

Most of the heat generated by the LTC2153-12 is trans-

ferred from the die through the bottom-side exposed pad

and package leads onto the printed circuit board. For good

electricalandthermalperformance,theexposedpadmust

be soldered to a large grounded pad on the PC board. This

pad should be connected to the internal ground planes by

an array of vias.

Software Reset

If serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset it is neces-

sary to write 1 in register A0 (Bit D7). After the reset is

complete, Bit D7 is automatically set back to zero. This

register is write-only.

215312fa

For more information www.linear.com/LTC2153-12

17

LTC2153-12

applicaTions inForMaTion

Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X indicates an unused bit that is read back as 0

REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only

D7

D6

X

D5

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

X

Bit 7

RESET

0 = Reset Disabled

Software Reset Bit

1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.

Bits 6-0

Unused Bits

REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

0

D0

0

SLEEP

NAP

Bits 7-4

Unused Bit

SLEEP

Bit 3

0 = Normal Operation

1 = Power Down Entire ADC

Bit 2

NAP

0 = Normal Mode

1 = Low Power Mode

Bit 1-0

Must be set to 0

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

D0

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused Bit

CLKINV

Bit 3

Output Clock Invert Bit

0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1:CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (as shown in the Timing Diagrams)

+

–

01 = CLKOUT /CLKOUT delayed by 45° (Clock Period • 1/8)

10 = CLKOUT /CLKOUT delayed by 90° (Clock Period • 1/4)

11 = CLKOUT /CLKOUT delayed by 135° (Clock Period • 3/8)

Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.

Bit 0

DCS

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

215312fa

For more information www.linear.com/LTC2153-12

18

LTC2153-12

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REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

X

D6

X

D5

X

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

Bits 7-5

Unused Bit

Bits 4-2

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 1

Bit 0

TERMON

0 = Internal Termination Off

1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0

LVDS Internal Termination Bit

OUTOFF

Digital Output Mode Control Bits

0 = Digital Outputs Are Enabled

1 = Digital Outputs Are Disabled (High Impedance)

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

0

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

DTESTON

RAND

TWOSCOMP

Bits 7-5

OUTTEST2:OUTTEST0

000 = All Digital Outputs = 0

001 = All Digital Outputs = 1

Digital Output Test Pattern Bits

010 = Alternating Output Pattern. OF, D11-D0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111

100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010

Note 1: Other bit combinations are not used.

Bit 4

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On

Bit 3

Bit 2

Must Be Set to 0

DTESTON

0 = Normal Mode

1 = Enable the Digital Output Test Patterns

Enable the digital output test patterns (set by Bits 7-5)

Bit 1

Bit 0

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

215312fa

For more information www.linear.com/LTC2153-12

19

LTC2153-12

applicaTions inForMaTion

215312 F15

215312 F16

215312 F14

Silkscreen Top

Inner Layer 1

Inner Layer 2

215312 F17

215312 F18

Inner Layer 3

Inner Layer 4

215312 F19

215312 F20

Inner Layer 5

Bottom Layer

215312fa

For more information www.linear.com/LTC2153-12

20

LTC2153-12

Typical applicaTions

2153-12 Schematic

SDO

SDI

SCK

CS

PAR/SER

V

DD

0.2µF

R9

1k

OV

DD

TP3

0.1µF

SENSE

C13

2.2µF

1

2

V

30

29

28

27

26

25

24

23

22

21

DD

OV

DD

+

–

D6_7

R14

10Ω

3

GND

–

+

–

+

–

+

–

4

+

–

A

INA

+

–

CLKOUT

D4_5

CLKOUT

5

–

R16

100Ω

LTC2153-12

6

GND

R19

10Ω

+

SENSE

C16

D4_5

7

SENSE

–

D4_5

8

V

REF

+

D2_3

9

V

CM

–

D2_3

2.2µF

10

41

GND

10Ω

OGND

V

CM

C21

0.1µF

OV

DD

0.1µF

215312 TA02

0.1µF

100Ω

0.1µF

+

–

CLK

215312fa

For more information www.linear.com/LTC2153-12

21

LTC2153-12

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 0.05

6.50 0.05

5.10 0.05

4.42 0.05

4.50 0.05

(4 SIDES)

4.42 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.115

TYP

6.00 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 ¥ 45

CHAMFER

4.42 0.10

4.50 REF

(4-SIDES)

4.42 0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

215312fa

For more information www.linear.com/LTC2153-12

22

LTC2153-12

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

12/14 Changed the pipeline latency to 6

Updated G15

5 and 10

7

215312fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2153-12

23

LTC2153-12

Typical applicaTion

LTC2153-12: 32K Point 2-Tone FFT,

V

DD

f_IN= 71MHz and 69MHz, 310Msps

OV

DD

0

D10_11

12-BIT

PIPELINED

ADC

•

–20

–40

–60

–80

CORRECTION

LOGIC

DDR

LVDS

ANALOG

INPUT

OUTPUT

DRIVERS

S/H

•

D0_1

OGND

CLOCK/DUTY

CYCLE

CONTROL

CLOCK

GND

215312 TA03a

–100

–120

0

40

60

80

100 120

20

FREQUENCY (MHz)

215312 TA03b

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC2208

16-Bit, 130Msps, 3.3V ADC, LVDS Outputs

14-Bit, 310Msps, 1.8V Dual ADC, DDR LVDS Outputs

1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package

724mW, 68.8dB SNR, 88dB SFDR, 64-Lead QFN Package

LTC2158-14

LTC2157-14/LTC2156-14/ 14-Bit Dual, 250Msps/210Msps/170Msps,

LTC2155-14 1.8V Dual ADC, DDR LVDS Outputs

605mW/565mW/511mW, 70dB SNR, 90dB SFDR, 9mm × 9mm

64-Lead QFN Package

LTC2152-14/LTC2151-14/ 14-Bit, 250Msps/210Msps/170Msps,

338mW/316mW/290mW, 70dB SNR, 90dB SFDR, 6mm × 6mm

40-Lead QFN Package

LTC2150-14

1.8V Single ADC, DDR LVDS Outputs

LTC2153-14

14-Bit, 310Msps 1.8V Single ADC, DDR LVDS Outputs

401mW, 68.8dB SNR, 88dB SFDR, 6mm × 6mm 40-Lead

QFN Package

RF Mixers/Demodulators

LT5517

40MHz to 900MHz Direct Conversion Quadrature

Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5527

LT5575

400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,

50Ω Single-Ended RF and LO Ports

800MHz to 2.7GHz Direct Conversion Quadrature

Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator,

Integrated RF and LO Transformer

Amplifiers/Filters

LTC6409

10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA

Supply Current, 3mm × 2mm QFN Package

LTC6412

800MHz, 31dB Range, Analog-Controlled Variable

Gain Amplifier

Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,

10dB Noise Figure, 4mm × 4mm QFN-24 Package

LTC6420-20

1.8GHz Dual Low Noise, Low Distortion Differential ADC Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply

Drivers for 300MHz IF

Current per Amplifier, 3mm × 4mm QFN-20 Package

Receiver Subsystems

LTM9002

14-Bit Dual Channel IF/Baseband Receiver Subsystem

12-Bit Digital Predistortion Receiver

Integrated High Speed ADC, Passive Filters and Fixed Gain

Differential Amplifiers

LTM9003

Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to

3.8GHz Input Frequency Range

215312fa

LT 1214 REV A • PRINTED IN USA

24 ^{LinearTechnology Corporation}

●

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC2153-12

 LINEAR TECHNOLOGY CORPORATION 2012

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2153-12

型号:	LTC2153IUJ-12#PBF
Brand Name：	Linear Technology
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	LINEAR TECHNOLOGY CORP
零件包装代码：	QFN
包装说明：	HVQCCN, LCC40,.24SQ,20
针数：	40
制造商包装代码：	UJ
Reach Compliance Code：	compliant
ECCN代码：	3A001.A.5.A.3
HTS代码：	8542.39.00.01
风险等级：	4.45
Is Samacsys：	N
最大模拟输入电压：	1.32 V
最小模拟输入电压：	-1.32 V
转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-PQCC-N40
JESD-609代码：	e3
长度：	6 mm
最大线性误差 (EL)：	1.8%
湿度敏感等级：	1
模拟输入通道数量：	1
位数：	12
功能数量：	1
端子数量：	40
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC40,.24SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.8 V
认证状态：	Not Qualified
采样速率：	310 MHz
采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	0.8 mm
子类别：	Analog to Digital Converters
标称供电电压：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6 mm
Base Number Matches：	1

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