M28W640FSU原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

M28W320FSU

M28W640FSU

32Mbit (2Mb x16) and 64Mbit (4Mb x16)

3V Supply, Uniform Block, Secure Flash Memories

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_DD= 2.7V to 3.6V Core Power Supply

V_DDQ= 2.7V to 3.6V for Input/Output

V_PP= 12V for fast Program (optional)

BGA

■

ACCESS TIME: 70ns

PROGRAMMING TIME:

–

10µs typical

Double Word Programming Option

Quadruple Word Programming Option

TBGA64 (ZA)

10 x 13mm

■

COMMON FLASH INTERFACE

UNIFORM BLOCKS

64-KWord UNIFORM MEMORY BLOCKS

–

M28W320FSU: 32 Blocks

M28W640FSU: 64 Blocks

■

HARDWARE PROTECTION

_PPPin for Write protect of All Blocks

SECURITY FEATURES

–

V

–

128 bit User-programmable OTP segment

64 bit Unique Device Identifier

KRYPTO Features:

Modify Protection,

Read Protection,

Device Authentication

■

AUTOMATIC STAND-BY MODE

PROGRAM and ERASE SUSPEND

100,000 PROGRAM/ERASE CYCLES per

BLOCK

■

ELECTRONIC SIGNATURE

–

Manufacturer Code: 20h

Device Codes:

M28W320FSU: 880Ch,

M28W640FSU: 8857h

■

PACKAGE

–

Compliant with Lead-Free Soldering

Processes

–

Lead-Free Version

May 2005

1/49

M28W320FSU, M28W640FSU

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. M28W320FSU Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. M28W640FSU Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. M28W320FSU and M28W640FSU Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_DDSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

_DDQSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_PPProgram Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

HARDWARE PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

_PP≤ V_{PPLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11}

SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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M28W320FSU, M28W640FSU

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Read Protection Register and Protection Register Lock . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 17

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V

_PPStatus (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13.TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline . . . . . . . . 29

Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . . 29

3/49

M28W320FSU, M28W640FSU

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20. Block Addresses, M28W320FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21. Block Addresses, M28W640FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 14.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 15.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 46

Table 28. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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M28W320FSU, M28W640FSU

SUMMARY DESCRIPTION

The M28W320FSU and the M28W640FSU are 32

Mbit (2Mbit x 16) and 64 Mbit (4Mbit x 16) Secure

Flash memories. The devices can be erased elec-

trically at block level and programmed in-system

on a Word-by-Word basis using a 2.7V to 3.6V

V_DDsupply for the circuitry and a 2.7V to 3.6V

V_DDQsupply for the Input/Output pins. An optional

12V V_PPpower supply is provided to speed up

customer programming.

The M28W320FSU and M28W640FSU feature 32

Mbits and 64 Mbits respectively and are divided

into thirty-two and sixty-four 64-KWord Uniform

blocks, respectively. Refer to Figure 5. for a de-

tailed description of the devices memory architec-

ture and map.

Two registers are available for protection purpose:

■

The Protection Register

■

The KRYPTO Protection Register.

The Protection Register is a 192 bit Protection

Register to increase the protection of a system de-

sign. The Protection Register is divided into a 64

bit segment and a 128 bit segment. The 64 bit seg-

ment contains a unique device number written by

ST, while the second one is one-time-programma-

ble by the user. The user programmable segment

can be permanently protected. Figure 6., shows

the Protection Register Memory Map.

The KRYPTO Protection Register is used to man-

age the Modify and Read protection modes. It also

features a Device Authentication mechanism. The

KRYPTO Protection Register is described in a

dedicated Application Note. Please contact STMi-

croelectronics for further details.

All devices are equipped with hardware and soft-

ware block protection features to avoid unwanted

program/erase (modify) or read of the Flash mem-

ory content:

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

■

Hardware Protection:

–

When V_PP≤ V_PPLKall blocks are

protected against program or erase.

■

Software Protection thanks to KRYPTO

Security Features:

–

Modify Protection: volatile and non-

volatile.

Read Protection.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

–

The KRYPTO Security features are described in a

dedicated Application Note. Please contact STMi-

croelectronics for further details.

All the devices are offered in a TBGA64 (10 x

13mm) package. In addition to the standard ver-

sion, the package is also available in Lead-free

version, in compliance with JEDEC Std J-STD-

020B, the ST ECOPACK 7191395 Specification,

and the RoHS (Restriction of Hazardous Sub-

stances) directive. The package is compliant with

Lead-free soldering processes.

All devices are supplied with all the bits erased

(set to ’1’).

5/49

M28W320FSU, M28W640FSU

Figure 2. M28W320FSU Logic Diagram

Figure 3. M28W640FSU Logic Diagram

V

DD DDQ PP

22

16

21

16

A0-A21

A0-A20

DQ0-DQ15

W

E

W

E

M28W640FSU

M28W320FSU

G

RP

V

SS

AI10660

AI10659

Table 1. Signal Names

M28W320FSU

M28W640FSU

Signal Names

A0-A20

A0-A21

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

E

G

Output Enable

Write Enable

Reset

W

RP

V

DD

Core Power Supply

Power Supply for

Input/Output

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

V

PP

SS

V

Ground

NC

Not Connected Internally

6/49

M28W320FSU, M28W640FSU

Figure 4. TBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A0

A1

A5

A7

A8

V

A12

A13

V

A17

A18

A21

NC

A20

A16

NC

G

PP

E

DD

V

NC

SS

A2

A6

A9

A11

RP

A14

A19

A3

A4

DQ1

DQ0

NC

A10

DQ9

DQ10

DQ2

NC

A15

DQ8

NC

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

NC

DQ15

NC

G

H

V

DQ6

DQ14

DQ7

W

DDQ

NC

V

NC

DD

SSQ

SS

AI09910b

Note: 1. The above figure gives the TBGA connections for M28W640FSU. On M28W320FSU, A21 is NC.

7/49

M28W320FSU, M28W640FSU

Figure 5. M28W320FSU and M28W640FSU Block Addresses

M28W320FSU

M28W640FSU

Block Addresses

1FFFFFh

3FFFFFh

64 KWords

1F0000h

1EFFFFh

3F0000h

3EFFFFh

1E0000h

3E0000h

Total of 32

Total of 64

1 Mbit Uniform Blocks

01FFFFh

64 KWords

010000h

00FFFFh

010000h

00FFFFh

000000h

AI10661

Note: 1. Also see APPENDIX A., Tables 21 and 20 for a full listing of the Block Addresses.

Figure 6. Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

85h

84h

Unique device number

81h

Protection Register Lock

1

0

80h

AI05520b

8/49

M28W320FSU, M28W640FSU

SIGNAL DESCRIPTIONS

See Figures 2 and 3, Logic Diagrams and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.

Enable or a change of the address is required to

ensure valid data outputs.

V_DDSupply Voltage. V_DDprovides the power

Address Inputs. The Address Inputs select the

cells in the memory array to access during Bus

Read operations. Address Inputs range from A0 to

A20 for the M28W320FSU. The M28W640FSU

has an additional A21 address line. During Bus

Write operations they control the commands sent

to the Command Interface of the internal state ma-

chine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Write Bus

operation.

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

V

_DDQSupply Voltage. V_DDQprovides the power

supply to the I/O pins and enables all Outputs to

be powered independently from V_DD. V_DDQcan be

tied to V_DDor can use a separate supply.

V_PPProgram Supply Voltage. V_PPis both a

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage V_DDand the

Program Supply Voltage V_PPcan be applied in

any order.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at V_ILand Reset is at V_IHthe device is in active

mode. When Chip Enable is at V_IHthe memory is

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable, E, or Write En-

able, W, whichever occurs first.

If V_PPis kept in a low voltage range (0V to 3.6V)

V

_PPis seen as a control input. In this case a volt-

age lower than V_PPLKgives an absolute protection

against program or erase, while V_PP> V_PP1en-

ables these functions (see Table 12., DC Charac-

teristics, for the relevant values). V_PPis only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect on Program or Erase.

If V_PPis set to V_PPH, it acts as a power supply pin.

In this condition V_PPmust be stable until the Pro-

gram/Erase algorithm is completed (see Table 14.

and Table 15.). A Quadruple Word Program com-

mand will be ignored if V_PPis not set to V_PPHwhile

a Double Word Program can be performed even if

V_PPis set to V_DD.

Reset (RP). The Reset input provides a hard-

ware reset of the memory. When Reset is at V_IL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. After Reset all blocks are in the Locked

state. When Reset is at V_IH, the device is in normal

operation. Exiting reset mode the device enters

read array mode, but a negative transition of Chip

V_SSGround. V_SSis the reference for all voltage

measurements.

Note: Each device in a system should have

V_DD, V_DDQand V_PPdecoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 8., AC Mea-

surement Load Circuit. The PCB track widths

should be sufficient to carry the required V_PP

program and erase currents.

9/49

M28W320FSU, M28W640FSU

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2., Bus Operations, for a summary.

Characteristics, for details of the timing require-

ments.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at V_IH.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at V_IHand the device is in

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

V_IHduring a program or erase operation, the de-

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V_IL, and the supply

current is reduced to I_DD1. The data Inputs/Out-

puts will still output data if a bus Read operation is

in progress.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

able must be at V_ILin order to perform a read op-

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 9., Read AC Waveforms, and Table

13., Read AC Characteristics, for details of when

the output becomes valid.

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

and Write Enable are at V_ILwith Output Enable at

V_IH. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

Reset. During Reset mode when Output Enable

is Low, V_IL, the memory is deselected and the out-

puts are high impedance. The memory is in Reset

mode when Reset is at V_IL. The power consump-

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to V_SSduring a Pro-

gram or Erase, this operation is aborted and the

memory content is no longer valid.

See Figure 10. and Figure 11., Write AC Wave-

forms, and Table 14. and Table 15., Write AC

Table 2. Bus Operations

V

Operation

Bus Read

E

G

W

RP

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

IH

V

IH

Don't Care

V or V

DD

IL

IH

V

IH

Bus Write

Output Disable

Standby

IL

PPH

V

IH

Don't Care

IH

V

IH

X

Hi-Z

IH

V

IL

Reset

X

Hi-Z

Note: X = V or V , V = 12V ± 5%.

PPH

IL

IH

10/49

M28W320FSU, M28W640FSU

HARDWARE PROTECTION

All devices feature hardware protection. Refer to

SIGNAL DESCRIPTIONS section for a detailed

description of these signals.

V

_PP≤ V_PPLK. The V_PPpin protects all the memo-

ry blocks from program and erase operations. Re-

fer to SIGNAL DESCRIPTIONS section for a

detailed description of these signals.

SECURITY FEATURES

The M28W320FSU and M28W640FSU are

equipped with KRYPTO Security features per-

forming software protection. They allow any block

to be protected from program/erase or read oper-

ations:

The KRYPTO features (Modify Protection mode,

Read Protection mode and Device Authentication

mechanism) are not described in this Datasheet.

For further details concerning these additional pro-

tection modes please contact ST Sales Offices.

■

Modify Protection including Volatile Block

Lock/Unlock, Non-Volatile Block Modify

Protection, Non-Volatile Password Modify

Protection and Irreversible Protection.

The devices also feature a 64 bit Unique Device

Identifier and a 128 bit user-programmable OTP

segment (see Figure 6., Protection Register Mem-

ory Map and Protection Register Program Com-

mand).

■

Read Protection.

11/49

M28W320FSU, M28W640FSU

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time, to monitor

the progress of the operation, or the Program/

Erase states. See Table 3., Command Codes, for

a summary of the commands and see APPENDIX

D., Table 28., Write State Machine Current/Next,

sheet 1 of 2., for a summary of the Command In-

terface.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V_DDis lower than V_LKO. Com-

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 4., Commands,

in conjunction with the text descriptions below.

Table 3. Command Codes

Hex Code

01h

Command

Block Lock confirm

Program

10h

20h

Erase

30h

Double Word Program

Program

40h

50h

Clear Status Register

Quadruple Word Program

Read Status Register

Read Electronic Signature

Read CFI Query

56h

70h

90h

98h

B0h

C0h

D0h

FFh

Program/Erase Suspend

Protection Register Program

Program/Erase Resume

Read Memory Array

Read Memory Array Command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device. One Bus Write

cycle is required to issue the Read Query Com-

mand. Once the command is issued subsequent

Bus Read operations read from the Common

Flash Interface Memory Area. See APPENDIX

B., COMMON FLASH INTERFACE (CFI), Tables

22, 23, 24, 25, 26 and 27 for details on the infor-

mation contained in the Common Flash Interface

memory area.

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register at any address, until another

command is issued. See Table 8., Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes, and the Pro-

tection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code and the

Protection Register. See Tables 5, and 6 for the

valid address.

Two Bus Write cycles are required to issue the

command.

■

The first bus cycle sets up the Erase

command.

■

The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

12/49

M28W320FSU, M28W640FSU

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to V_IL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V_IL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See APPENDIX C., Figure 15., Double Word Pro-

gram Flowchart and Pseudo Code for the flow-

chart for using the Double Word Program

command.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 7., Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See APPENDIX C., Figure 18., Erase Flowchart

and Pseudo Code, for a suggested flowchart for

using the Erase command.

Quadruple Word Program Command

This feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel.The four words must differ only for the

addresses A0 and A1.

Program Command

A Quadruple word Program command will be ig-

nored if V_PPis not set to V_PPH

.

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

■

The first bus cycle sets up the Program

command.

The second latches the Address and the Data

to be written and starts the Program/Erase

Controller.

■

The first bus cycle sets up the Quadruple

Word Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written.

The fourth bus cycle latches the Address and

the Data of the third word to be written.

■

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 7., Program, Erase

Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to V_IL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V_IL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See APPENDIX C., Figure 16., Quadruple Word

Program Flowchart and Pseudo Code, for the

flowchart for using the Quadruple Word Program

command.

See APPENDIX C., Figure 14., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0.

The Double Word Program command can be is-

sued either with V_PPset to V_PPHor to V_DD

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

.

Three bus write cycles are necessary to issue the

Double Word Program command.

■

The first bus cycle sets up the Double Word

Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

13/49

M28W320FSU, M28W640FSU

command and pause the Program/Erase control-

ler.

quent Bus Read operations read the Status Reg-

ister.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Double Word Program, Quadruple

Word Program, Block Lock, or Protection Program

commands will also be accepted. The block being

erased may be protected by issuing the Block Pro-

tect, Block Lock or Protection Program com-

mands. When the Program/Erase Resume

command is issued the operation will complete.

Only the blocks not being erased may be read or

programmed correctly.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to V_IH. Program/Erase is aborted if

Reset turns to V_IL.

See APPENDIX C., Figure 17., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 19., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

See APPENDIX C., Figure 17., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 19., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

Protection Register Program Command

The Protection Register Program command is

used to Program the 128 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protec-

tion Register Program command.

■

The first bus cycle sets up the Protection

Register Program command.

■

The second latches the Address and the Data

to be written to the Protection Register and

starts the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register (see Figure

6., Protection Register Memory Map). Attempting

to program a previously protected Protection Reg-

ister will result in a Status Register error. The pro-

tection of the Protection Register is not reversible.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

The Protection Register Program cannot be sus-

pended.

14/49

M28W320FSU, M28W640FSU

Table 4. Commands

Commands

Bus Write Operations

3rd Cycle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

1st Cycle

2nd Cycle

4th Cycle

5th Cycle

Read Memory

Array

1+ Write

X

FFh

RA

X

RD

SRD

IDh

Read

Read Status

Register

1+ Write

70h Read

90h Read

Read Electronic

Signature

(2)

SA

Read CFI Query 1+ Write

X

98h Read QA

20h Write BA

QD

Erase

2

Write

D0h

40h or

Program

X

Write PA

10h

PD

Double Word

3

Write

30h Write PA1 PD1 Write PA2 PD2

(3)

Program

Quadruple Word

5

1

2

Write

X

56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

(4)

Program

Clear Status

Register

50h

Program/Erase

Suspend

B0h

Program/Erase

Resume

D0h

Protection

Register Program

C0h Write PRA PRD

Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),

QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-

dress, PRD=Protection Register Data.

2. The signature addresses are listed in Tables 5 and 6.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

Table 5. Read Electronic Signature

A8-A20

Code

Device

E

G

W

A0

A1

A2-A7

DQ0-DQ7

DQ8-DQ15

(2)

A8-A21

Manufacture

Code

V

IL

V

IL

0

Don't Care

20h

00h

IL

IH

V

M28W320FSU

M28W640FSU

0

Don't Care

0Ch

57h

88h

IL

IH

IL

Device Code

V

IH

V

IL

Note: 1. RP = V

.

IH

2. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.

15/49

M28W320FSU, M28W640FSU

Table 6. Read Protection Register and Protection Register Lock

(1)

Word

E

G

W

A0-A7

DQ0

DQ1

DQ2

DQ3-DQ7 DQ8-DQ15

A8-A21

OTP Prot.

data

V

Lock

80h Don't Care

0

00h

IL

IH

V

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don't Care

82h Don't Care

83h Don't Care

84h Don't Care

ID data

IL

IH

ID data

85h Don't Care OTP data

86h Don't Care OTP data

87h Don't Care OTP data

88h Don't Care OTP data

89h Don't Care OTP data

8Ah Don't Care OTP data

8Bh Don't Care OTP data

8Ch Don't Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

OTP 4

OTP 5

OTP 6

OTP 7

Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.

16/49

M28W320FSU, M28W640FSU

Table 7. Program, Erase Times and Program/Erase Endurance Cycles

M28W320FSU, M28W640FSU

Parameter

Word Program

Test Conditions

= V

Unit

Min

Typ

Max

V

PP

10

200

µs

s

DD

V

= V

or

PP

PPH

Double Word Program

10

200

V

PP

= V

DD

V

PP

= V

Quadruple Word Program

PPH

Using Word

Program command

V

PP

= V

DD

0.64

V

= V

or

PPH

Using Double Word

Program command

PP

V

0.32

0.16

1

s

Block Program

= V

5

PP

DD

Using Quadruple

Word Program

command

V

= V

PPH

PP

V

=V

or

PPH

PP

V

Block Erase

10

= V

DD

PP

Program/Erase Cycles (per Block)

Data Retention

100,000

20

cycles

years

17/49

M28W320FSU, M28W640FSU

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

or Output Enable returns to V_IH. Either Chip En-

able or Output Enable must be toggled to update

the latched data.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 8., Status Register Bits. Refer to Table 8. in

conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The

Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive. When the Program/Erase Controller Sta-

tus bit is Low (set to ‘0’), the Program/Erase Con-

troller is active; when the bit is High (set to ‘1’), the

Program/Erase Controller is inactive, and the de-

vice is ready to process a new command.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V_PPStatus (Bit 3). The V_PPStatus bit can be

used to identify an invalid voltage on the V_PPpin

during Program and Erase operations. The V_PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V_PPbecomes invalid during an operation.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V_PP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

When the V_PPStatus bit is Low (set to ‘0’), the volt-

age on the V_PPpin was sampled at a valid voltage;

when the V_PPStatus bit is High (set to ‘1’), the V_PP

pin has a voltage that is below the V_PPLockout

Voltage, V_PPLK, the memory is protected and Pro-

gram and Erase operations cannot be performed.

Once set High, the V_PPStatus bit can only be reset

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

18/49

M28W320FSU, M28W640FSU

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to APPENDIX C., FLOWCHARTS

AND PSEUDO CODES, for using the Status

Register.

Table 8. Status Register Bits

Bit

Name

Logic Level

Definition

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

Status

PP

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level '1' is High, '0' is Low.

19/49

M28W320FSU, M28W640FSU

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 9. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

– 40

– 55

Max

(1)

T

A

85

°C

V

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

125

155

(2)

BIAS

T

STG

T

Lead Temperature during Soldering

Input or Output Voltage

Supply Voltage

LEAD

V

IO

V

+0.6

DDQ

– 0.6

V

, V

DDQ

4.1

13

V

DD

V

PP

Program Voltage

V

Note: 1. Depends on range.

®

2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification,

and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

20/49

M28W320FSU, M28W640FSU

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment

Conditions

summarized

in

Table

10., Operating and AC Measurement Conditions.

Designers should check that the operating condi-

tions in their circuit match the measurement condi-

tions when relying on the quoted parameters.

Table 10. Operating and AC Measurement Conditions

Parameter

M28W320FSU, M28W640FSU

70

Units

Min

2.7

Max

3.6

85

V

Supply Voltage

V

DD

2.7

DDQ

Ambient Operating Temperature

–40

°C

pF

ns

V

Load Capacitance (C )

50

L

Input Rise and Fall Times

5

0 to V

Input Pulse Voltages

DDQ

V /2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 7. AC Measurement I/O Waveform

Figure 8. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DDQ

V

0V

DD

25kΩ

AI00610

DEVICE

UNDER

TEST

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI00609C

L

Table 11. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

IN

= 0V

IN

C

V

OUT

12

pF

OUT

Note: Sampled only, not 100% tested.

21/49

M28W320FSU, M28W640FSU

Table 12. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V≤ V ≤ V

LI

IN

DDQ

I

0V≤ V

≤V

±10

18

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

9

mA

DD

SS

IH

E = V

RP = V

± 0.2V,

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

15

50

10

20

50

400

µA

DD1

± 0.2V

DDQ

Supply Current

(Reset)

I

RP = V ± 0.2V

15

5

DD2

SS

Program in progress

mA

µA

V

= 12V ± 5%

PP

I

Supply Current (Program)

Supply Current (Erase)

DD3

Program in progress

= V

10

5

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

DD4

Erase in progress

= V

10

15

V

PP

DD

E = V

Erase suspended

± 0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

DD5

Program Current

(Read or Stand-by)

I

V

> V

µA

PP

DD

Program Current

(Read or Stand-by)

I

V

≤ V

1

5

µA

PP1

DD

I

RP = V ± 0.2V

Program Current (Reset)

PP2

SS

Program in progress

10

mA

V

= 12V ± 5%

PP

I

Program Current (Program)

PP3

Program in progress

= V

1

3

1

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V ± 5%

10

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

5

V

PP

DD

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 V

V

+0.4

IH

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

Output Low Voltage

Output High Voltage

0.1

V

OL

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

OH

V

–0.1

DDQ

V

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

PP1

2.7

3.6

Program Voltage

(Program or Erase

operations)

V

PPH

11.4

12.6

V

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

DD

Supply Voltage (Program

V

LKO

and Erase lock-out)

22/49

M28W320FSU, M28W640FSU

Figure 9. Read AC Waveforms

tAVAV

VALID

(1)

A0-A20/A21

tAVQV

tAXQX

E

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQV

tGHQX

tGHQZ

tGLQX

VALID

DQ0-DQ15

OUTPUTS

ENABLED

ADDR. VALID

CHIP ENABLE

DATA VALID

STANDBY

AI09928

Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.

Table 13. Read AC Characteristics

M28W320FSU M28W640FSU

Symbol Alt

Parameter

Unit

70

t

RC

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

Max

Min

ns

AVAV

t

ACC

AVQV

(1)

(2)

(1)

(2)

(1)

t

Address Transition to Output Transition

0

t

OH

AXQX

EHQX

EHQZ

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

Min

Max

Min

Max

Min

ns

OH

t

20

70

0

20

70

0

HZ

t

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

LZ

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

0

t

OH

GHQX

t

20

0

20

0

DF

GHQZ

t

OE

GLQV

t

OLZ

GLQX

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

23/49

M28W320FSU, M28W640FSU

Figure 10. Write AC Waveforms, Write Enable Controlled

Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.

24/49

M28W320FSU, M28W640FSU

Table 14. Write AC Characteristics, Write Enable Controlled

M28W320FSU M28W640FSU

Unit

Symbol

Alt

Parameter

70

45

0

70

45

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

DVWH

t

ELWL

t

70

ELQV

t

QVVPL

(1,2)

Output Valid to V Low

Min

0

ns

PP

t

VPHWH

(1)

t

V

High to Write Enable High

PP

200

VPS

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Min

0

ns

WHAX

AH

DH

CH

t

WHDX

t

0

WHEH

t

25

20

25

45

25

20

25

45

WHEL

t

WHGL

t

WPH

WHWL

t

WLWH

WP

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

25/49

M28W320FSU, M28W640FSU

Figure 11. Write AC Waveforms, Chip Enable Controlled

Note: 1. Addresses range from A0 to A20 for the M28W320FSU and from A0 to A21 for the M28W640FSU.

26/49

M28W320FSU, M28W640FSU

Table 15. Write AC Characteristics, Chip Enable Controlled

M28W320FSU

M28W640FSU

Symbol Alt

Parameter

Unit

70

45

0

70

45

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

EHAX

t

0

EHDX

DH

t

CPH

25

0

25

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

45

70

45

70

ELEH

ELQV

t

QVVPL

(1,2)

Output Valid to V Low

Min

0

ns

PP

t

VPHEH

(1)

t

V

High to Chip Enable High

Min

200

0

200

0

ns

VPS

PP

t

CS

Write Enable Low to Chip Enable Low

WLEL

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

27/49

M28W320FSU, M28W640FSU

Figure 12. Power-Up and Reset AC Waveforms

W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

Reset

VDD, VDDQ

Power-Up

AI03537b

Table 16. Power-Up and Reset AC Characteristics

M28W320FSU,

M28W640FSU

Symbol

Parameter

Test Condition

Unit

70

During Program

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip Enable Low,

Output Enable Low

and Erase

t

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

< 100ns.

PLPH

2. Sampled only, not 100% tested.

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

28/49

M28W320FSU, M28W640FSU

PACKAGE MECHANICAL

Figure 13. TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

E

E1

ddd

BALL "A1"

A

e

b

A2

A1

BGA-Z23

Note: Drawing is not to scale.

Table 17. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.350

Typ

Max

A

A1

A2

b

0.0472

0.0138

0.300

0.800

0.200

0.0118

0.0315

0.0079

0.350

9.900

–

0.500

0.0138

0.3898

–

0.0197

D

10.000

7.000

10.100

0.3937

0.2756

0.3976

D1

ddd

e

–

0.100

0.0039

1.000

13.000

7.000

1.500

3.000

0.500

–

0.0394

0.5118

0.2756

0.0591

0.1181

0.0197

–

E

12.900

13.100

0.5079

0.5157

E1

FD

FE

SD

SE

–

29/49

M28W320FSU, M28W640FSU

PART NUMBERING

Table 18. Ordering Information Scheme

Example:

M28W320FSU 70 ZA

6

T

Device Type

M28

Operating Voltage

W = V = 2.7V to 3.6V; V

= 2.7V to 3.6V

DDQ

DD

Device Function

320FSU = 32 Mbit (2 Mb x16), Uniform Block, Secure, 0.13µm

640FSU = 64 Mbit (4 Mb x16), Uniform Block, Secure, 0.13µm

Speed

70 = 70ns

Package

ZA = TBGA64:10 x 13mm, 1mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing

30/49

M28W320FSU, M28W640FSU

Table 19. Daisy Chain Ordering Scheme

Example:

M28W640FSU

-ZA

T

Device Type

M28W320FSU

M28W640FSU

Daisy Chain

-ZA = TBGA64: 10 x 13, 1mm pitch

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc.) or for further information on any aspect of this device, please contact

the ST Sales Office nearest to you.

31/49

M28W320FSU, M28W640FSU

APPENDIX A. BLOCK ADDRESS TABLES

Table 20. Block Addresses, M28W320FSU

Block

Number

Address Range

Block

Address Range

Number

15

14

13

12

11

10

9

0F0000h-0FFFFFh

0E0000h-0EFFFFh

0D0000h-0DFFFFh

0C0000h-0CFFFFh

0B0000h-0BFFFFh

0A0000h-0AFFFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

000000h-00FFFFh

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

1F0000h-1FFFFFh

1E0000h-1EFFFFh

1D0000h-1DFFFFh

1C0000h-1CFFFFh

1B0000h-1BFFFFh

1A0000h-1AFFFFh

190000h-19FFFFh

180000h-18FFFFh

170000h-17FFFFh

160000h-16FFFFh

150000h-15FFFFh

140000h-14FFFFh

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

8

7

6

5

4

3

2

1

0

32/49

M28W320FSU, M28W640FSU

Table 21. Block Addresses, M28W640FSU

Block

Number

Address Range

Block

Address Range

Number

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

1F0000h-1FFFFFh

1E0000h-1EFFFFh

1D0000h-1DFFFFh

1C0000h-1CFFFFh

1B0000h-1BFFFFh

1A0000h-1AFFFFh

190000h-19FFFFh

180000h-18FFFFh

170000h-17FFFFh

160000h-16FFFFh

150000h-15FFFFh

140000h-14FFFFh

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

0F0000h-0FFFFFh

0E0000h-0EFFFFh

0D0000h-0DFFFFh

0C0000h-0CFFFFh

0B0000h-0BFFFFh

0A0000h-0AFFFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

000000h-00FFFFh

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

3F0000h-3FFFFFh

3E0000h-3EFFFFh

3D0000h-3DFFFFh

3C0000h-3CFFFFh

3B0000h-3BFFFFh

3A0000h-3AFFFFh

390000h-39FFFFh

380000h-38FFFFh

370000h-37FFFFh

360000h-36FFFFh

350000h-35FFFFh

340000h-34FFFFh

330000h-33FFFFh

320000h-32FFFFh

310000h-31FFFFh

300000h-30FFFFh

2F0000h-2FFFFFh

2E0000h-2EFFFFh

2D0000h-2DFFFFh

2C0000h-2CFFFFh

2B0000h-2BFFFFh

2A0000h-2AFFFFh

290000h-29FFFFh

280000h-28FFFFh

270000h-27FFFFh

260000h-26FFFFh

250000h-25FFFFh

240000h-24FFFFh

230000h-23FFFFh

220000h-22FFFFh

210000h-21FFFFh

200000h-20FFFFh

8

7

6

5

4

3

2

1

0

33/49

M28W320FSU, M28W640FSU

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 22, 23,

24, 25, 26 and 27 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 27., Security Code Area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 22. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 23. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

ST

880Ch M28W320FSU Device Code

8857h M28W640FSU Device Code

01h

Uniform

02h-0Fh reserved Reserved

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

0051h

0052h

0059h

0003h

0000h

0035h

0000h

"Q"

"R"

"Y"

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

Address for Primary Algorithm extended Query table (see Table 26.)

P = 35h

NA

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

34/49

M28W320FSU, M28W640FSU

Table 24. CFI Query System Interface Information

Offset

Data

Description

Value

V

Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100mV

DD

1Bh

0027h

2.7V

3.6V

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100mV

DD

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100mV

PP

11.4V

12.6V

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100mV

PP

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double/Quadruple Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for Word program = 2 times typical

n

Maximum time-out for Double/Quadruple Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

35/49

M28W320FSU, M28W640FSU

Table 25. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

0016h

4 MBytes

n

27h

Device Size = 2 in number of bytes

0017h

8 MBytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8

1

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

2Ch

0001h

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Dh

2Eh

001Fh

0000h

Region 1 Information

Number of identical-size erase blocks = 001Fh+1

32

Region 1 Information

Block size in Region 1 = 0200h * 256 byte

2Fh

30h

0000h

0002h

128

KBytes

2Dh

2Eh

003Fh

0000h

Region 1 Information

Number of identical-size erase blocks = 003Fh+1

64

Region 1 Information

Block size in Region 1 = 0200h * 256 byte

2Fh

30h

0000h

0002h

128

KBytes

31h to 34h

Reserved

36/49

M28W320FSU, M28W640FSU

Table 26. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0066h

0000h

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0Chip Erase supported(1 = Yes, 0 = No)

No

Yes

No

bit 1Suspend Erase supported(1 = Yes, 0 = No)

bit 2Suspend Program supported(1 = Yes, 0 = No)

bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)

bit 4Queued Erase supported(1 = Yes, 0 = No)

bit 5Instant individual block locking supported(1 = Yes, 0 = No)

bit 6Protection bits supported(1 = Yes, 0 = No)

bit 7Page mode read supported(1 = Yes, 0 = No)

bit 8Synchronous read supported(1 = Yes, 0 = No)

bit 31 to 9 Reserved; undefined bits are ‘0’

No

Yes

No

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 15 to 1Reserved for future use; undefined bits are ‘0’

Yes

3V

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0030h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

DD

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100mV

V

Supply Optimum Program/Erase voltage

12V

01

PP

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

0004h

Protection Field 1: Protection Description

80h

00h

This field describes user-available One Time Programmable (OTP)

Protection Register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection Register Lock byte, the section’s first byte.

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7 Lock/bytes JEDEC-plane physical low address

8 Bytes

16 Bytes

bit 8 to 15Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 23., offset 15 for P pointer definition.

37/49

M28W320FSU, M28W640FSU

Table 27. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

128 bits: User Programmable OTP

38/49

M28W320FSU, M28W640FSU

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 14. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

39/49

M28W320FSU, M28W640FSU

Figure 15. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03539b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

40/49

M28W320FSU, M28W640FSU

Figure 16. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write 56h

Write Address 1

& Data 1 (3)

writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI06233

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

41/49

M28W320FSU, M28W640FSU

Figure 17. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI03540b

42/49

M28W320FSU, M28W640FSU

Figure 18. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

43/49

M28W320FSU, M28W640FSU

Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI03542b

44/49

M28W320FSU, M28W640FSU

Figure 20. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0xC0) ;

Write C0h

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

45/49

M28W320FSU, M28W640FSU

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER

STATE

Table 28. Write State Machine Current/Next, sheet 1 of 2.

Command Input (and Next State)

Data

When

Read

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array “1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

“1”

Electronic

Signature

Program

Setup

Erase

Setup

Read

Read Array

Status

Elect.Sg.

Read CFI

“1”

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Query

Prot. Prog.

“1”

Status

Protection Register Program

Protection Register Program continue

Setup

Prot. Prog.

“0”

(continue)

Prot. Prog.

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

(complete)

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

Status

Array

Status

(continue) Read Array (continue)

Program Prog. Sus Program

(continue) Read Array (continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus Prog. Sus

Read Sts Read Array

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

(continue) Read Array (continue)

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

“0”

“1”

Read Array

(continue) Read Array (continue)

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Array

Read Array

Status

Erase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

Erase

(continue)

Erase Sus

Read Sts

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Program Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Setup

Read Array (continue) Read Array (continue)

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase Sus Erase Sus

Read Sts Read Array

Read Array (continue) Read Array (continue)

Erase Sus

Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array (continue) Read Array (continue)

Erase Sus

Read CFI

Erase Sus

CFI

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array

Read Array (continue) Read Array (continue)

Erase

(complete)

Program

Setup

Erase

Read

Status

Read Array

Setup

Read Array

Status

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

46/49

M28W320FSU, M28W640FSU

Table 29. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Current State

Read Elect.Sg.

(90h)

Read CFI Query

Prot. Prog. Setup (C0h)

(98h)

Read CFI Query

Read Array

Read Status

Read Elect.Sg.

Prot. Prog. Setup

Read CFI Query

Read Elect.Sg.

Read CFI Query

Prot. Prog. Setup

Prot. Prog. (continue)

Prot. Prog. (complete)

Prog. Setup

Read CFI Query

Protection Register Program

Protection Register Program (continue)

Read CFI Query

Read Elect.Sg.

Prot. Prog. Setup

Program

Program (continue)

Prog. Suspend

Read Status

Prog. Suspend Read Elect.Sg.

Prog. Suspend Read CFI Query Program Suspend Read Array

Prog. Suspend

Read Array

Prog. Suspend

Read Elect.Sg.

Prog. Suspend

Read CFI

Prog. Suspend Read Elect.Sg.

Read Elect.Sg.

Program (complete)

Erase Setup

Read CFIQuery

Erase Command Error

Read CFI Query

Prot. Prog. Setup

Erase Cmd.Error

Erase (continue)

Read Elect.Sg.

Erase (continue)

Erase Suspend

Read Ststus

Erase Suspend

Read CFI Query

Erase Suspend Read Elect.Sg.

Erase Suspend Read Array

Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query

Erase Suspend Read Array

Prot. Prog. Setup

Erase Suspend Read Elect.Sg.

Erase Suspend Read CFI Query Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query

Erase (complete) Read Elect.Sg. Read CFI Query

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

47/49

M28W320FSU, M28W640FSU

REVISION HISTORY

Table 30. Document Revision History

Date

Version

0.1

Revision Details

07-Dec-2004

07-Feb-2005

First Issue.

0.2

Locations 31h to 34h set to reserved in Table 25., Device Geometry Definition.

Datasheet status updated to “Full Datasheet”.

Table 25., Device Geometry Definition updated.

16-May-2005

1.0

48/49

M28W320FSU, M28W640FSU

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

49/49

型号:	M28W640FSU70ZA1
生命周期：	Obsolete
IHS 制造商：	NUMONYX
零件包装代码：	BGA
包装说明：	10 X 13 MM, 1 MM PITCH, TBGA-64
针数：	64
Reach Compliance Code：	unknown
ECCN代码：	3A991.B.1.A
HTS代码：	8542.32.00.51
风险等级：	5.66
最长访问时间：	70 ns
其他特性：	100,000 PROGRAM/ERASE CYCLES
JESD-30 代码：	R-PBGA-B64
JESD-609代码：	e1
长度：	13 mm
内存密度：	67108864 bit
内存集成电路类型：	FLASH
内存宽度：	16
功能数量：	1
端子数量：	64
字数：	4194304 words
字数代码：	4000000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	4MX16
封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260
编程电压：	3 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN SILVER COPPER
端子形式：	BALL
端子节距：	1 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
类型：	NOR TYPE
宽度：	10 mm

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