M51996芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

DESCRIPTION

M51996A is the primary switching regulator controller which is

PIN CONFIGURATION (TOP VIEW)

especially designed to get the regulated DC voltage from AC power

supply.

This IC can directly drive the MOS-FET with fast rise and fast fall

output pulse and with a large-drive totempole output.

Type M51996A has the functions of not only high frequency OSC

and fast output drive but also current limit with fast response and

high sensibility so the true "fast switching regulator" can be

realized.

Vcc

COLLECTOR

1

2

3

4

5

6

7

14

13

12

11

10

9

VOUT

CLM+

GND

T-OFF

CF

EMITTER

OVP

F/B

DET

T-ON

The M51996A is equivalent to the M51978 with externally re-

settable OVP(over voltage protection)circuit.

8

REG

SOFT

Outline 14P4

FEATURES

500kHz operation to MOS FET

Output current...............................................................±1A

Output rise time 60ns,fall time 40ns

Vcc

1

2

3

4

5

6

7

8

16

15

14

13

COLLECTOR

Modified totempole output method with small through current

Compact and light-weight power supply

CLM+

VOUT

•Small start-up current............................................100µA typ.

•Big difference between "start-up voltage" and "stop voltage"

makes the smoothing capacitor of the power input section small.

Start-up threshold 16V,stop voltage 10V

GND

EMITTER

HEAT SINK PIN

OVP

F/B

12 T-OFF

CF

10 T-ON

SOFT

11

•Packages with high power dissipation are used to with-stand the

heat generated by the gate-drive current of MOS FET.

14-pin DIP,16-pin SOP 1.5W(at 25°C)

DET

REG

9

Simplified peripheral circuit with protection circuit and built-in

large-capacity totempole output

Outline 16P2N-A

•High-speed current limiting circuit using pulse-by-pulse

method(CLM+pin)

•Over-voltage protection circuit with an externally re-settable

latch(OVP)

Connect the heat sink pin to GND.

•Protection circuit for output miss action at low supply

voltage(UVLO)

High-performance and highly functional power supply

•Triangular wave oscillator for easy dead time setting

•SOFT start function by expanding period

APPLICATION

Feed forward regulator,fly-back regulator

RECOMMENDED OPERATING CONDITIONS

Supply voltage range............................................12 to 30V

Operating frequency.................................less than 500kHz

Oscillator frequency setting resistance

•T-ON pin resistance RON...........................10k to 75kW

•T-OFF pin resistance ROFF..........................2k to 30kW

1

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

BLOCK DIAGRAM

F/B

REG(7.8V)

VCC

7.1V

5.8V

500

3K

VOLTAGE

REGULATOR

15.2K

6S

1S

DET

OP AMP

UNDER

VOLTAGE

LOCK OUT

1S

2.5V

LATCH

OVP

PWM

COMPARATOR

PWM

LATCH

COLLECTOR

VOUT

EMITTER

CF

T-ON

CURRENT LIMIT

DETECTION

OSCILLATOR

(TRIANGLE)

T-OFF

SOFT

GND

CLM+

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC

Parameter

Conditions

Ratings

Unit

V

Supply voltage

31

Collector voltage

VC

V

Peak

±1

±0.15

IO

Output current

A

Continuous

VREG terminal output current

SOFT terminal voltage

CLM+ terminal voltage

DET terminal voltage

OVP terminal current

F/B terminal current

mA

V

IVREG

-6

VSOFT

VREG +0.2

-0.3 to +3

VCLM+

VDET

IOVP

IFB

V

6

8

mA

-10

ITON

-1

-2

T-ON terminal input current

T-OFF terminal input current

Power dissipation

ITOFF

Pd

1.5

W

mW/˚C

Ta=25˚C

Ta>25˚C

12

Thermal derating

K

-30 to +85

-40 to +125

Topr

Tstg

Operating temperature

Storage temperature

˚C

Note 1."+" sign shows the direction of current flowing into the IC and "-" sign shows the current flowing out from the IC.

2.The low impedance voltage supply should not be applied to the OVP terminal.

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

ELECTRICAL CHARACTERISTICS (VCC=18V, Ta=25°C, unless otherwise noted)

Limits

Typ.

Block

Symbol

Parameter

Test conditions

Unit

Min.

Vcc(STOP)

Max.

30

Operating supply voltage range

V

VCC

VCC(START) Operation start up voltage

16.2

9.9

17.2

10.9

15.2

9.0

Operation stop voltage

VCC(STOP)

5.0

6.3

7.6

V

DVcc=Vcc(START) -Vcc(STOP)

DVcc

Vcc(START),Vcc(STOP) difference

65

50

100

150

200

Vcc=14.5V,Ta=25°C

Vcc=14.5V,-30£Ta£85°C

Vcc=15V,f=188kHz

Stand-by current

IccL

IccO

µA

mA

7.3

8

1.3

11

12

17

19

3.0

320

-1.0

-0.4

-0.70

Operating circuit current

Vcc=30V,f=188kHz

Vcc=25V

mA

µA

mA

2.0

Circuit current in OVP state

Current at 0% duty

IccOVP

210

-1.5

-0.6

-0.99

140

-2.1

-0.9

-1.35

Vcc=9.5V

IFBMIND

IFBMAXD

DIFB

F/B terminal input current

DIFB=IFBMIND-IFBMAXD

Current at maximum duty

Current difference between max and 0% duty

mA

V

5.9

4.9

420

540

7.1

F/B terminal voltage

VFB

F/B terminal input current=0.95mA

OVP terminal resistance

W

mV

RFB

600

750

780

960

VTHOVPH

DVTHOVP

ITHOVP

IINOVP

OVP terminal H threshold voltage

OVP terminal hysteresis voltage

OVP terminal threshold current

OVP terminal input current

OVP reset supply voltage

30

150

9.0

DVTHOVP=VTHOVPH-VTHOVPL

250

80

µA

VOVP=400mV

µA

V

7.5

10.0

VCCOVPC

OVP terminal is open.

(high impedance)

VCC(STOP)

-VCCOVPC

Difference supply voltage between

operation stop and OVP reset

1.20

V

0.55

-480

-210

-320

-140

-213

-93

Vcc=30V

Vcc=18V

Current from OVP terminal for

OVP reset

ITHOVPC

µA

CLM+ terminal threshold voltage

CLM+ terminal current

180

-280

200

-200

mV

µA

ns

VTHCLM+

IINCLM+

220

-140

VCLM+=0V

TPDCLM+

Delay time from CLM+ to VOUT

100

188

RON=20kW,ROFF=17kW

CF=220pF,-5£Ta£85°C

Oscillating frequency

170

207

kHz

fOSC

47

50

53

%

V

TDUTY

VOSCH

VOSCL

Maximum ON duty

Upper limit voltage of oscillation waveform

3.97

1.76

4.37

1.96

4.77

2.16

RON=20kW,ROFF=17kW

CF=220pF

Lower limit voltage of oscillation waveform

V

Voltage difference between upper limit and

lower limit of OSC waveform

2.11

2.41

2.71

DVOSC

V

VT-ON

4.5

3.5

5.4

RON=20kW

ROFF=17kW

3.8

T-ON terminal voltage

T-OFF terminal voltage

VSOFT=5.5V

V

VT-OFF

2.9

170

111

19.0

-0.5

4.2

207

151

27.0

188

131

23.3

-0.1

RON=20kW,ROFF=17kW

CF=220pF

Oscillating frequency during

fOSCSOFT

VSOFT=2.5V

kHz

SOFT operation

VSOFT=0.2V

ISOFTIN

ISOFDIS

VSOFT=1V

SOFT terminal input current

µA

Discharge current of SOFT terminal at

Vcc less than Vcc(STOP)

SOFT terminal discharging current

Regulator output voltage

1

3.3

7.8

mA

6.8

8.8

0.4

1.4

1.0

2.0

VREG

V

Vcc=18V,Io=10mA

Vcc=18V,Io=100mA

Vcc=5V,Io=1mA

0.04

0.7

VOL1

VOL2

VOL3

VOL4

Output low voltage

0.85

1.3

Vcc=5V,Io=100mA

Vcc=18V,Io=-10mA

Vcc=18V,Io=-100mA

16.0

15.5

VOH1

VOH2

TRISE

TFALL

16.7

16.5

60

Output high voltage

V

ns

V

Output voltage rise time

Output voltage fall time

Detection voltage

40

2.5

2.4

30

2.6

3.0

VDET

IINDET

µA

dB

DET terminal input current

Voltage gain of detection amp

VDET=2.5V

1.0

40

GAVDET

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

TYPICAL CHARACTERISTICS

THERMAL DERATING

(MAXIMUM RATING)

CIRCUIT CURRENT VS.SUPPLY VOLTAGE

(NORMAL OPERATION)

1800

16m

14m

12m

10m

fOSC=500kHz

RON=18kW

ROFF=20kW

1500

1200

fOSC=100kHz

900

150m

100µ

50µ

600

300

Ta=-30°C

Ta=25°C

Ta=85°C

0

10

15

25

35

0

5

20

30

40

85

100

0

25

50

75

125

150

SUPPLY VOLTAGE Vcc(V)

AMBIENT TEMPERATURE Ta(°C)

SOFT TERMINAL INPUT VOLTAGE VS.

EXPANSION RATE OF PERIOD

SOFT TERMINAL INPUT VOLTAGE VS.

EXPANSION RATE OF PERIOD

5.0

4.5

(fOSC=100kHz)

(fOSC=500kHz)

4.5

4.0

3.5

3.0

2.5

2.0

4.0

3.5

RON=15k,ROFF=27k

RON=18k,ROFF=24k

RON=22k,ROFF=22k

RON=24k,ROFF=20k

RON=22k,ROFF=12k

RON=36k,ROFF=6.2k

1

2

3

RON=15k,ROFF=27k

RON=18k,ROFF=24k

RON=22k,ROFF=22k

RON=24k,ROFF=20k

RON=22k,ROFF=12k

RON=36k,ROFF=6.2k

1

2

3

4

5

3.0

2.5

4

5

6

2.0

1.5

1.0

0.5

0

4

2

6

1

3

5

4

2

6

1

3

5

0

2

4

6

8

10 12 14 16 18 20

EXPANSION RATE OF PERIOD(TIMES)

0

2

4

6

8

10 12 14 16 18 20

EXPANSION RATE OF PERIOD(TIMES)

CLM+ TERMINAL THRESHOLD VOLTAGE

VS. AMBIENT TEMPERATURE

SOFT TERMINAL INPUT VOLTAGE VS.

INPUT VOLTAGE

-100

-90

-80

-70

205

200

195

-60

-50

-40

Ta=-30°C

Ta=25°C

Ta=85°C

-30

-20

-10

0

10

SOFT TERMINAL INPUT VOLTAGE VSOFT(V)

100

0

2

3

4

5

6

7

9

-40 -20

0

20

40 60 80

1

8

-60

AMBIENT TEMPERATURE Ta(°C)

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

CLM+ TERMINAL CURRENT

REG OUTPUT VOLTAGE

VS. CLM+ TERMINAL VOLTAGE

VS. AMBIENT TEMPERATURE

-400

-300

-200

-100

0

8.5

8.0

Rc=¥

Rc=3.6k

Rc=1.5k

Ta=-30°C

Ta=25°C

Ta=85°C

7.5

7.0

100

-60 -40 -20

0

20

40 60 80

0

0.3

1.0

0.4 0.5 0.6 0.7 0.8 0.9

0.1 0.2

AMBIENT TEMPERATURE Ta(°C)

CLM+ TERMINAL VOLTAGE VCLM+(V)

OUTPUT HIGH VOLTAGE VS.

SOURCE CURRENT

OUTPUT LOW VOLTAGE

VS. SINK CURRENT

4.5

4.2

3.9

3.6

3.3

3.0

2.7

2.4

2.1

1.8

1.5

1.2

5.0

Ta=25°C

4.5

4.0

Vcc=18V

Ta=25°C

3.5

3.0

2.5

2.0

Vcc=18V

Vcc=5V

1.5

1.0

0.5

0

10⁰

10¹

3

2

5

2

5

2

3

5

2

3

5

10^-2

10^-1

2

3

5

2

3

5

2

3

5

10^-3

10^-2

10^-1

2

3

5

10^-3

10⁰

SINK CURRENT IOL(A)

SOURCE CURRENT IOH(A)

DETECTION TERMINAL INPUT CURRENT

VS. AMBIENT TEMPERATURE

DETECTION VOLTAGE

VS. AMBIENT TEMPERATURE

1.4

1.3

2.55

2.50

1.2

1.1

1.0

0.9

0.8

2.45

2.40

0.7

0

100

-40 -20

0

20

40 60 80

-60

100

-40 -20

0

20

40 60 80

-60

AMBIENT TEMPERATURE Ta(°C)

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

VOLTAGE GAIN OF DETECTION AMP

VS. FREQUENCY

ON duty

VS. F/B TERMINAL INPUT CURRENT

50

45

50

(fOSC=100kHz)

RON=18kW

ROFF=20kW

45

40

35

30

25

20

15

10

Ta=-30°C

25

20

15

Ta=25°C

Ta=85°C

10

5

0

10⁶

10³

10⁴

0

2

3

5

2

3

5

2

3

5

2

3

5

10²

10⁵

0

0.4

1.0

2.0

1.2 1.4 1.6 1.8 2.2

0.6 0.8

F/B TERMINAL INPUT CURRENT IF/B (mA)

FREQUENCY f(Hz)

ON duty VS.

F/B TERMINAL INPUT CURRENT

ON duty

VS. F/B TERMINAL INPUT CURRENT

50

40

(fOSC=500kHz)

RON=18kW

ROFF=20kW

(fOSC=200kHz)

RON=18kW

ROFF=20kW

40

30

20

10

30

20

Ta=-30°C

Ta=25°C

Ta=-30°C

Ta=25°C

Ta=85°C

10

0

0.4

2.0

2.2

0

0.6 0.8 1.0 1.2 1.4 1.6 1.8

0

0.4

1.0

2.0

1.2 1.4 1.6 1.8 2.2

0.6 0.8

F/B TERMINAL INPUT CURRENT IF/B (mA)

F/B TERMINAL INPUT CURRENT IF/B(mA)

UPPER & LOWER LIMIT VOLTAGE OF OSC

VS. AMBIENT TEMPERATURE

OSCILLATING FREQUENCY VS. CF

TERMINAL CAPACITANCE

10 ⁴

5

RON=18kW

ROFF=20kW

5.2

4.8

RON=22kW

ROFF=12kW

3

2

10 ³

5

4.4

4.0

fOSC=500kHz

fOSC=200kHz

fOSC=100kHz

3

2

10²

RON=36kW

ROFF=6.2kW

5

3

2

RON=24kW

ROFF=20kW

fOSC=100kHz

fOSC=200kHz

fOSC=500kHz

2.2

2.0

1.8

10¹

5

3

2

10⁰

2

3

5

2

3

5

3

2

3

5

10⁰

10¹

10 ⁴

10 ³

10 ²

100

-40 -20

0

20

40 60 80

-60

AMBIENT TEMPERATURE Ta(°C)

CF TERMINAL CAPACITANCE(pF)

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

OSCILLATOR FREQUENCY VS.

AMBIENT TEMPERATURE

ON duty VS. ROFF

100

90

80

70

60

50

40

30

20

10

0

120

110

RON=24kW

ROFF=20kW

CF=330pF

RON=75kW

51kW

36kW

100

90

24kW

22kW

18kW

15kW

10kW

80

10⁰

10 ¹

ROFF(kW)

10 ²

5

7

5

7

3

100

-40 -20

0

20

40 60 80

-60

AMBIENT TEMPERATURE Ta(°C)

OSCILLATOR FREQUENCY VS.

AMBIENT TEMPERATURE

ON duty VS. AMBIENT TEMPERATURE

700

600

100

90

80

70

60

50

40

30

20

10

0

(fOSC=100kHz)

RON=24kW

ROFF=20kW

CF=47pF

RON=36k,ROFF=6.2k

RON=22k,ROFF=12k

500

RON=24k,ROFF=20k

RON=22k,ROFF=22k

400

300

200

RON=18k,ROFF=24k

RON=15k,ROFF=27k

100

-40 -20

0

20

40 60 80

-60

100

-40 -20

0

20

40 60 80

-60

AMBIENT TEMPERATURE Ta(°C)

ON duty VS. AMBIENT TEMPERATURE

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

(fOSC=200kHz)

(fOSC=500kHz)

RON=36k,ROFF=6.2k

RON=22k,ROFF=12k

RON=36k,ROFF=6.2k

RON=22k,ROFF=12k

RON=24k,ROFF=20k

RON=22k,ROFF=22k

RON=24k,ROFF=20k

RON=22k,ROFF=22k

RON=18k,ROFF=24k

RON=15k,ROFF=27k

100

-40 -20

0

20

40 60 80

-60

100

-40 -20

0

20

40 60 80

-60

AMBIENT TEMPERATURE Ta(°C)

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7

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

OVP TERMINAL THRESHOLD VOLTAGE

VS.AMBIENT TEMPERATURE

OVP TERMINAL INPUT VOLTAGE VS.

INPUT CURRENT

1.1

1m

100µ

10µ

Vcc=18V

Ta=85°C

Ta=25°C

Ta=-30°C

1.0

0.9

H threshold voltage

(VTHOVPH)

0.8

0.7

0.6

0.5

0.4

0.3

L threshold voltage

(VTHOVPL)

1µ

-40 -20

0

20 40

60

80 100

0.2

0.4

0.6

0.8

1.0

AMBIENT TEMPERATURE Ta(°C)

OVP TERMINAL INPUT VOLTAGE VOVP(V)

CURRENT FROM OVP TERMINAL FOR

OVP RESET VS.SUPPLY VOLTAGE

CIRCUIT CURRENT VS.SUPPLY VOLTAGE

(OVP OPERATION)

800

700

600

500

400

300

200

100

0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0

OVP RESET POINT

8.87V(-30°C)

8.94V(25°C)

9.23V(85°C)

Ta=-30°C

Ta=25°C

Ta=85°C

Ta=-30°C

Ta=25°C

Ta=85°C

15

25

35

5

40

40.0

10

20

30

0

10.0

20.0

30.0

0

SUPPLY VOLTAGE Vcc(V)

OUTPUT THRUGH CURRENT WAVEFORM

AT RISING EDGE OF OUTPUT PULSE

AT FALLING EDGE OF OUTPUT PULSE

Horizontal-axis : 20ns/div

Vertical-axis : 5mA/div

Horizontal-axis : 20ns/div

Vertical-axis : 50mA/div

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

FUNCTION DESCRIPTION

parts can be reduced and also parts can be replaced by

reasonable one.

In the following circuit diagram,MOS-FIT is used for output

transistor,however bipolar transistor can be replaced with no

problem.

Type M51996AP and M51996AFP are especially designed for

off-line primary PWM control IC of switching mode power supply

to get DC voltage from AC power supply.

Using this IC,smart SMPS can be realized with reasonable

cost and compact size as the number of external electric

RUSH CURRENT

PREVENTION CIRCUIT

DC OUTPUT

R1

Vcc

COLLECTOR

VOUT

REG

CLM+

EMITTER

GND

R2

CVcc

M51996AP/FP

AC

INPUT

CFIN

SOFT

DET

OVP F/B

T-ON

T-OFF

CF

ROFF

RON

FEEDBACK

OVP

(TL431)

Fig.1 Application example for feed forward regulator

RUSH CURRENT

PREVENTION CIRCUIT

DC OUTPUT

R1

Vcc

COLLECTOR

VOUT

F/B

CLM+

EMITTER

GND

DET

REG

M51996AP/FP

AC

INPUT

CVcc

CFIN

SOFT

DET

T-ON

T-OFF

CF

ROFF

RON

Fig.2 Application example for fly-back regulator

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M51996AP/FP

SWITCHING REGULATOR CONTROL

Start-up circuit section

~

where VOSCH

VOSCL

4.4V

2.0V

The start-up current is such low current level as typical 100µ

A,as shown in Fig.3,when the Vcc voltage is increased

from low level to start-up voltage Vcc(START).

In this voltage range,only a few parts in this IC,which has the

function to make the output voltage low level,is alive and

Icc current is used to keep output low level.The large voltage

difference between Vcc(START) and Vcc(STOP) makes start-up

easy,because it takes rather long duration from Vcc(START) to

Vcc(STOP).

~

CF is discharged by the summed-up of ROFF current and one

sixteenth (1/16) of RON current by the function of Q2,Q3 and Q4

when SW1,SW2 are switched to "discharge side".

5.8V

Q4

Q1

1/16

T-ON

CHARGING

SW1

Q3

RON

Icco

11mA

T-OFF

CF

~

FROM

SWITCHED BY

VF SIGNAL

CHARGING AND

DISCHARGING

SIGNAL

ROFF

~

Vz 4.2V

CF

SW2

IccL

~

Q2

DISCHARGING

100µA

Vcc

(STOP)

Vcc

(START)

M51996A

~

9.9V

16.2V

Fig.4 Schematic diagram of charging and discharging

control circuit for OSC.capacitor CF

SUPPLY VOLTAGE Vcc(V)

Fig.3 Circuit current vs.supply voltage

VOSCH

~

4.4V

Oscillator section

VOSCL

The oscillation waveform is the triangle one.The ON-duration

of output pulse depends on the rising duration of the triangle

waveform and dead-time is decided by the falling duration.

The rising duration is determined by the product of external

resistor RON and capacitor CF and the falling duration is mainly

determined by the product of resistor ROFF and capacitor CF.

~

2.0V

(1)Oscillator operation when SOFT circuit does

not operate

VOH

VOL

Fig.4 shows the equivalent charging and discharging circuit

diagram of oscillator.

The current flows through RON from the constant voltage source

of 5.8V.CF is charged up by the same amplitude as RON

current,when internal switch SW1,SW2 is switched to "charging

side".The rise rate of CF terminal is given as

Fig.5 OSC.waveform at normal condition (no-

operation of intermittent action and OSC.control

circuit)

VT - ON

RON X CF

~

(V/s)

................................................(1)

So fall rate of CF terminal is given as

VT - OFF

ROFF X CF

VT - ON

16 X RON X CF

~

where VT - ON

~

4.5V

+

(V/s)

.....................(3)

The maximum on duration is approximately given as

The minimum off duration approximately is given as

(VOSCH-VOSCL) X RON X CF

~

(s)

........................(2)

(VOSCH-VOSCL) X CF

VT-OFF

ROFF

~

VT - ON

(s)

.....................................(4)

VT-ON

+

16 X RON

~

where VT - OFF

3.5V

The cycle time of oscillation is given by the summation of

Equations 2 and 4.

The frequency including the dead-time is not influenced by the

temperature because of the built-in temperature compensating

circuit.

10

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MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

(2)Oscillator operation when the SOFT(soft

start) circuit is operating.

START FROM 0V

VOSCH

Output transistor is protected from rush current by CLM function

at the start time of power on.SOFT terminal is used to improve

the rising response of the output voltage of power

supply(prevention of overshooting).

VOSCL

The ON duration of output is kept constant,and the OFF

duration is extended as the SOFT terminal voltage becomes

lower by the soft start circuit of this IC.

0

The maximum value of extension is set internally at

approximately sixteen times of the maximum ON duartion.

The features of this method are as follows:

1 It is ideal for primary control as IC driving current is supplied

from the third widing of the main transformer at the start-up

because constant ON duration is obtained from start-up.

2 It is possible to get a wide dynamic range for ON/OFF ratio

by pulse-by-pulse current limit circuit.

3 The response characteristics at power-on is not affected by

input voltage as the pulse-by-pulse limit current value is not

affected by the input voltage.

Fig.6 shows the circuit diagram of the soft start.If SOFT terminal

voltage is low,T-OFF terminal voltage bocomes low and VT-OFF

in equations (3) and (4) become low.

THE FIRST

OUTPUT PULSE

VOH

NO OUTPUT

PULSE

VOL

0

t

Fig.8 Relationship between oscillator waveform and

output waveform at start-up

Fig.7 shows the relationship between oscillator waveform and

output pulse.

If the SOFT terminal voltage is VSOFT,the rise rate of CF

terminal given as

TO REG

TERMINAL

TO REG

TERMINAL

RSOFT

VT - ON

~

(V/S)

..............................................................(5)

SOFT

TERMINAL

RON • CF

The fall rate of oscillation waveform is given as

CSOFT

T-OFF

TERMINAL

VT - ON

VSOFT - VBE

RON • CF

~

+

.............................(6)

(V/S)

16 • RON • CF

~

Vz 4.2V

GND

TERMINAL

DISCHARGING TRANSISTOR*

IC's INTERNAL CIRCUIT

where

VSOFT;SOFT terminal applied voltage

VBE ~ 0.65V

*Active when operation stops.

If VSOFT - VBE < 0, VSOFT - VBE = 0

If VSOFT - VBE > VT - OFF (~3.5V), VSOFT - VBE =VT - OFF

Fig.6 Circuit diagram of SOFT terminal section and T-

OFF terminal section

VOSCH

~

4.4V

PWM comparator, PWM latch and current limit

latch section

Fig.9 shows the scematic diagram of PWM comparator and

PWM latch section. The on-duration of output waveform

coincides with the rising duration of CF terminal waveform,when

the no output current flows from F/B terminal.

When the F/B terminal has finite impedance and current flows

out from F/B terminal,"A" point potential shown in Fig.9 depends

on this current.So the "A" point potential is close to GND level

when the flow-out current becomes large.

VOSCL

~

2.0V

t

"A" point potential is compared with the CF terminal oscillator

waveform and PWM comparator,and the latch circuit is set

when the potential of oscillator waveform is higher than "A"

point potential.

VOH

VOL

The latch circuit is reset during the dead-time of oscillation

(falling duration of oscillation current).So the "B" point potential

or output waveform of latch circuit is the one shown in Fig.10.

The final output waveform or "C" point potential is got by

combining the "B" point signal and dead-time signal

logically.(please refer to Fig.10)

t

Fig.7 Oscillator waveform when the SOFT circuit is

operating

(

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22

)

11

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

~

7.1V

5.8V

OSC WAVEFORM

OF CF TERMINAL

POINT A

~

VTHCLM 200mV

POINT B

LATCH

CURRENT

TO

OUTPUT

-

+

PWM

COMP

WAVEFORM OF

CLM+ TERMINAL

6S

1S

*1

POINT C

F/B

CURRENT LIMIT

SIGNAL TO SET

LATCH

POINT D

*2

FROM

OSC

M51996

CF

CLM+

WAVEFORM OF

VOUT TERMINAL

*1 Resistor to determine current limit sensitivety

*2 High level during dead time

Fig.11 Operating waveform of current limiting circuit

Fig.9 PWM comparator PWM latch and

current limit latch section

To eliminate the abnormal operation by the noise voltage,the

low pass filter,which consists of RNF and CNF is used as shown

in Fig.12.

It is recommended to use 10 to 100Wfor RNF because such

range of RNF is not influenced by the flow-out current of some

200µA from CLM+ terminal and CNF is designed to have the

enough value to absorb the noise voltage.

OSC WAVEFORM

WAVEFORM AT POINT A

WAVEFORM

OF O.S.C. &

POINT A

M51996

POINT B

POINT C

VOUT

POINT

D

RNF

CNF

CLM+

GND

RCLM

Fig.10 Waveforms of PWM comparator input point A,

latch circuit points B and C

Current limiting section

When the current-limit signal is applied before the crossing

instant of "A" pint potential and CF terminal voltage shown in

Fig.9,this signal makes the output "off" and the off state will

continue until next cycle.Fig.11 shows the timing relation among

them.

If the current limiting circuit is set,no waveform is generated at

output terminal, however this state is reset during the

succeeding dead-time.

So this current limiting circuit is able to have the function in

every cycle,and is named "pulse-by-pulse current limit".

There happen some noise voltage on RCLM during the switching

of power transistor due to the snubber circuit and stray

capacitor of the transformer windings.

Fig.12 Connection diagram of current limit circuit

Voltage detector circuit(DET) section

The DET terminal can be used to control the output voltage

which is determined by the winding ratio of fly back transformer

in fly-back system or in case of common ground circuit of

primary and secondary in feed forward system.

The circuit diagram is quite similar to that of shunt regulator

type 431 as shown in Fig.13.As well known from Fig.13 and

Fig.14,the output of OP AMP has the current-sink ability,when

the DET terminal voltage is higher than 2.5V

(

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22

)

12

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

7.1V

It is necessary to input the sufficient larger current(800µA to

8mA)than I2 for triggering the OVP operation.

500W

3k

The reason to decrease I2 is that it is necessary that Icc at the

OVP rest supply voltage is small.

It is necessary that OVP state holds by circuit current from R1 in

the application example,so this IC has the characteristic of

small Icc at the OVP reset supply voltage(~stand-by current +

20µA)

1S

6S

F/B

DET

5.4k

On the other hand,the circuit current is large in the higher

supply voltage,so the supply voltage of this IC doesn't become

so high by the voltage drop across R1.

10.8k

1.2k

10.8k

This characteristic is shown in Fig.16.

10S

The OVP terminal input current in the voltage lower than the

OVP threshold voltage is based on I2 and the input current in

the voltage higher than the OVP threshold voltage is the sum of

the current flowing to the base of Q3 and the current flowing

from the collector of Q2 to the base.

For holding in the latch state,it is necessary that the OVP

terminal voltage is kept in the voltage higher than VBE of Q3.

So if the capacitor is connected between the OVP terminal and

GND,even though Q2 turns on in a moment by the surge

voltage,etc,this latch action does not hold if the OVP terminal

voltage does not become higher than VBE of Q3 by charging

this capacitor.

For resetting OVP state,it is necessary to make the OVP

terminal voltage lower than the OVP L threshold voltage or

make Vcc lower than the OVP reset supply voltage.

As the OVP reset voltage is settled on the rather high voltage of

9.0V,SMPS can be reset in rather short time from the switch-off

of the AC power source if the smoothing capacitor is not so

large value.

Fig.13 Voltage detector circuit section(DET)

but it becomes high impedance state when lower than

2.5V DET terminal and F/B terminal have inverting

phase characteristics each other,so it is recommended

to connect the resistor and capacitor in series between

them for phase compensation.It is very important one

can not connect by resistor directly as there is the

voltage difference between them and the capacitor has

the DC stopper function.

7.1V

3k

500W

Vcc

1S

6S

7.8V

F/B

100µA

8k

12k

I1

DET

-

OP

AMP

+

Q1

2.5V

Q2

Fig.14 Schmatic diagram of voltage detector circuit section(DET)

400

Q3

OVP

GND

2.5k

OVP circuit(over voltage protection circuit)section

I2

OVP circuit is basically positive feedback circuit constructed

by Q2,Q3 as shown in Fig.15.

I1=0 when OVP operates

Q2,Q3 turn on and the circuit operation of IC stops,when the

input signal is applied to OVP terminal.(threshold voltage ~

750mV)

Fig.15 Detail diagram of OVP circuit

The current value of I2 is about 150µA when the OVP does

not operates but it decreases to about 2µA when OVP

operates.

(

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13

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

RECTIFIED DC

VOLTAGE FROM

SMOOTHING CAPACITOR

8

7

MAIN TRANSFORMER

R1

OVP RESET POINT

8.87V(-30°C)

VF

8.94V(25°C)

9.23V(85°C)

THIRD WINDING OR

BIAS WINDING

Vcc

M51996A

GND

6

5

4

3

Ta=-30°C

Ta=25°C

Ta=85°C

CVcc

2

1

Fig.24 Start-up circuit diagram when it is not

necessary to set the start and stop input voltage

0

10

30

40

20

0

SUPPLY VOLTAGE Vcc(V)

Just after the start-up,the Icc current is supplied from

Cvcc,however,under the steady state condition ,IC will be

supplied from the third winding or bias winding of

transformer,the winding ratio of the third winding must be

designed so that the induced voltage may be higher than the

operation-stop voltage Vcc(STOP).

Fig.16 CIRCUIT CURRENT VS. SUPPLY VOLTAGE

(OVP OPERATION)

The Vcc voltage is recommended to be 12V to 17V as the

normal and optimum gate voltage is 10 to 15V and the output

voltage(VOH) of type M51996AP/FP is about(Vcc-2V).

It is not necessary that the induced voltage is settled higher

than the operation start-up voltage Vcc(START),and the high gate

drive voltage causes high gate dissipation,on the other hand,too

low gate drive voltage does not make the MOS-FET fully on-

state or the saturation state.

Output section

It is required that the output circuit have the high sink and

source abilities for MOS-FET drive.It is well known that the

"totempole circuit has high sink and source ability.However,it

has the demerit of high through current.

For example,the through current may reach such the high

current level of 1A,if type M51996A has the "conventional"

totempole circuit.For the high frequency application such as

higher than 100kHz,this through current is very important factor

and will cause not only the large Icc current and the inevitable

heat-up of IC but also the noise voltage.

(2)The start-up circuit when it is not necessary to set the

start and stop input voltage

It is recommend to use the third winding of "forward winding"

or "positive polarity" as shown in Fig.18,when the DC source

voltages at both the IC operation start and stop must be

settled at the specified values.

This IC uses the improved totempole circuit,so without

deteriorating the characteristic of operating speed,its through

current is approximately 100mA.

The input voltage(VIN(START)),at which the IC operation

starts,is decided by R1 and R2 utilizing the low start-up

APPLICATION NOTE OF TYPE M51996AP/FP

Design of start-up circuit and the power supply

of IC

RECTIFIED DC

PRIMARY WINDING

OF TRANSFORMER

VIN

VOLTAGE FROM

SMOOTHING CAPACITOR

NP

(1)The start-up circuit when it is not necessary to set the

start and stop input voltage

Fig.17 shows one of the example circuit diagram of the start-up

circuit which is used when it is not necessary to set the start

and stop voltage.

It is recommended that the current more than 300µA flows

through R1 in order to overcome the operation start-up current

Icc(START) and Cvcc is in the range of 10 to 47µF.The product of

R1 by Cvcc causes the time delay of operation,so the response

time will be long if the product is too much large.

R1

VF

THIRD WINDING OF

TRANSFORMER

Vcc

M51996A

GND

NB

R2

CVcc

Fig.18 Start-up circuit diagram when it is not

necessary to set the start and stop input voltage

(

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14

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

current characteristics of type M51996AP/FP.

The input voltage(VIN(STOP)),at which the IC operation stops,is

decided by the ratio of third winding of transformer.

The VIN(START) and VIN(STOP) are given by following equations.

MAIN

TRANSFORMER

THIRD

Vcc

COLLECTOR

R1

R2

~

VIN(START) R1 • ICCL + (

+ 1) • Vcc(START)

...............(7)

WINDING

NP

1

2

+

~

VIN(STOP)

^{(Vcc(STOP)-VF) •}NB

V'IN RIP(P-P)

............(8)

M51996A

CVcc

where

OUTPUT

RCLM

ICCL is the operation start-up current of IC

Vcc(START) is the operation start-up voltage of IC

Vcc(STOP) is the operation stop voltage of IC

VF is the forward voltage of rectifier diode

V'IN(P-P) is the peak to peak ripple voltage of

EMITTER

GND

NB

NP

~

Vcc terminal

V'IN RIP(P-P)

Fig.19 How to design the conductor-pattern of type

M51996A on PC board(schematic example)

It is required that the VIN(START) must be higher than VIN(STOP).

When the third winding is the "fly back winding" or "reverse

polarity",the VIN(START) can be fixed,however,VIN(STOP) can not

be settled by this system,so the auxiliary circuit is required.

(4)Power supply circuit for easy start-up

When IC start to operate,the voltage of the CVCC begins to

decrease till the CVCC becomes to be charged from the third

winding of main-transformer as the Icc of the IC increases

abruptly.In case shown in Fig.17 and 18,some "unstable start-

up" or "fall to start-up" may happen, as the charging interval of

CVCC is very short duration;that is the charging does occur only

the duration while the induced winding voltage is higher than

the CVCC voltage,if the induced winding voltage is nearly equal

to the "operation-stop voltage" of type M51996A.

(3)Notice to the Vcc,Vcc line and GND line

To avoid the abnormal IC operation,it is recommended to

design the Vcc is not vary abruptly and has few spike

voltage,which is induced from the stray capacity between the

winding of main transformer.

To reduce the spike voltage,the Cvcc,which is connected

between Vcc and ground,must have the good high frequency

characteristics.

It is recommended to use the 10 to 47µF for CVCC1,and about 5

times capacity bigger than CVCC1 for CVCC2.

To design the conductor-pattern on PC board,following cautions

must be considered as shown in Fig.19.

(a)To separate the emitter line of type M51996A from the GND

line of the IC

R1

(b)The locate the CVCC as near as possible to type M51996A

and connect directly

(c)To separate the collector line of type M51996A from the Vcc

line of the IC

(d)To connect the ground terminals of peripheral parts of ICs to

GND of type M51996A as short as possible

MAIN

TRANSFORMER

THIRD

WINDING

Vcc

M51996A

CVcc1

CVcc2

GND

Fig.20 DC source circuit for stable start-up

(

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15

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

OVP circuit

(1)To avoid the miss operation of OVP

It is recommended to connect the capacitor between OVP

terminal and GND for avoiding the miss operation by the spike

noise.

TO MAIN

TRANSFORMER

R1

The OVP terminal is connected with the sink current source

(~150µA) in IC when OVP does not operate,for absorbing the

leak current of the photo coupler in the application.

So the resistance between the OVP terminal and GND for leak-

cut is not necessary.

If the resistance is connected,the supply current at the OVP

reset supply voltage becomes large.

As the result,the OVP reset supply voltage may become higher

than the operation stop voltage.

Vcc

~

CFIN

Cvcc

R2

M51996A

GND

In that case,the OVP action is reset when the OVP is triggered

at the supply voltage a little high than the operation stop

voltage.

THE TIME CONSTANT OF

THIS PART SHOULD BE SHORT

So it should be avoided absolutely to connect the resistance

between the OVP terminal and GND.

Fig.22 Example circuit diagram to make the

OVP-reset-time fast

To REG or Vcc

5.6k

Vcc

MAIN

TRANSFORMER

THIRD

Vcc

WINDING

470W

M51996A

OVP

M51996A

PHOTO COUPLER

OVP

CVcc

GND

Fig.21 Peripheral circuit of OVP terminal

FIG.23 OVP setting method using the induced

third winding voltage on fly back system

(2)Application circuit to make the OVP-reset time fast

The reset time may becomes problem when the discharge time

constant of CFIN • (R1+R2) is long. Under such the circuit

condition,it is recommended to discharge the CVCC forcedly and

to make the Vcc low value;This makes the OVP-reset time fast.

(4)Method to control for ON/OFF using the OVP terminal

You can reset OVP to lower the OVP terminal voltage lower

than VTHOVPL.

So you can control for ON/OFF using this nature.

The application is shown in Fig.24.

The circuit turns off by SW OFF and turns on by SW ON in this

application.

Of course you can make use of the transistor or photo-transistor

instead of SW.

(3)OVP setting method using the induced third winding

voltage on fly back system

For the over voltage protection (OVP),the induced fly back type

third winding voltage can be utilized,as the induced third

winding voltage depends on the output voltage.Fig.23 shows

one of the example circuit diagram.

REG

5.1k

M51996A

ON/OFF

SW

FIG.24 Method to control for ON/OFF using the

OVP terminal

(

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16

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

Current limiting circuit

I2

(1)Peripheral circuit of CLM+ terminal

Fig.25 shows the example circuit diagrams around the CLM+

terminal.It is required to connect the low pass filter,in order to

reduce the spike current component,as the main current or

drain current contains the spike current especially during the

turn-on duration of MOS-FIT.

1,000pF to 22,000pF is recommended for CNF and the RNF1

and RNF2 have the functions both to adjust the "current-

detecting-sensitivity" and to consist the low pass filter.

CLM

RCLM

I1

(a) Feed forward system

IP1

IP2

R1

I1

I2

CFIN

INPUT

SMOOTHING

CAPACITOR

COLLECTOR

VOUT

Vcc

Cvcc

M51996A

CLM+

RNF1

RNF2

(b) Primary and secondary current

GND

EMITTER

RCLM

CNF

Fig.26 Primary and secondary current waveforms

under the current limiting operation

Fig.25 Peripheral circuit diagram of CLM+ terminal

condition on feed forward system

To design the RNF1 and RNF2,it is required to consider the

influence of CLM+ terminal source current(IINCLM+),

which value is in the range of 90 to 270µA.

In order to be not influenced from these resistor paralleled value

of RNF1 and RNF2,(RNF1/RNF2)is recommended to be less than

100W.

The RCLM should be the non-inductive resistor.

(2)Over current limiting curve

(a)In case of feed forward system

OUTPUT CURRENT

Fig.26 shows the primary and secondary current wave-forms

under the current limiting operation.

At the typical application of pulse by pulse primary current

detecting circuit,the secondary current depends on the primary

current.As the peak value of secondary current is limited to

specified value,the characteristics curve of output voltage

versus output current become to the one as shown in Fig.27.

Fig.27 Over current limiting curve on feed forward

system

The demerit of the pulse by pulse current limiting system is that

the output pulse width can not reduce to less than some value

because of the delay time of low pass filter connected to the

CLM+ terminal and propagation delay time TPDCLM from CLM+

terminal to output terminal of type M51996A.The typical

TPDCLM+ is 100ns.

As the frequency becomes higher,the delay time must be

shorter.And as the secondary output voltage becomes

higher,the dynamic range of on-duty must be wider;it means

that it is required to make the on-duration much more narrower.

So this system has the demerit at the higher oscillating

frequency and higher output voltage applications.

To prevent that the SOFT terminal is used to lower the

frequency when the curve starts to become vertical.

(

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17

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

BIAS WINDING OF

THE MAIN TRANSFORMER

D2

Vcc

COLLECTOR

CVcc

REG

VOUT

TO OUTPUT TRANSISTOR

500

3K

R3

C

SOFT

M51996A

1S

6S

F/B

REG

M51996A

R1

R2

Q1

D1

Fig.28 Relationship between REG terminal and

F/B terminal

PHOTO-COUPLER

FOR FEED BACK SIGNAL

If the curve becomes vertical because of an excess current, the

output voltage is lowered and no feedback current flows from

feedback photo-coupler;the PWM comparator operates to

enlarge the duty sufficiently,but the signal from the CLM+

section operates to make the pulse width narrower.

Fig.29 Current to lower frequency during over current

Under the condition in which I2 in Fig.26 does not become 0,the

output voltage is proportional to the product of the input voltage

VIN(primary side voltage of the main transformer) and on duty.If

the bias winding is positive,Vcc is approximately proportional to

VIN.The existance of feed back current of the photo-coupler is

known by measuring the F/B terminal voltage which becomes

less than 2VBE in the internal circuit of REG terminal and F/B

terminal if the output current flows from the F/B terminal.

Fig.29 shows an application example.

SOFT

VOUT

TO MAKE THE KNEE POINT HIGH

Q1 is turned on when normal output voltage is controlled at a

certain value.The SOFT terminal is clampedto a high-level

voltage.If the output voltage decreases and the curve starts to

drop,no feed back current flows,Q1 is turned off and the SOFT

terminal responds to the smoothed output voltage.

SOFT

VOUT

It is recommended to use an R1 and R2 of 10kW~30kW.An R3

of 20 to 100kWand C of 1000pF to 8200pF should be used.

To change the knee point of frequency drop,use the circuit in

Fig.30.

TO MAKE THE KNEE POINT LOW

To have a normal SOFT start function in the circuit in Fig.29,use

the circuit in Fig.31.It is recommended to use an R4 of 10kW.

Fig.30 Method to control the knee point of

frequency drop

BIAS WINDING OF

THE MAIN TRANSFORMER

D2

Vcc

COLLECTOR

VOUT

CVcc

TO OUTPUT TRANSISTOR

M51996A

R3

C

SOFT

R4

REG

F/B

R1

RSOFT

CSOFT

D1

Q2

R2

Q1

PHOTO-COUPLER

FOR FEED BACK SIGNAL

Fig.31 Circuit to use frequency drop during the over

current and normal soft start

(

/

22

)

18

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

Output circuit

(b)In case of fly back system

(1)The output terminal characteristics at the Vcc voltage

lower than the "Operation-stop" voltage

The DC output voltage of SMPS depends on the Vcc voltage of

type M51996A when the polarity of the third winding is negative

and the system is fly back.So the operation of type M51996A

will stop when the Vcc becomes lower than "Operation-stop

voltage" of M51996A when the DC output voltage of SMPS

decreases under specified value at over load condition.

However,the M51996A will non-operate and operate

intermittently,as the Vcc voltage rises in accordance with the

decrease of Icc current.

TO MAIN

TRANSFORMER

VOUT

M51996A

The fly back system has the constant output power

characteristics as shown in Fig.32 when the peak primary

current and the operating frequency are constant.

Toavoid anincrease of the output current,the frequency is

lowered when the DC output voltage of SMPS starts to drop

using the SOFT terminal.Vcc is divided and is input to the SOFT

terminal as shown in Fig.33,because the voltage in proportional

to the output voltage is obtained from the bias winding.In this

application example,the current flowing to R3 added to the start-

up current.So please use high resistance or 100kWto 200kWfor

R3.

RCLM

100kW

Fig.34 Circuit diagram to prevent the MOS-FIT gate

potential rising

The output terminal has the current sink ability even though the

Vcc voltage lower than the "Operation-stop" voltage or Vcc(STOP)

(It means that the terminal is "Output low state" and please refer

characteristics of output low voltage versus sink current.)

This characteristics has the merit not to damage the MOS-FIT

at the stop of operation when the Vcc voltage decreases lower

than the voltage of Vcc(STOP),as the gate charge of MOS-

FIT,which shows the capacitive load characteristics to the

output terminal,is drawn out rapidly.

The output terminal has the draw-out ability above the Vcc

voltage of 2V,however,lower than the 2V,it loses the ability and

the output terminal potential may rise due to the leakage

current.

The start-up current is not affected by R3 if R3 is connected to

Cvcc2 in the circuit shown in Fig.20.

POINT THAT Vcc VOLTAGE

OR THIRD WINDING

VOLTAGE DECREASES

UNDER "OPERATION-STOP

VOLTAGE"

In this case, it is recommended to connect the resistor of 100kW

between gate and source of MOS-FIT as shown in Fig.34.

DC OUTPUT CURRENT

Fig.32 Over current limitting curve on fly back system

(2)MOS-FIT gate drive power dissipation

Fig.35 shows the relation between the applied gate voltage

and the stored gate charge.

In the region 1 ,the charge is mainly stored at CGS as the

depletion is spread and CGD is small owing to the off-state of

MOS-FIT and the high drain voltage.

In the region 2 ,the CGD is multiplied by the "mirror effect" as

the characteristics of MOS-FIT transfers from off-state to on-

state.

In the region 3 ,both the CGD and CGS affect to the

characteristics as the MOS-FIT is on-state and the drain

voltage is low.

Vcc

COLLECTOR

SOFT

R3

R4

M51996A

CVcc

F/B

REG

R1

The charging and discharging current caused by this gate

charge makes the gate power dissipation.The relation between

gate drive current ID and total gate charge QGSH is shown by

following equation;

R2

To photo-coupler for feed back signal

_{ID=QGSH • fOSC}.....................................(11)

Fig.33 Current to lower the frequency during the

over current in the fly back system

Where

fOSC is switching frequency

(

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19

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

As the gate drive current may reach up to several tenths

milliamperes at 500kHz operation,depending on the size of

MOS-FIT,the power dissipation caused by the gate current can

not be neglected.

In this case,following action will be considered to avoid heat

up of type M51996A.

DETECTING

VOLTAGE

C1

C

R1

R2

F/B

C2

C4

R3

DET

M51996A

B

20

DRAIN

Fig.37 How to use the DET circuit for the voltage

detector

VDS=80V

15

ID

VDS=200V

VDS=320V

CGD

Fig.38 shows the gain-frequency characteristics between point

B and point C shown in Fig.37.

CDS

3

GATE

VD

The G1, ₁and

are given by following equations;

2

10

CGS

R3

R1/R2

1

VGS

G1=

2

.............................................(10)

............................................(11)

....................................(12)

SOURCE

=

1

C2 • R3

5

0

C1 + C2

C1 • C2 • R3

1

ID=4A

16

=

2

At the start of the operation,there happen to be no output pulse

due to F/B terminal current through C1 and C2,as the potential

of F/B terminal rises sharply just after the start of the operation.

Not to lack the output pulse,is recommended to connect the

capacitor C4 as shown by broken line.

20

8

12

0

4

TOTAL STORED GATE CHARGE(nC)

Please take notice that the current flows through the R1 and R2

are superposed to Icc(START).Not to superpose,R1 is connected

to Cvcc2 as shown in Fig.20.

Fig.35 The relation between applied gate-source

voltage and stored gate charge

GAVDET

(DC VOLTAGE GAIN)

(1) To attach the heat sink to type M51996A

(2) To use the printed circuit board with the good

thermal conductivity

(3) To use the buffer circuit shown next section

G1

2

Log

1

(3)Output buffer circuit

It is recommended to use the output buffer circuit as shown in

Fig.36,when type M51996A drives the large capacitive load or

bipolar transistor.

Fig.38 Gain-frequency characteristics between

point B and C shown in Fig.37

How to get the narrow pulse width during the

start of operation

Fig.39 shows how to get the narrow pulse width during the start

of the operation.If the pulse train of forcedly narrowed pulse-

width continues too long,the misstart of operation may

happen,so it is recommended to make the output pulse width

narrow only for a few pulse at the start of operation.0.1µF is

recommended for the C.

VOUT

M51996A

Fig.36 Output buffer circuit diagram

DET

Fig.37 shows how to use the DET circuit for the voltage detector

and error amplifier.

For the phase shift compensation,it is recommended to

connected the CR network between det terminal and F/B

terminal.

(

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20

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

Driver circuit for bipolar transistor

F/B

When the bipolar transistor is used instead of MOS-FIT,the

base current of bipolar transistor must be sinked by the

negative base voltage source for the switching-off duration,in

order to make the switching speed of bipolar transistor fast one.

In this case,over current can not be detected by detecting

resistor in series to bipolar transistor,so it is recommended to

use the CT(current transformer).

M51996A

100W

TO PHOTO

COUPLER

C

Fig.39 How to get the narrow pulse width

during the start of operation

For the low current rating transistor,type M51996A can drive it

directly as shown in Fig.42.

How to synchronize with external circuit

Type M51996A has no function to synchronize with external

circuit,however,there is some application circuit for

synchronization as shown in Fig.40.

COLLECTOR

Vcc

VOUT

BIPOLAR

TRANSISTOR

M51996A

EMITTER

GND

CF

T-ON

T-OFF

Fig.42 Driver circuit diagram (2) for bipolar transistor

ROFF

CF

RON

Q1

SYNCHRONOUS

PULSE

0V

MINIMUM PULSE

WIDTH OF

SYNCHRONOUS

PULSE

MAXIMUM PULSE WIDTH OF

SYNCHRONOUS PULSE

Fig.40 How to synchronize with external circuit

COLLECTOR

VOUT

Vcc

M51996A

-Vss

(-2V to -5V)

EMITTER

GND

Fig.41 Driver circuit diagram (1) for bipolar transistor

(

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21

MITSUBISHI (Dig./Ana. INTERFACE)

M51996AP/FP

SWITCHING REGULATOR CONTROL

Attention for heat generation

The maximum ambient temperature of type M51996A is

+85°C,however,the ambient temperature in vicinity of the IC is

not uniform and varies place by place,as the amount of power

dissipation is fearfully large and the power dissipation is

generated locally in the switching regulator.

So it is one of the good idea to check the IC package

temperature.

The temperature difference between IC junction and the surface

of IC package is 15°C or less,when the IC junction temperature is

measured by temperature dependency of forward voltage of pin

junction,and IC package temperature is measured by "thermo-

viewer",and also the IC is mounted on the "phenol-base" PC

board in normal atmosphere.

So it is concluded that the maximum case temperature(surface

temperature of IC) rating is 120°C with adequate margin.

(

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22

型号:	M51996AP
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	MITSUBISHI ELECTRIC CORP
零件包装代码：	DIP
包装说明：	DIP, DIP14,.3
针数：	14
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.64
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	30 V
最小输入电压：	12 V
标称输入电压：	18 V
JESD-30 代码：	R-PDIP-T14
JESD-609代码：	e0
长度：	19 mm
功能数量：	1
端子数量：	14
最高工作温度：	85 °C
最低工作温度：	-30 °C
最大输出电流：	1 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP14,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
认证状态：	Not Qualified
座面最大高度：	4.5 mm
子类别：	Switching Regulator or Controllers
最大供电电流 (Isup)：	19 mA
表面贴装：	NO
切换器配置：	SINGLE
最大切换频率：	500 kHz
技术：	BIPOLAR
温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
宽度：	7.62 mm
Base Number Matches：	1

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