Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not
used, connect to GND.
1
VBATT
Output Supply Voltage. When V is greater than VBATT and above the reset threshold, V
connects to
CC
OUT
2
V
OUT
V
. When V falls below VBATT and is below the reset threshold, V connects to VBATT. Connect a 0.1µF
OUT
CC
CC
capacitor from V
to GND. Connect V to V if no backup battery is used.
OUT CC
OUT
3
4
V
CC
Input Supply Voltage, 5V input.
GND
Ground. 0V reference for all signals.
Battery On Output. When V
goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for V
ments greater than 250mA.
switches to VBATT, BATT ON goes high. When V
switches to V
BATT ON
OUT
OUT
CC,
5
6
BATT ON
current require-
OUT
LOW LINE output goes low when V falls below the reset threshold. It returns high as soon as V rises above
the reset threshold.
CC
CC
LOW LINE
External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from V
to
OUT
OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast
and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may
be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).
7
8
OSC IN
Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and
watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1).
OSC SEL has a 10µA internal pull-up.
OSC SEL
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO
9
PFI
goes low. When PFI is not used, connect PFI to GND or V
.
OUT
Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
10
PFO
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran-
sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage
11
WDI
divider between V
and GND, which sets it to mid-supply when left unconnected.
OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and V is above the reset threshold. If CE IN is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first.
CC
12
13
CE OUT
CE IN
Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or V
OUT.
Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset
is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if
WDI is unconnected.
14
WDO
RESET Output goes low whenever V falls below the reset threshold. RESET will remain low typically for
200ms after V crosses the reset threshold on power-up.
CC
CC
15
16
RESET
RESET
RESET is an active-high output. It is open drain, and the inverse of RESET.
g ua ra nte e d to b e va lid d own to VCC = 1V, a nd a n
external 10kΩ pull-down resistor on RESET insures
that it will be valid with VCC down to GND (Figure 1).
As VCC goes below 1V, the gate drive to the RESET
outp ut s witc h re d uc e s a c c ord ing ly, inc re a s ing the
RDS(ON) and the saturation voltage. The 10kΩ pull-
down resistor insures the parallel combination of switch
plus resistor is around 10kΩ and the output saturation
voltage is below 0.4V while sinking 40µA. When using
a 10kΩ external pull-down resistor, the high state for
RESET output with VCC = 4.75V will be 4.5V typical.
For battery voltages ≥ 2V connected to VBATT, RESET
and RESET remain valid for VCC from 0V to 5.5V.
_______________De t a ile d De s c rip t io n
–————–
R E S E T a n d RES ET Ou t p u t s
The MAX691A/MAX693A/MAX800L/MAX800M’s RESET
a nd RESET outp uts e ns ure tha t the µP (with re s e t
inputs a sse rte d e ithe r hig h or low) p owe rs up in a
known state, and prevents code-execution errors dur-
ing power-down or brownout conditions.
The RESET output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
–
When deasserted, RESET sources 1.6mA at typically
VOUT - 0.5V. RESET output is open drain, active high,
and typically sinks 3.2mA with a saturation voltage of
0.1V. When no backup battery is used, RESET output is
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