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AD9248BSTZ-40

日期:2021-3-30类别:会员资讯 阅读:346 (来源:互联网)
公司:
北京显易科技有限公司
联系人:
田小姐
手机:
010-51987308
电话:
086-010-51987308
传真:
086-010-51986915
QQ:
1306610685
地址:
北京市海淀区上地信息路1号2号楼4层404-1
摘要:北京显易科技有限公司小曹: 010-51987308 ; QQ:1306610685;企业QQ:800062492 邮箱:bjxianyi-4@163.com 网址: www.ic158.com

北京显易科技有限公司小曹: 010-51987308 ;

QQ:1306610685;企业QQ:800062492

邮箱:bjxianyi-4@163.com 网址: www.ic158.com

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TERMINOLOGY
Analog Bandwidth
Harmonic Distortion, Third
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The encode rate at which parametric testing is performed.
Output Propagation Delay
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for any range within the ADC)
V
NOISE
=
Z
×
0.001
×
10
FS
dBm
SNR
dBc
Signal
dBFS
10
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differen-
tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak-to-peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Differential Nonlinearity
Where
Z
is the input impedance,
FS
is the full-scale of the
device for the frequency in question,
SNR
is the value for the
particular input level and Signal is the signal level within the
ADC reported in dB below full-scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio (PSRR)
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
Full Scale
SINAD
MEASURED
– 1.76
dB
+
20 log
Actual
ENOB
=
6.02
Encode Pulsewidth/Duty Cycle
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic “1” state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing t
ENCH
in text. At a
given clock rate, these specs define an acceptable Encode duty cycle.
Full-Scale Input Power
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
Expressed in dBm. Computed using the following equation:
V
2
FULL SCALE rms
Z
INPUT
=
10 log
0.001
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
Power
FULL SCALE
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May
be reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc