H5TQ2G83EFR-PBC原装现货热卖

VDD=VDDQ=1.5V +/- 0.075V

? Fully differential clock inputs (CK, CK) operation

? Differential Data Strobe (DQS, DQS)

? On chip DLL align DQ, DQS and DQS transition with CK?transition

? DM masks write data-in at the both rising and falling?edges of the data strobe

? All addresses and CONTROL inputs except data, datastrobes and data masks latched on the rising edges ofthe clock

? Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and14 supported

? Programmable additive latency 0, CL-1, and CL-2?supported

? Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,10

? Programmable burst length 4/8 with both nibble?sequential and interleave mode

? BL SWITCH on the fly