TMS320DM8147SCYE2 原装正品，假一罚十
日期：2017-5-15摘要：深圳市达瑞诚科技有限公司，专业代理销售TI ST NXP ADI IR XILINX
深圳市达瑞诚科技有限公司
联系人：程生
电 话：0755-33532096
手 机：13392816498
1 High-Performance System-on-Chip (SoC)
1.1
123
Features
•
8-Bit Multiplies per Clock Cycle
C674x™ Two-Level Memory Architecture
– 32K-Byte L1P RAM/Cache With EDC
– 32K-Byte L1D RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Caches
With ECC
DSP/EDMA Memory Management Unit
(DEMMU)
– Maps C674x DSP and EDMA TC Memory
Accesses to System Addresses
128K-Bytes On-Chip Memory Controller
(OCMC) RAM
Imaging Subsystem (ISS)
– Camera Sensor Connection
• Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8-/16-bit)
– Image Sensor Interface (ISIF) for Handling
Image/Video Data From the Camera Sensor
– Resizer
• Resizing Image/Video From 1/16x to 8x
• Generating Two Different Resizing
Outputs Concurrently
Programmable High-Definition Video Image
Coprocessing (HDVICP v2) Engine
– Encode, Decode, Transcode Operations
– H.264, MPEG2, VC1, MPEG4, SP/ASP,
JPEG/MJPEG
Media Controller
– Controls the HDVPSS, HDVICP2, and ISS
SGX530 3D Graphics Engine
– Delivers up to 18 MPoly/sec
– Universal Scalable Shader Engine
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
OpenVG 1.0, OpenMax API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
Endianness
– ARM/DSP Instructions/Data – Little Endian
HD Video Processing Subsystem (HDVPSS)
– Two 148.5 MHz HD Video Capture Inputs
• High-Performance DaVinci™ Digital Media
Processors
– Up to 1-GHz ARM® Cortex™-A8 RISC MPU
– Up to 2000 ARM® Cortex™-A8 MIPS
– Up to 750-MHz C674x™ VLIW DSP
– 6000/4500 C674x™ MIPS/MFLOPS
– Fully Software-Compatible with C67x+™,
C64x+™
• ARM® Cortex™-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Microprocessor Core
• NEON™ Multimedia Architecture
• Supports Integer and Floating Point
• Jazelle® RCT Execution Environment
• ARM® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 512K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• TMS320C674x™ Floating-Point VLIW DSP
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Adds Per Clock
and Four DP Adds Every Two Clocks
• Supports up to Two Floating-Point (SP or
DP) Approximate Reciprocal or Square
Root Operations Per Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating-Point
Multiply Supported up to:
– 2 SP x SP
→
SP Per Clock
– 2 SP x SP
→
DP Every Two Clocks
– 2 SP x DP
→
DP Every Three Clocks
– 2 DP x DP
→
DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32 x
32 Multiplies, Four 16 x 16-bit Multiplies
including Complex Multiplies, or Eight 8