全新 原装 现货 热卖 TMS320C31PQL50

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High-Performance Floating-Point DigitalSignal Processor (DSP):– TMS320C31-80 (5 V)25-ns Instruction Cycle Time440 MOPS, 80 MFLOPS, 40 MIPS– TMS320C31-60 (5 V)33-ns Instruction Cycle Time330 MOPS, 60 MFLOPS, 30 MIPS– TMS320C31-50 (5 V)40-ns Instruction Cycle Time275 MOPS, 50 MFLOPS, 25 MIPS– TMS320C31-40 (5 V)50-ns Instruction Cycle Time220 MOPS, 40 MFLOPS, 20 MIPS– TMS320LC31-40 (3.3 V)50-ns Instruction Cycle Time220 MOPS, 40 MFLOPS, 20 MIPS– TMS320LC31-33 (3.3 V)60-ns Instruction Cycle Time183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS
32-Bit High-Performance CPU
16-/32-Bit Integer and 32-/40-BitFloating-Point Operations
32-Bit Instruction Word, 24-Bit Addresses
Two 1K × 32-Bit Single-Cycle Dual-AccessOn-Chip RAM Blocks
Boot-Program Loader
On-Chip Memory-Mapped Peripherals:– One Serial Port– Two 32-Bit Timers– One-Channel Direct Memory Access(DMA) Coprocessor for Concurrent I/Oand CPU Operation
Fabricated Using 0.6 µm EnhancedPerformance Implanted CMOS (EPIC)Technology by Texas Instruments (TI)
132-Pin Plastic Quad Flat Package(PQ Suffix)
Eight Extended-Precision Registers
Two Address Generators With EightAuxiliary Registers and Two AuxiliaryRegister Arithmetic Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic/Logic Unit (ALU) andMultiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-CycleBranches
Conditional Calls and Returns
Interlocked Instructions forMultiprocessing Support
Bus-Control Registers ConfigureStrobe-Control Wait-State Generation

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