全新 原装 现货 热卖 TMS320TCI100BQZLZA

Highest-Performance Fixed-Point DigitalSignal Processors (DSPs)− 1.18-ns Instruction Cycle Time− 850-MHz Clock Rate− Eight 32-Bit Instructions/Cycle− Twenty-Eight Operations/Cycle− 6800 MIPS− Fully Software-Compatible With C62x− TCI100/C6416 Pin-Compatible− Extended Temperature Device Available
VelociTI.2 Extensions to VelociTIAdvanced Very-Long-Instruction-Word(VLIW) TMS320C64x DSP Core− Eight Highly Independent FunctionalUnits With VelociTI.2 Extensions:− Six ALUs (32-/40-Bit), Each SupportsSingle 32-Bit, Dual 16-Bit, or Quad8-Bit Arithmetic per Clock Cycle− Two Multipliers SupportFour 16 x 16-Bit Multiplies(32-Bit Results) per Clock Cycle orEight 8 x 8-Bit Multiplies(16-Bit Results) per Clock Cycle− Non-Aligned Load-Store Architecture− 64 32-Bit General-Purpose Registers− Instruction Packing Reduces Code Size− All Instructions Conditional
Instruction Set Features− Byte-Addressable (8-/16-/32-/64-Bit Data)− 8-Bit Overflow Protection− Bit-Field Extract, Set, Clear− Normalization, Saturation, Bit-Counting− VelociTI.2 Increased Orthogonality
VCP− Supports Over 600 7.95-Kbps AMR− Programmable Code Parameters
TCP− Supports up to Seven 2-Mbps 3GPP(6 Iterations)− Programmable Turbo Code andDecoding Parameters
L1/L2 Memory Architecture− 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)− 128K-Bit (16K-Byte) L1D Data Cache(2-Way Set-Associative)− 8M-Bit (1024K-Byte) L2 Unified MappedRAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)− One 64-Bit (EMIFA), One 16-Bit (EMIFB)− Glueless Interface to AsynchronousMemories (SRAM and EPROM) andSynchronous Memories (SDRAM,SBSRAM, ZBT SRAM, and FIFO)− 1280M-Byte Total Addressable ExternalMemory Space
Enhanced Direct-Memory-Access (EDMA)Controller (64 Independent Channels)
Host-Port Interface (HPI)− User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/SlaveInterface Conforms to PCI Specification 2.2− Three PCI Bus Address Registers:Prefetchable MemoryNon-Prefetchable Memory I/O− Four-Wire Serial EEPROM Interface− PCI Interrupt Request Under DSPProgram Control− DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports− Direct Interface to T1/E1, MVIP, SCSAFramers− Up to 256 Channels Each− ST-Bus-Switching-, AC97-Compatible− Serial Peripheral Interface (SPI)Compatible (Motorola)
Three 32-Bit General-Purpose Timers
UTOPIA− UTOPIA Level 2 Slave ATM Controller− 8-Bit Transmit and Receive Operationsup to 50 MHz per Direction− User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†)Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package(GLZ, ZLZ and CLZ Suffixes), 0.8-mm BallPitch
0.09-µm/7-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (850 MHz)

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