全新 原装 现货 热卖 ICS8543BGILF

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Features• Four differential LVDS output pairs• Selectable differential CLK, nCLK or LVPECL clock inputs• CLK, nCLK pair can accept the following differential input levels:LVPECL, LVDS, LVHSTL, SSTL, HCSL• PCLK, nPCLK pair can accept the following differential inputlevels: LVPECL, CML, SSTL• Maximum output frequency: 800MHz• Translates any single-ended input signals to LVDS levels withresistor bias on nCLK input• Additive phase jitter, RMS: 0.164ps (typical)• Output skew: 40ps (maximum)• Part-to-part skew: 500ps (maximum)• Propagation delay: 2.6ns (maximum)• Full 3.3V supply mode• 0°C to 70°C ambient operating temperature• Available in both standard (RoHS 5) and lead-free (RoHS 6)packages

General DescriptionThe ICS8543 is a low skew, high performance 1-to-4Differential-to-LVDS Clock Fanout Buffer. Utilizing Low VoltageDifferential Signaling (LVDS) the ICS8543 provides a low power, lownoise, solution for distributing clock signals over controlledimpedances of 100Ω. The ICS8543 has two selectable clock inputs.The CLK, nCLK pair can accept most standard differential inputlevels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTLinput levels. The clock enable is internally synchronized to eliminaterunt pulses on the outputs during asynchronousassertion/deassertion of the clock enable pin.Guaranteed output and part-to-part skew characteristics make theICS8543 ideal for those applications demanding well definedperformance and repeatability.

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