MM74HCT374WM全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号MM74HCT374WM的概述

MM74HCT374WM 概述 MM74HCT374WM 是一款高性能 CMOS 74HCT 系列 D 触发器，具有 8 位并行输入和 8 位并行输出的特性，适用于各种数字电路应用。这款芯片的设计兼容 TTL（晶体管-晶体管逻辑）电路，支持多种逻辑电平，能够在较宽的电源电压范围内稳定工作。其内建具有触发功能的锁存器，适合用于数据储存、寄存器文件以及其他逻辑应用。详细参数 MM74HCT374WM 的电气特性与参数如下： 1. 输入电压范围： - Vih（高电平输入阈值）: 2.0V（典型值） - Vil（低电平输入阈值）: 0.8V（典型值） 2. 电源电压： - Vcc: 4.5V 至 5.5V（标准工作电压为 5V） 3. 工作温度范围： - -40°C 至 +125°C 4. 输出驱动能力： - Ioh（高电平输出电流）: ±25mA - ...

产品型号MM74HCT374WM的Datasheet PDF文件预览

February 1984

Revised February 1999

MM74HCT373 • MM74HCT374

3-STATE Octal D-Type Latch •

3-STATE Octal D-Type Flip-Flop

requirements, are transferred to the Q outputs on positive

going transitions of the CLOCK (CK) input. When a high

logic level is applied to the OUTPUT CONTROL (OC)

input, all outputs go to a high impedance state, regardless

of what signals are present at the other inputs and the state

of the storage elements.

General Description

The

MM74HCT373

octal

D-type

latches

and

MM74HCT374 Octal D-type flip flops advanced silicon-

gate CMOS technology, which provides the inherent bene-

fits of low power consumption and wide power supply

range, but are LS-TTL input and output characteristic &

pin-out compatible. The 3-STATE outputs are capable of

driving 15 LS-TTL loads. All inputs are protected from dam-

age due to static discharge by internal diodes to V_CCand

MM74HCT devices are intended to interface between TTL

and NMOS components and standard CMOS devices.

These parts are also plug in replacements for LS-TTL

devices and can be used to reduce power consumption in

existing designs.

ground.

When the MM74HCT373 LATCH ENABLE input is HIGH,

the Q outputs will follow the D inputs. When the LATCH

ENABLE goes LOW, data at the D inputs will be retained at

the outputs until LATCH ENABLE returns HIGH again.

When a high logic level is applied to the OUTPUT CON-

TROL input, all outputs go to a high impedance state,

regardless of what signals are present at the other inputs

and the state of the storage elements.

Features

■ TTL input characteristic compatible

■ Typical propagation delay: 20 ns

■ Low input current: 1 µA maximum

■ Low quiescent current: 80 µA maximum

■ Compatible with bus-oriented systems

■ Output drive capability: 15 LS-TTL loads

The MM74HCT374 are positive edge triggered flip-flops.

Data at the D inputs, meeting the setup and hold time

Ordering Code:

Order Number

MM74HCT373WM

MM74HCT373SJ

MM74HCT373MTC

MM74HCT373N

MM74HCT373WM

MM74HCT373SJ

MM74HCT373MTC

MM74HCT373N

Package Number

M20B

Package Descriptions

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M20D

MTC20

N20A

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

M20B

M20D

MTC20

N20A

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS005367.prf

www.fairchildsemi.com

Connection Diagrams

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

MM74HCT374

MM74HCT373

Truth Tables

MM74HCT373

MM74HCT374

Output

Data

373

Output

Clock

Data

Output

Control

Output

Control

(374)

↑

Q₀

H = HIGH Level

L = LOW Level

H = HIGH Level

L = LOW Level

X = Don’t Care

= Level of output before steady-state input conditions were established.

↑ = Transition from LOW-to-HIGH

Z = High Impedance State

Z = High Impedance

= The level of the output before steady state input conditions were

established.

www.fairchildsemi.com

Logic Diagrams

MM74HCT373

MM74HCT374

www.fairchildsemi.com

Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended Operating

Conditions

Supply Voltage (V_CC

DC Input Voltage (V_IN

DC Output Voltage (V_OUT

Clamp Diode Current (I_IK, I_OK

DC Output Current, per pin (I_OUT

DC V_CCor GND Current, per pin (I_CC

)

−0.5 to +7.0V

−1.5 to V_CC+1.5V

−0.5 to V_CC+0.5V

±20 mA

Min

Max Units

)

Supply Voltage (V_CC

DC Input or Output Voltage

(V_IN, V_OUT

)

4.5

5.5

)

V_CC

)

±35 mA

Operating Temperature Range (T_A) −40

Input Rise or Fall Times

(t_r, t_f)

+85

°C

)

±70 mA

Storage Temperature Range (T_STG

Power Dissipation (P_D)

(Note 3)

)

−65°C to +150°C

500

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

600 mW

500 mW

Note 2: Unless otherwise specified all voltages are referenced to ground.

S.O. Package only

Note 3: Power Dissipation temperature derating — plastic “N” package: −

12 mW/°C from 65°C to 85°C.

Lead Temperature (T_L)

(Soldering 10 seconds)

260°C

DC Electrical Characteristics

= 5V ± 10% (unless otherwise specified)

= 25°C

= −40 to 85°C

T = −55 to 125°C

Symbol

Parameter

Conditions

Units

Typ

Guaranteed Limits

Minimum HIGH Level

Input Voltage

2.0

0.8

Maximum LOW Level

Input Voltage

0.8

Minimum HIGH Level

Output Voltage

= V or V

IH IL

| = 20 µA

− 0.1

V − 0.1

OUT

| = 6.0 mA, V = 4.5V

4.2

5.7

3.98

4.98

3.84

3.7

| = 7.2 mA, V = 5.5V

4.84

4.7

Maximum LOW Level

Voltage

= V or V

IH IL

| = 20 µA

0.1

0.4

OUT

| = 6.0 mA, V = 4.5V

0.2

0.26

±0.1

0.33

±1.0

| = 7.2 mA, V = 5.5V

0.4

Maximum Input

Current

= V or GND,

±1.0

µA

or V

Maximum 3-STATE

Output Leakage

Current

= V or GND

±0.5

±5.0

±10

µA

OUT

Enable = V or VIL

Maximum Quiescent

Supply Current

= V or GND

8.0

1.0

160

1.5

µA

= 0 µA

OUT

= 2.4V or 0.5V (Note 4)

1.3

Note 4: Measured per pin. All others tied to V or ground.

www.fairchildsemi.com

AC Electrical Characteristics

MM74HCT373: V_CC= 5.0V, t = t = 6 ns T = 25°C (unless otherwise specified)

Guaranteed

Limit

Symbol

, t

Parameter

Conditions

Typ

Units

Maximum Propagation Delay

Data to Output

= 45 pF

PHL PLH

, t

Maximum Propagation Delay

Latch Enable to Output

PHL PLH

, t

Maximum Enable Propagation Delay

Control to Output

= 45 pF

= 1 kΩ

= 5 pF

= 1 kΩ

PZH PZL

, t

Maximum Disable Propagation Delay

Control to Output

PHZ PLZ

Minimum Clock Pulse Width

Minimum Setup Time Data to Clock

Minimum Hold Time Clock to Data

AC Electrical Characteristics

MM74HCT373: V_CC= 5.0V ± 10%, t = t = 6 ns (unless otherwise specified)

=25°C

T =−40 to 85°C T =−55 to 125°C

A A

Symbol

, t

Parameter

Conditions

Units

Typ

Guaranteed Limits

Maximum Propagation

Delay Data to Output

= 50 pF

PHL PLH

= 150 pF

= 50 pF

= 150 pF

= 50 pF

= 150 pF

= 1 kΩ

, t

Maximum Propagation Delay

Latch Enable to Output

PHL PLH

, t

Maximum Enable Propagation

Delay Control to Output

PZH PZL

, t

Maximum Disable Propagation

Delay Control to Output

= 50 pF

= 1 kΩ

PHZ PLZ

, t

Maximum Output Rise

= 50 pF

THL TLH

and Fall Time

Minimum Clock Pulse Width

Minimum Setup Time Data to Clock

Minimum Hold Time Clock to Data

Maximum Input Capacitance

Maximum Output Capacitance

Power Dissipation Capacitance

(Note 5)

OUT

OC = V

OC = GND

Note 5: C determines the no load dynamic power consumption, P = C

2 f + I

, and the no load dynamic current consumption,

PD CC

CC CC

= C

f + I

PD CC

www.fairchildsemi.com

AC Electrical Characteristics

MM74HCT374: V_CC= 5.0V, t = t = 6 ns T = 25°C (unless otherwise specified)

Guaranteed

Symbol

Parameter

Conditions

Typ

Units

Limit

Maximum Clock Frequency

Maximum Propagation Delay

to Output

MHz

MAX

, t

= 45 pF

PHL PLH

, t

Maximum Enable Propagation Delay

Control to Output

= 45 pF

= 1 kΩ

= 5 pF

= 1 kΩ

PZH PZL

, t

Maximum Disable Propagation Delay

Control to Output

PHZ PLZ

Minimum Clock Pulse Width

Minimum Setup Time Data to Clock

Minimum Hold Time Clock to Data

AC Electrical Characteristics

MM74HCT374: V_CC= 5.0V ± 10%, t = t = 6 ns (unless otherwise specified)

= 25°C

= −40 to 85°C T = −55 to 125°C

Symbol

Parameter

Conditions

Units

Typ

Guaranteed Limits

Maximum Clock Frequency

Maximum Propagation Delay

to Output

MHz

MAX

, t

= 50 pF

PHL PLH

= 150 pF

= 50 pF

= 150 pF

= 1 kΩ

, t

Maximum Enable Propagation

Delay Control to Output

PZH PZL

, t

Maximum Disable Propagation

Delay Control to Output

= 50 pF

= 1 kΩ

PHZ PLZ

, t

Maximum Output Rise

= 50 pF

THL TLH

and Fall Time

Minimum Clock Pulse Width

Minimum Setup Time Data to Clock

Minimum Hold Time Clock to Data

Maximum Input Capacitance

Maximum Output Capacitance

Power Dissipation Capacitance

(Note 6)

OUT

OC = V

OC = GND

Note 6:

determines the no load power consumption, P = C

2 f + I

, and the no load dynamic current consumption, I = C

f + I

PD CC

CC CC

PD CC

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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MM74HCT374WM产品参数

型号:	MM74HCT374WM
是否Rohs认证：	不符合
生命周期：	Transferred
零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4
针数：	20
Reach Compliance Code：	unknown
风险等级：	5.1
系列：	HCT
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
长度：	12.8 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	BUS DRIVER
最大频率@ Nom-Sup：	24000000 Hz
最大I（ol）：	0.006 A
位数：	8
功能数量：	1
端口数量：	2
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
电源：	5 V
传播延迟（tpd）：	45 ns
认证状态：	Not Qualified
座面最大高度：	2.65 mm
子类别：	FF/Latches
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
触发器类型：	POSITIVE EDGE
宽度：	7.5 mm
Base Number Matches：	1

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产品型号MM74HCT374WM的概述

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