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产品型号MSM7507-02的Datasheet PDF文件预览

E2U0019-28-81  
This version: Aug. 1998  
Previous version: Nov. 1996  
¡ Semiconductor  
MSM7507-01/02/03  
Single Rail CODEC  
GENERAL DESCRIPTION  
The MSM7507 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400  
Hz with filters for A/D and D/A conversion.  
Designed especially for a single-power supply and low-power applications, the device is  
optimized for ISDN terminals, digital wireless systems, and digital PBX systems.  
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.  
The analog output signal, which is of a differential type and can drive a 600 W load, can directly  
drive a handset receiver.  
FEATURES  
• Single power supply: +5 V ±5%  
• Low power consumption  
Operating mode:  
Power down mode:  
• ITU-T Companding law  
20 mW Typ. 40 mW Max.  
0.03 mW Typ. 0.3 mW Max.  
V
DD  
V
DD  
= 5 V  
= 5 V  
MSM7507-01: m/A-law pin selectable  
MSM7507-02: m-law  
MSM7507-03: A-law  
• Transmission characteristics conforms to ITU-T G.714  
• Built-in PLL eliminates a master clock  
• Serial data rate: 64/128/256/512/1024/2048 kHz  
96/192/384/768/1536/1544/200 kHz  
• Adjustable transmit gain  
• Adjustable receive gain  
• Built-in reference voltage supply  
• Analog output can directly drive a 600 W line transformer  
• The 24-Pin SOP package products provide pin compatibility with the MSM7543/7544  
• The 20-Pin SSOP package products have 1/3 the foot print of conventional products  
• Package options:  
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7507-01GS-K)  
(Product name : MSM7507-02GS-K)  
(Product name : MSM7507-03GS-K)  
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7507-01MS-K)  
(Product name : MSM7507-02MS-K)  
(Product name : MSM7507-03MS-K)  
1/18  
¡ Semiconductor  
MSM7507-01/02/03  
BLOCK DIAGRAM  
PCMOUT  
+
AIN–  
AIN+  
RC  
8th  
AD  
TCONT  
PLL  
LPF  
BPF  
CONV.  
GSX  
XSYNC  
BCLK  
AUTO  
ZERO  
SGC  
SG  
SG  
GEN  
VR  
GEN  
RTIM  
RSYNC  
(ALAW)  
5th  
LPF  
DA  
CONV.  
+
RCONT  
VFRO  
PCMIN  
PDN  
SG  
PWD  
Logic  
PWI  
PWD  
VDD  
+
AG  
AOUT–  
SG  
SG  
DG  
+
AOUT+  
2/18  
¡ Semiconductor  
MSM7507-01/02/03  
PIN CONFIGURATION (TOP VIEW)  
SG 1  
AOUT+ 2  
AOUT– 3  
NC 4  
24 SGC  
23 AIN+  
22 AIN–  
21 GSX  
20 NC  
SG 1  
AOUT+ 2  
AOUT– 3  
PWI 4  
20 SGC  
19 AIN+  
18 AIN–  
17 GSX  
PWI 5  
VFRO 5  
16 NC  
VDD  
VFRO 6  
NC 7  
19 NC  
6
15 (ALAW)*  
14 AG  
18 (ALAW)*  
17 NC  
DG 7  
PDN 8  
V
DD  
8
13 BCLK  
12 XSYNC  
11 PCMOUT  
DG 9  
PDN 10  
16 AG  
RSYNC 9  
PCMIN 10  
15 BCLK  
14 XSYNC  
13 PCMOUT  
RSYNC 11  
PCMIN 12  
NC : No connect pin  
20-Pin Plastic SSOP  
NC : No connect pin  
24-Pin Plastic SOP  
* The ALAW pin is only applied to the MSM7507-01GS-K/MSM7507-01MS-K.  
3/18  
¡ Semiconductor  
MSM7507-01/02/03  
PIN AND FUNCTIONAL DESCRIPTIONS  
AIN+, AIN–, GSX  
Transmit analog input and transmit level adjustment.  
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is  
connected to the output of the op-amp and is used to adjust the level, as shown below.  
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving  
and power down modes, the GSX output is at AG voltage.  
1) Inverting input type  
R1 : variable  
R2 > 20 kW  
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)  
GSX  
AIN–  
AIN+  
SG  
C1  
R2  
+
Analog input  
R1  
Gain = R2/R1 £ 10  
2) Non inverting input type  
C2  
R3 > 20 kW  
AIN+  
AIN–  
GSX  
+
Analog input  
R4 > 20 kW  
R5 > 50 kW  
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)  
R5  
R4  
R3  
SG  
Gain = 1 + R4 / R3 £ 10  
AG  
Analog signal ground.  
VFRO  
Receive filter output.  
The output signal has an amplitude of 2.4 V above and below the signal ground voltage (SG)  
PP  
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.  
For driving a load of 20 kW or less, connect a resistor of 20 kW or more between the pins VFRO  
and PWI.  
Whenaddingthefrequencycharacteristicstothereceivesignal, refertotheapplicationexample.  
During power saving or power down mode, the output of VFRO is at the voltage level of SG.  
4/18  
¡ Semiconductor  
MSM7507-01/02/03  
PWI, AOUT+, AOUT–  
PWI is connected to the inverting input of the receive driver. The receive driver output is  
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,  
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and  
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the  
output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2  
kW, these outputs can directly be connected to a receiver of handset using a piezoelectric  
earphone. Refer to the application example.  
VI  
R6  
R6 > 20 kW  
ZL 1.2 kW  
VFRO  
PWI  
Receive Filter  
R7  
Gain = VO/VI = 2 ¥ R7/R6 £ 2  
AOUT–  
+
SG  
VO  
ZL  
+
AOUT+  
SG  
During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high  
impedance state.  
The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The  
output load resistor has a minimum value of 0.6 kW.  
If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less  
than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC  
APPLICATION NOTE.  
V
DD  
Power supply for +5 V.  
PCMIN  
PCM signal input.  
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the  
RSYNC signal and BCLK signal.  
The data rate of the PCM signal is equal to the frequency of the BCLK signal.  
ThePCMsignalisshiftedatafallingedgeoftheBCLKsignalandlatchedintotheinternalregister  
when shifted by eight bits.  
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.  
BCLK  
Shift clock signal input for the PCMIN and PCMOUT signal.  
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,  
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the  
power saving state.  
5/18  
¡ Semiconductor  
MSM7507-01/02/03  
RSYNC  
Receive synchronizing signal input.  
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive  
synchronizing signal.  
Signals in the receive section are synchronized by this synchronizing signal. This signal must be  
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the  
AC characteristics which are mainly the frequency characteristics of the receive section.  
However, if the frequency characteristic of an applied system is not specified exactly, this device  
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are  
not guaranteed.  
XSYNC  
Transmit synchronizing signal input.  
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit  
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing  
signals of the transmit section.  
This synchronizing signal must be synchronized in phase with BCLK.  
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly  
the frequency characteristics of the transmit section.  
However, if the frequency characteristic of an applied system is not specified exactly, this device  
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are  
not guaranteed.  
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving  
state.  
6/18  
¡ Semiconductor  
MSM7507-01/02/03  
DG  
Ground for the digital signal circuits.  
This ground is separate from the analog signal ground. The DG pin must be connected to the AG  
pin on the printed circuit board to make a common analog ground.  
PDN  
Power down control signal.  
A logic "0" level drives both transmit and receive circuits to a power down state.  
PCMOUT  
PCM signal output.  
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising  
edge of the BCLK signal.  
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK  
and XSYNC.  
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high  
impedance state during power saving or power down modes.  
Apull-upresistormustbeconnectedtothispinbecauseitsoutputisconfiguredasanopendrain.  
This device is compatible with the ITU-T recommendation on coding law and output coding  
format.  
The MSM7507-03 (A-law) outputs the character signal, inverting the even bits.  
PCMIN/PCMOUT  
Input/Output Level  
MSM7507-02 (m-law)  
MSM7507-03 (A-law)  
MSD  
MSD  
+Full scale  
+0  
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0  
–Full scale  
7/18  
¡ Semiconductor  
MSM7507-01/02/03  
SG  
Signal ground voltage output.  
The output voltage is 1/2 of the power supply voltage.  
The output drive current capability is ±300 mA.  
This pin provides the SG level for CODEC peripherals.  
This output voltage level is undefined during power saving or power down modes.  
SGC  
Used to generate the signal ground voltage level by connecting a bypass capacitor.  
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and  
the SGC pin.  
ALAW  
Control signal input of the companding law selection.  
Provides only for the MSM7507-01GS-K/7507-01MS-K. The CODEC will operate in the m-law  
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at  
a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally  
pulled down.  
8/18  
¡ Semiconductor  
MSM7507-01/02/03  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Power Supply Voltage  
Analog Input Voltage  
Digital Input Voltage  
Storage Temperature  
Symbol  
VDD  
Condition  
Rating  
0 to 7  
Unit  
V
VAIN  
–0.3 to VDD + 0.3  
–0.3 to VDD + 0.3  
–55 to +150  
V
VDIN  
TSTG  
V
°C  
RECOMMENDED OPERATING CONDITIONS  
Parameter  
Power Supply Voltage  
Operating Temperature  
Analog Input Voltage  
Input High Voltage  
Symbol  
VDD Voltage must be fixed  
Ta  
Condition  
Min.  
Typ.  
5.0  
+25  
Max.  
Unit  
V
4.75  
–30  
5.25  
+85  
2.4  
°C  
VPP  
V
VAIN Connect AIN– and GSX  
VIH XSYNC, RSYNC, BCLK,  
VIL PCMIN, PDN, ALAW  
2.2  
0
VDD  
0.8  
Input Low Voltage  
V
64, 128, 256, 512, 1024,  
2048, 96, 192, 384, 768,  
1536, 1544, 200  
Clock Frequency  
FC  
BCLK  
kHz  
Sync Pulse Frequency  
Clock Duty Ratio  
FS  
DC  
tIr  
XSYNC, RSYNC  
6.0  
40  
8.0  
50  
9.0  
60  
kHz  
%
BCLK  
Digital Input Rise Time  
Digital Input Fall Time  
XSYNC, RSYNC, BCLK,  
PCMIN, PDN, ALAW  
50  
ns  
tIf  
50  
ns  
tXS  
tSX  
tRS  
tSR  
BCLKÆXSYNC, See Timing Diagram  
XSYNCÆBCLK, See Timing Diagram  
BCLKÆRSYNC, See Timing Diagram  
RSYNCÆBCLK, See Timing Diagram  
100  
100  
100  
100  
1 BCLK  
100  
100  
0.5  
ns  
Transmit Sync Pulse Setting Time  
Receive Sync Pulse Setting Time  
ns  
ns  
ns  
Sync Pulse Width  
PCMIN Set-up Time  
PCMIN Hold Time  
tWS XSYNC, RSYNC  
100  
ms  
ns  
tDS  
tDH  
ns  
RDL Pull-up resistor  
kW  
pF  
Digital Output Load  
CDL  
Voff  
100  
+100  
+10  
500  
Transmit gain stage, Gain = 1  
Transmit gain stage, Gain = 10  
XSYNC, RSYNC  
–100  
–10  
mV  
mV  
ns  
Analog Input Allowable DC Offset  
Allowable Jitter Width  
9/18  
¡ Semiconductor  
MSM7507-01/02/03  
ELECTRICAL CHARACTERISTICS  
DC and Digital Interface Characteristics  
(VDD = +5 V 5%, Ta = –30°C to +85°C)  
Parameter  
Symbol  
Condition  
IDD1 Operating mode  
Power-save mode, PDN = 1,  
XSYNC Æ OFF  
IDD3 Power-down mode, PDN = 0  
Min.  
Typ.  
Max.  
Unit  
5.0  
10  
mA  
Power Supply Current  
IDD2  
1.5  
3.0  
mA  
2.2  
0.0  
0.01  
0.2  
5
0.05  
VDD  
0.8  
2.0  
0.5  
0.4  
10  
mA  
V
Input High Voltage  
VIH  
VIL  
IIH  
IIL  
Input Low Voltage  
V
High Level Input Leakage Current  
Low Level Input Leakage Current  
Digital Output Low Voltage  
Digital Output Leakage Current  
Input Capacitance  
mA  
mA  
V
VOL Pull-up resistance > 500 W  
0.0  
IO  
mA  
pF  
CIN  
Transmit Analog Interface Characteristics  
(VDD = +5 V 5%, Ta = –30°C to +85°C)  
Parameter  
Input Resistance  
Symbol  
Condition  
Min.  
10  
Typ.  
Max.  
Unit  
MW  
kW  
pF  
RINX AIN+, AIN–  
Output Load Resistance  
Output Load Capacitance  
Output Amplitude  
RLGX GSX with respect to SG  
20  
CLGX  
VOGX  
30  
–1.2  
–20  
+1.2  
+20  
V
Offset Voltage  
VOSGX  
Gain = 1  
mV  
Receive Analog Interface Characteristics  
(VDD = +5 V 5%, Ta = –30°C to +85°C)  
Parameter  
Input Resistance  
Symbol  
Condition  
Min.  
10  
Typ.  
Max.  
Unit  
MW  
kW  
RINPW PWI  
RLVF VFRO with respect to SG  
20  
Output Load Resistance  
Output Load Capacitance  
AOUT+, AOUT– (each) with  
RLAO  
0.6  
kW  
respect to SG  
CLVF VFRO  
30  
50  
pF  
pF  
CLAO AOUT+, AOUT–  
VFRO, RL = 20 kW with  
VOVF  
–1.2  
+1.2  
V
respect to SG  
Output Amplitude  
Offset Voltage  
AOUT+, AOUT–, RL = 0.6 kW  
VOAO  
–1.3  
–100  
–100  
+1.3  
+100  
+100  
V
with respect to SG  
VOSVF VFRO with respect to SG  
mV  
mV  
AOUT+, AOUT–, Gain = 1 with  
VOSAO  
respect to SG  
10/18  
¡ Semiconductor  
AC Characteristics  
Parameter  
MSM7507-01/02/03  
(VDD = +5 V 5%, Ta = –30°C to +85°C, SYNC = 8 kHz)  
Freq.  
(Hz)  
Level  
(dBm0)  
Symbol  
Condition Min.  
Typ.  
Max.  
Unit  
Loss T1  
Loss T2  
Loss T3  
Loss T4  
Loss T5  
Loss T6  
LossR1  
LossR2  
LossR3  
LossR4  
LossR5  
SD T1  
SD T2  
SD T3  
60  
300  
20  
26  
+0.07  
Reference  
–0.04  
+0.06  
0.4  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
–0.15  
+0.20  
1020  
2020  
3000  
3400  
300  
Transmit Frequency Response  
Receive Frequency Response  
0
0
–0.15  
–0.15  
0
+0.20  
+0.20  
0.80  
–0.15  
–0.03  
Reference  
0.0  
+0.20  
1020  
2020  
3000  
3400  
–0.15  
–0.15  
0.0  
+0.20  
+0.20  
0.80  
+0.05  
0.56  
43  
3
0
35  
35  
41  
–30  
*1  
35  
38  
Transmit Signal to Distortion Ratio  
1020  
31.5  
31  
dB  
SD T4  
SD T5  
–40  
–45  
*2  
*2  
29  
27  
24  
26  
SD R1  
SD R2  
SD R3  
3
0
36  
36  
36  
43  
41  
–30  
40  
Receive Signal to Distortion Ratio  
1020  
dB  
33.5  
32  
SD R4  
SD R5  
–40  
–45  
*1  
*2  
*2  
30  
30  
25  
27  
GT T1  
GT T2  
GT T3  
GT T4  
GT T5  
GT R1  
GT R2  
GT R3  
GT R4  
GT R5  
3
–0.3  
+0.01  
Reference  
0
+0.3  
–10  
–40  
–50  
–55  
3
Transmit Gain Tracking  
1020  
1020  
–0.3  
–0.5  
–1.2  
–0.3  
+0.3  
+0.5  
+1.2  
+0.3  
dB  
dB  
–0.03  
+0.15  
0
–10  
–40  
–50  
–55  
Reference  
+0.08  
+0.12  
+0.15  
Receive Gain Tracking  
–0.3  
–0.5  
–0.8  
+0.3  
+0.5  
+0.8  
*1 Psophometric filter is used  
*2 Upper is specified for the m-law, lower for the A-law  
11/18  
¡ Semiconductor  
MSM7507-01/02/03  
AC Characteristics (Continued)  
(VDD = +5 V 5%, Ta = –30°C to +85°C, SYNC = 8 kHz)  
Freq.  
(Hz)  
Level  
(dBm0)  
Parameter  
Symbol  
Condition Min.  
Typ.  
Max.  
Unit  
AIN = SG  
–74.5  
–72.5  
–78  
–70  
–69  
–75  
Nidle T  
Idle Channel Noise  
*1 *2  
dBmOp  
Nidle R  
AV T  
*1 *3  
VDD = 5.0 V  
Ta = 25°C  
*4  
0.58  
0.6007  
0.6007  
0.622  
0.622  
Absolute Level (Initial Difference)  
Vrms  
AV R  
AV Tt  
0.58  
–0.2  
1020  
1020  
0
VDD = +5 V  
+0.2  
+0.2  
dB  
dB  
Absolute Level  
5%  
(Deviation of Temperature and Power)  
Ta = –30  
to 85°C *4  
A to A  
BCLK  
AV Rt  
Td  
–0.2  
Absolute Delay  
0
0
0.60  
ms  
ms  
= 64 kHz  
*5  
tgd T1  
tgd T2  
tgd T3  
tgd T4  
tgd T5  
tgdR1  
tgdR2  
tgdR3  
tgdR4  
tgdR5  
CR T  
500  
600  
75  
70  
0.19  
0.11  
0.02  
0.05  
0.07  
0.00  
0.00  
0.00  
0.09  
0.12  
80  
0.75  
0.35  
0.125  
0.125  
0.75  
0.75  
0.35  
0.125  
0.125  
0.75  
Transmit Group Delay  
1000  
2600  
2800  
500  
*5  
600  
Receive Group Delay  
1000  
2600  
2800  
0
0
ms  
dB  
TRANS Æ RECV  
RECV Æ TRANS  
Crosstalk Attenuation  
1020  
CR R  
76  
*1 Psophometric filter is used  
*2 Upper is specified for the m-law, lower for the A-law  
*3 Input "0" code to PCMIN  
*4 AVR is defined at VFRO output  
*5 Minimum value of the group delay distortion  
12/18  
¡ Semiconductor  
MSM7507-01/02/03  
AC Characteristics (Continued)  
(VDD = +5 V 5%, Ta = –30°C to +85°C, SYNC = 8 kHz)  
Freq.  
(Hz)  
4.6 kHz to  
72 kHz  
300 to  
3400  
Level  
(dBm0)  
Parameter  
Discrimination  
Symbol  
Condition Min.  
Typ.  
32  
Max.  
Unit  
dB  
0 to  
DIS  
S
0
0
30  
4000 Hz  
4.6 kHz to  
Out-of-band Spurious  
–37.5  
–52  
30  
–35  
–35  
dBmO  
dBmO  
dB  
100 kHz  
fa = 470  
fb = 320  
0 to  
Intermodulation Distortion  
Power Supply Noise Rejection Ratio  
IMD  
–4  
2fa – fb  
*6  
PSR T  
50 mVPP  
PSR R 50 kHz  
t
20  
20  
20  
20  
200  
200  
200  
200  
SD  
t
XD1  
XD2  
XD3  
Digital Output Delay Time  
CL = 100 pF + 1 LSTTL  
ns  
t
t
*6 The measurement under idle channel noise  
13/18  
¡ Semiconductor  
MSM7507-01/02/03  
TIMING DIAGRAM  
PCM Data Input/Output Timing  
Transmit Timing  
BCLK  
XSYNC  
1
2
3
4
5
6
7
8
9
10  
11  
tXS  
tSX  
tWS  
tXD1  
tSD  
MSD  
tXD2  
D3  
tXD3  
D8  
PCMOUT  
D2  
D4  
D5  
D6  
D7  
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1  
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD  
.
.
Receive Timing  
BCLK  
1
2
3
4
5
6
7
8
9
10  
11  
tRS  
tSR  
tWS  
RSYNC  
PCMIN  
tDS  
tDH  
MSD  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
14/18  
¡ Semiconductor  
MSM7507-01/02/03  
APPLICATION CIRCUIT  
Analog interface  
Digital interface  
+5 V  
MSM7507  
1:1  
1:1  
51 kW  
0.1 mF  
AIN–  
PCMOUT  
PCM signal output  
Analog input  
600 W  
XSYNC  
RSYNC  
BCLK  
8 kHz SYNC signal input  
GSX  
AIN+  
SG  
PCM shift clock input  
PCM data input  
300 W  
300 W  
AOUT+  
PCMIN  
PDN  
Analog output  
600 W  
AOUT–  
PWI  
Power Down control input  
VFRO  
SGC  
AG  
51 kW  
0.1 mF  
0 V  
DG  
+
10 mF  
0–20W  
1 mF  
+5 V  
VDD  
FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT  
Microphone amp  
C1  
Transmit frequency  
characteristic  
Adjustment determined with  
C1, C2, R1, R2  
R1  
M
AIN–  
C2  
R2  
GSX  
AIN+  
SG  
Receive frequency  
characteristic  
Adjustment determined with  
C3, C4, R3, R4  
AOUT+  
AOUT–  
R5  
R4  
C4  
PWI  
VFRO  
R3 C3  
15/18  
¡ Semiconductor  
MSM7507-01/02/03  
RECOMMENDATIONS FOR ACTUAL DESIGN  
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency  
characteristics for the power supply and keep them as close as possible to the device pins.  
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system  
ground with low impedance.  
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an  
IC socket is unavoidable, use the short lead type socket.  
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave  
source such as power supply transformers surround the device.  
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-  
DD  
up phenomenon when turning the power on.  
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)  
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese  
devices.  
16/18  
¡ Semiconductor  
PACKAGE DIMENSIONS  
SOP24-P-430-1.27-K  
MSM7507-01/02/03  
(Unit : mm)  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.58 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
17/18  
¡ Semiconductor  
MSM7507-01/02/03  
(Unit : mm)  
SSOP20-P-250-0.95-K  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.18 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
18/18  
配单直通车
MSM7507-02GS-K产品参数
型号:MSM7507-02GS-K
是否Rohs认证:不符合
生命周期:Obsolete
IHS 制造商:LAPIS SEMICONDUCTOR CO LTD
零件包装代码:SOIC
包装说明:SOP, SOP24,.45
针数:24
Reach Compliance Code:unknown
HTS代码:8542.39.00.01
风险等级:5.35
Is Samacsys:N
压伸定律:MU-LAW
滤波器:YES
JESD-30 代码:R-PDSO-G24
JESD-609代码:e0
长度:15.95 mm
线性编码:NOT AVAILABLE
功能数量:1
端子数量:24
工作模式:SYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP24,.45
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V
认证状态:Not Qualified
座面最大高度:2.5 mm
子类别:Codecs
最大压摆率:0.01 mA
标称供电电压:5 V
表面贴装:YES
技术:CMOS
电信集成电路类型:PCM CODEC
温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.9 mm
Base Number Matches:1
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