NCP1015ST100T3G中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

NCP1015

Self-Supplied Monolithic

Switcher for Low Standby-

Power Offline SMPS

The NCP1015 integrates a fixed−frequency current−mode

controller and a 700 V voltage MOSFET. Housed in a PDIP−7 or

SOT−223 package, the NCP1015 offers everything needed to build a

rugged and low−cost power supply, including soft−start, frequency

jittering, short−circuit protection, skip−cycle, a maximum peak

current set−point and a Dynamic Self−Supply (no need for an auxiliary

winding).

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MARKING

DIAGRAMS

Unlike other monolithic solutions, the NCP1015 is quiet by nature:

during nominal load operation, the part switches at one of the available

frequencies (65−100 kHz). When the current set−point falls below a

given value, e.g. the output power demand diminishes, the IC

automatically enters the so−called skip cycle mode and provides

excellent efficiency at light loads. Because this occurs at typically 0.25

of the maximum peak value, no acoustic noise takes place. As a result,

standby power is reduced to the minimum without acoustic noise

generation.

Short−circuit detection takes place when the feedback signal fades

away e.g. un−true short−circuit or is broken optocoupler cases. Finally

soft−start and frequency jittering further ease the designer task to

quickly develop low−cost and robust offline power supplies.

For improved standby performance, the connection of an auxiliary

winding stops the DSS operation and helps to consume less than

100 mW at high line.

PDIP−7

CASE 626A

AP SUFFIX

P1015APyy

AWL

YYWWG

8

1

4

SOT−223

CASE 318E

ST SUFFIX

4

AYW

1015y G

G

1

yy

y

A

WL

YY

WW

= 06 (65 kHz), 10 (100 kHz)

= A (65 kHz), B (100 kHz)

= Assembly Location

= Wafer Lot

= Year

= Work Week

G or G = Pb−Free Package

(*Note: Microdot may be in either location)

Features

• Built−in 700 V MOSFET with typical R

of 11 W

DS(on)

PIN CONNECTIONS

• Large Creepage Distance between High−voltage Pins

• Current−mode Fixed Frequency Operation: 65 kHz − 100 kHz

• Skip−cycle Operation at Low Peak Currents Only: No Acoustic Noise!

• Dynamic Self−Supply, No Need for an Auxiliary Winding

• Internal 1 ms Soft−start

• Auto−recovery Internal Output Short−circuit Protection

• Frequency Jittering for Better EMI Signature

• Below 100 mW Standby Power if Auxiliary Winding is Used

• Internal Temperature Shutdown

PDIP−7

V

GND

1

2

3

4

8

7

CC

NC

GND

FB

DRAIN

5

(Top View)

SOT−223

• Direct Optocoupler Connection

• SPICE Models Available for TRANsient and AC Analysis

• This is a Pb−Free Device

V

CC

1

FB

2

3

4

GND

Typical Applications

DRAIN

• Low Power ac−dc Adapters for Chargers

• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 20 of this data sheet.

1

Publication Order Number:

March, 2011 − Rev. 3

NCP1015/D

NCP1015

Indicative Maximum Output Power from NCP1015

R

− I

230 Vac

14 W

100 − 250 Vac

6.0 W

DS(on)

p

11 W − 450 mA DSS

11 W − 450 mA Auxiliary Winding

19 W

8.0 W

1. Informative values only, with: T

= 50°C, circuit mounted on minimum copper area as recommended.

amb

V

out

+

100−250 Vac

1

2

3

4

8

7

5

+

GND

Figure 1. Typical Application Example

PIN FUNCTION DESCRIPTION

Pin No.

SOT−223

PDIP−7

Pin Name

Function

Description

1

V

CC

Powers the Internal Circuitry This pin is connected to an external capacitor of typically

10 mF. The natural ripple superimposed on the V

CC

participates to the frequency jittering. For improved

standby performance, an auxiliary V can be connected

CC

to Pin 1. The V also includes an active shunt which

CC

serves as an opto fail−safe protection.

−

2

3

4

NC

GND

FB

−

The IC Ground

Feedback Signal Input

By connecting an optocoupler to this pin, the peak current

setpoint is adjusted accordingly to the output power

demand.

3

−

4

5

−

7

8

DRAIN

−

Drain Connection

−

The internal drain MOSFET connection.

−

GND

The IC Ground

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2

NCP1015

V

CC

Startup Source

1

8

GND

V

CC

Drain

R

sense

High when V t 3 V

CC

UVLO

250 ns

L.E.B.

Management

Reset

2

3

4

7

NC

GND

65 kHz

100 kHz

Clock

Q

Set

EMI Jittering

4 V

Flip−Flop

Driver

D

= 65%

max

Reset

V

CC

18 k

Error flag armed?

GND

−

+

0.5 V

+

Overload?

-

Startup Sequence

Overload

Soft−Start

5

FB

Drain

DRAIN

Figure 2. Simplified Internal Circuit Architecture

Rating

MAXIMUM RATINGS

Symbol

Value

−0.3 to 10

−0.3 to 700

1

Unit

V

CC

Power Supply voltage on all pins, except pin 5 (drain)

Vds

Drain voltage

V

Ids

Drain peak current during transformer saturation

Maximum current into pin 1

A

pk

I_V

15

mA

°C/W

CC

Thermal Characteristics

P Suffix, Case 626A

R

q

Junction−to−Lead

9.0

q

JL

R

Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad

0.36 Sq. Inch (2.32 Sq. Cm)

JA

77

60

1.0 Sq. Inch (6.45 Sq. Cm)

ST Suffix, Plastic Package Case 318E

Junction−to−Lead

Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad

0.36 Sq. Inch (2.32 Sq. Cm)

1.0 Sq. Inch (6.45 Sq. Cm)

14

R

q

JL

q

JA

74

55

TJ

Maximum Junction Temperature

150

°C

kV

V

MAX

Storage Temperature Range

−60 to +150

ESD Capability, Human Body Model (HBM) (All pins except HV)

ESD Capability, Machine Model (MM)

2

200

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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3

NCP1015

ELECTRICAL CHARACTERISTICS (For typical values T =25°C, for min/max values T =−40°Cto125°C, V =8V unless otherwise noted)

J

CC

Symbol

Rating

Min

Typ

Max

Unit

SUPPLY SECTION AND V MANAGEMENT

CC

V

increasing level at which the current source turns−off

decreasing level at which the current source turns−on

1

7.9

6.9

4.4

−

8.5

7.5

9.1

8.1

5.1

−

V

CC(off)

CC

CC(on)

CC

V

Decreasing level at which the Latch−off phase Ends

Hysteresis between V

4.7

CCLATCH

DV

1.0

CC

CC(off)

ICC1

Internal IC consumption, MOSFET switching at 65 kHz

Internal IC consumption, MOSFET switching at 100 kHz

−

0.92

0.95

200

1.1

1.15

300

mA

mV

−

V

Active zener voltage positive offset to V

140

clamp

CC(off)

POWER SWITCH CIRCUIT

Power Switch Circuit on−state resistance (Id = 50 mA)

T = 25°C

R

W

DS(on)

5

−

11

−

19

24

J

T = 125°C

J

V

dsb

Power Switch Circuit & Startup breakdown voltage

5

700

−

V

(I

= 100 mA, T = 25°C)

J

DS(off)

I

Power Switch & Startup breakdown voltage off−state leakage current

T = −40°C (Vds = 650 V)

mA

DS(off)

5

−

70

50

30

120

−

J

T = 25°C (Vds = 700 V)

J

T = 125°C (Vds = 700 V)

J

Switching characteristics (R = 50 W, Vds set for Ids = 0.7 x Ids

)

ns

L

lim

t

Turn−on time (90% − 10%)

Turn−off time (10% − 90%)

5

−

20

10

−

on

off

INTERNAL START−UP CURRENT SOURCE

IC1

High−voltage current source, V = 8 V

0°C < T < 125°C

1

5.0

8.0

10

11

mA

CC

J

−40°C < T < 125°C

J

IC2

High−voltage current source, V = 0

−

10

−

CC

CURRENT COMPARATOR T = 255C (Note 2)

J

I

Maximum internal current set−point

5

405

450

25

495

mA

%

peak

I

Default internal current set−point for skip cycle operation,

−

Lskip

percentage Ipeak

max

t

Propagation delay from current detection to drain OFF state

Leading Edge Blanking Duration

−

125

250

−

ns

DEL

t

LEB

INTERNAL OSCILLATOR

f

Oscillation frequency, 65 kHz version, T = 25°C (Note 2)

59

90

−

65

100

3.3

67

71

110

−

kHz

%

OSC

J

Oscillation frequency, 100 kHz version, T = 25°C (Note 2)

J

f

Frequency dithering compared to switching frequency (with active DSS)

dither

D

Maximum Duty−cycle

62

72

%

max

FEEDBACK SECTION

R

Internal pull−up resistor

4

−

18

−

kW

up

ss

t

Internal soft−start (guaranteed by design)

−

1.0

ms

SKIP CYCLE GENERATION

Default skip mode level on FB pin

TEMPERATURE MANAGEMENT

V

skip

4

0.5

V

TSD

Temperature shutdown

Hysteresis in shutdown

150

50

°C

2. See characterization curves for temperature evolution

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4

NCP1015

TYPICAL CHARACTERISTICS

1.5

1.4

−2

−3

−4

−5

1.3

1.2

1.1

1.0

0.9

0.8

0.7

−6

−7

−8

−9

−10

−11

−12

0.6

0.5

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 3. IC1 @ V_CC= 8.0 V, FB = 1.5 V

vs. Temperature

Figure 4. ICC1 @ V_CC= 8.0 V, FB = 1.5 V

vs. Temperature

9.0

8.9

8.8

8.7

0.40

0.38

0.36

0.34

0.32

0.30

0.28

0.26

0.24

8.6

8.5

8.4

8.3

8.2

0.22

0.20

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 5. ICC2 @ V_CC= 6.0 V, FB = Open

vs. Temperature

Figure 6. V_CCOFF, FB = 1.5 V vs. Temperature

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5

NCP1015

TYPICAL CHARACTERISTICS

69

8.0

7.9

7.8

7.7

7.6

7.5

7.4

7.3

7.2

68

67

66

7.1

7.0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 7. V_CCON, FB = 3.5 V vs. Temperature

Figure 8. Duty Cycle vs. Temperature

600

550

500

450

400

350

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 9. Ipeak−RR, V_CC= 8.0 V, FB = 3.5 V

vs. Temperature

25

20

110

100 kHz

100

90

15

10

5

80

70

65 kHz

40

60

50

0

−40 −20

0

20

60

80

100 120

−40 −20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 10. Frequency vs. Temperature

Figure 11. ON Resistance vs. Temperature

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6

NCP1015

APPLICATION INFORMATION

Introduction

The NCP1015 offers a complete current−mode control

solution (actually an enhanced NCP1200 controller section)

together with a high−voltage power MOSFET in a

monolithic structure. The component integrates everything

needed to build a rugged and low−cost Switch−Mode Power

Supply (SMPS) featuring low standby power. The quick

selection table details the differences in operating

frequency.

• No need for an auxiliary winding: ON Semiconductor

Very High Voltage Integrated Circuit technology lets

you supply the IC directly from the high−voltage dc

rail. We call it Dynamic Self−Supply (DSS). This

solution simplifies the transformer design and ensures a

better control of the SMPS in difficult output

averaged version to help you closing the loop.

Ready−to−use templates can be downloaded in

OrCAD’s PSpice, and INTUSOFT’s IsSpice4 from ON

Semiconductor web site, NCP1015 related section.

Dynamic Self−Supply

When the power supply is first powered from the mains

outlet, the internal current source (typically 8 mA) is biased

and charges up the V capacitor from the drain pin. Once

CC

the voltage on this V capacitor reaches the V

level

CC

CC(off)

(typically 8.5 V), the current source turns off and pulses are

delivered by the output stage: the circuit is awake and

activates the power MOSFET. Figure 12 details the internal

circuitry:

conditions, e.g. constant current operations. However,

for improved standby performance, an auxiliary

Vref OFF = 8.5 V

Vref ON = 7.5 V

Drain

winding can be connected to the V pin to disable the

Vref

= 4.7 V

CC

Latch

DSS operation.

+

-

• Short−circuit protection: by permanently monitoring

the feedback line activity, the IC is able to detect the

presence short−circuit, immediately reducing the output

power for a total system protection. Once the short has

disappeared, the controller resumes and goes back to

normal operation.

• Low standby−power: If SMPS naturally exhibit a good

efficiency at nominal load, they begin to be less

efficient when the output power demand diminishes. By

skipping un−needed switching cycles, the NCP1015

drastically reduces the power wasted during light load

conditions. An auxiliary winding can further help

decreasing the standby power to extremely low levels

by invalidating the DSS operation. Typical

Startup Source

V

CC

Internal Supply

+

Vref

CV

V

CC

CC(off)

+200 mV

(8.7 V Typ.)

Figure 12. The Current Source Regulates V_CC

by Introducing a Ripple

measurements show results below 80 mW @ 230 Vac

for a typical 7 W universal power supply.

Being loaded by the circuit consumption, the voltage on

the V capacitor goes down. When the DSS controller

CC

• No acoustic noise while operating: Instead of skipping

cycles at high peak currents, the NCP1015 waits until

the peak current demand falls below a fixed 0.25 of the

maximum limit. As a result, cycle skipping can take

place without having a singing transformer. You can

thus select cheap magnetic components free of noise

problems.

detects that V has reached 7.5 V (V

), it activates the

CC

CC(on)

internal current source to bring V toward 8.5 V and stops

CC

again: a cycle takes place whose low frequency depends on

the V capacitor and the IC consumption. A 1 V ripple

CC

takes place on the V pin whose average value equals

CC

(V

+ V

) / 2. Figure 13 shows a typical operation

CC(off)

CC(on)

of the DSS.

• SPICE model: a dedicated model to run transient

cycle−by−cycle simulations is available but also an

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7

NCP1015

8.5V

8.00

6.00

4.00

2.00

7.5V

Vcc

Device

internally

pulses

0

Startup period

Figure 13. The Charge/Discharge Cycle over a 10 mF V_CCCapacitor

As one can see, the V capacitor shall be dimensioned to

offer an adequate startup time, i.e. ensure regulation is

the so−called latch−off level, where the current source

activates again to attempt a new re−start. If the error has

gone, the IC automatically resumes its operation. If the

default is still there, the IC pulses during 8.5 V down to 7.5 V

and enters a new latch−off phase. The resulting burst

operation guarantees a low average power dissipation and

lets the SMPS sustain a permanent short−circuit. Figure 14

presents the corresponding diagram:

CC

reached before V crosses 7.5 V (otherwise the part enters

CC

the fault condition mode). If we know that DV = 1 V and

ICC1 is 1.2 mA (for instance we selected a 11 W device

switching at 65 kHz), then the V

calculated using:

capacitor can be

CC

ICC1 @ t_startup

(eq. 1)

C w

DV

Current Sense

Let’s suppose that the SMPS needs 10 ms to startup, then

we will calculate C to offer a 15 ms period. As a result, C

should be greater than 18 mF thus the selection of a 33 mF /

16 V capacitor is appropriate.

Information

4 V

+

−

FB

To

Latch

Reset

Division

Short Circuit Protection

The internal protection circuitry involves a patented

arrangement that permanently monitors the assertion of an

internal error flag. This error flag is, in fact, a signal that

instructs the controller that the internal maximum peak

current limit is reached. This naturally occurs during the

V

CC

Max

Ip

V

CC(on)

Flag

Clamp

Active?

startup period (V is not stabilized to the target value) or

out

when the optocoupler LED is no longer biased, e.g in a

short−circuit condition or when the feedback network is

broken. When the DSS normally operates, the logic checks

for the presence of the error flag every time V crosses

CC

Figure 14. Simplified NCP1015 Short−Circuit

V . If the error flag is low (peak limit not active) then

CC(on)

Detection Circuitry

the IC works normally. If the error signal is active, then the

NCP1015 immediately stops the output pulses, reduces its

internal current consumption and does not allow the startup

The protection burst duty−cycle can easily be computed

through the various timing events as portrayed by Figure 15:

source to activate: V drops toward ground until it reaches

CC

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8

NCP1015

Tsw

1 V Ripple

Tstart

TLatch

Latch−off

Level

Figure 15. NCP1015 Facing a Fault Condition (V_in= 150 Vdc)

The rising slope from the latch−off level up to 8.5 V is

expressed by:

Figure 16 shows a typical drain−ground wave−shape

where leakage effects have been removed:

P

_DSS+ V_in@ ICC1

Vds(t)

DV1 @ C

IC1

t_start

+

toff

The time during which the IC actually pulses is given by:

Vr

DV2 @ C

Vin

dt

t_sw

+

ICC1

Finally, the latch−off time can be derived using the same

formula topology:

DV3 @ C

ICC2

t_latch

+

ton

t

From these three definitions, the burst duty−cycle D can

Tsw

be computed:

Figure 16. A Typical Drain−ground Waveshape

where Leakage Effects are Not Accounted for

t_sw

D +

(eq. 2)

(eq. 3)

t_start) t_sw) t_latch

DV2

D +

By looking at Figure 16 the average result can easily be

derived by additive square area calculation:

DV3

DV2

ICC1

DV1

IC1

_{ICC1 @}ǒ

Ǔ

)

ICC2

Feeding the equation with values extracted from the

parameter section gives a typical duty−cycle D of 13%,

precluding any lethal thermal runaway while in a fault

condition.

t_off

t_sw

(eq. 5)

(eq. 6)

(eq. 7)

(eq. 8)

t V_DS(t)u+ V_in@ (1 * D) ) V_r@

By developing Equation 5 we obtain:

t_off

t_sw

t_on

t_sw

t V_DS(t)u+ V_in* V_in

@

) V_r@

DSS Internal Dissipation

The Dynamic Self−Supplied pulls the energy out from the

drain pin. In the Flyback−based converters, this drain level

can easily go above 600 V peak and thus increase the stress

on the DSS startup source. However, the drain voltage

evolves with time and its period is small compared to that of

the DSS. As a result, the averaged dissipation, excluding

capacitive losses, can be derived by:

t

can be expressed by:

off

L_p

V_r

t_off+ I_p@

can be evaluated by:

on

L_p

V_in

t

_on+ I_p@

P

_DSS+ ICC1 @t V_DS(t)u

(eq. 4)

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9

NCP1015

Plugging Equation 7 and Equation 8 into Equation 6 leads

to <V > = V and thus:

V

_nom* V

V

_stby* V_CC(on)

^clampv R_limv

(eq. 10)

ds(t)

in

I_trip

ICC1

P

_DSS+ V_in@ ICC1

(eq. 9)

Where:

The worse case occurs at high line, when V equals

in

V

is the auxiliary voltage at nominal load

nom

370 Vdc. With ICC1 = 1.2 mA (65 kHz version), we can

expect a DSS dissipation around 440 mW. If you select a

higher switching frequency version, the ICC1 increases and

it is likely that the DSS consumption exceeds 500 mW. In

that case, we recommend adding an auxiliary winding in

order to offer more dissipation room to the power MOSFET.

Please read application note AND8125/D “Evaluating the

power capability of the NCP101X members” to help

selecting the right part / configuration for your application.

is the auxiliary voltage when standby is entered

stdby

I

trip

is the current corresponding to the nominal operation.

It thus must be selected to avoid false tripping in overshoot

conditions.

ICC1 is the controller consumption. This number slightly

decreases compared to ICC1 from the spec since the part in

standby does almost not switch.

V

CC(on)

is the level above which V must be maintained

aux

to keep the DSS in the OFF mode. It is good to shoot around

8 V in order to offer an adequate design margin, e.g. to not

re−activate the startup source (which is not a problem in

itself if low standby power does not matter)

Lowering the Standby Power with an Auxiliary

Winding

The DSS operation can bother the designer when a) its

dissipation is too high b) extremely low standby power is a

must. In both cases, one can connect an auxiliary winding to

disable the self−supply. The current source then ensures the

startup sequence only and stays in the off state as long as

Since R

shall not bother the controller in standby, e.g.

limit

keep V to around 8 V (as selected above), we purposely

aux

select a V

well above this value. As explained before,

nom

experience shows that a 40% decrease can be seen on

auxiliary windings from nominal operation down to standby

mode. Let’s select a nominal auxiliary winding of 20 V to

V

does not drop below V

or 7.5 V. Figure 17 shows

CC

CC(on)

that the insertion of a resistor (R

dc level and the V pin is mandatory a) not to damage the

) between the auxiliary

limit

CC

offer sufficient margin regarding 8 V when in standby (R

also drops voltage in standby). Plugging the values in

internal 8.7 V zener diode during an overshoot for instance

(absolute maximum current is 15 mA) b) to implement the

fail−safe optocoupler protection as offered by the active

clamp. Please note that there cannot be bad interaction

between the clamping voltage of the internal zener and

limit

Equation 10 gives the limits within which R

selected:

shall be

limit

20 * 8.7

6.3 m

12 * 8

1.1 m

v R_limitv

(eq. 11)

V

CC(off)

since this clamping voltage is actually built on top

of V

with a fixed amount of offset (200 mV typical).

CC(off)

that is to say: 1.8 kW < R

If we are designing a power supply delivering 12 V, then

the ratio auxiliary/power must be: 12 / 20 = 0.6. The I

current has to not exceed 6.4 mA. This will occur when V

grows−up to: 8.7 V + 1.8 k x (6.4 m + 1.1 m) = 22.2 V for

the first boundary or 8.7 V + 3.6 k x (6.4 m +1.1 m) = 35.7 V

for second boundary. On the power output, it will

respectively give 22.6 x 0.6 = 13.3 V and 35.7 x 0.6 = 21.4 V.

< 3.6 kW.

limit

Self−supplying controllers in extremely low standby

applications often puzzles the designer. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

an arbitrary 16 V (V ), this voltage can drop to below

10 V (V ) when entering standby. This is because the

recurrence of the switching pulses expands so much that the

low frequency re−fueling rate of the V capacitor is not

enough to keep a proper auxiliary voltage. Figure 18 shows

a typical scope shot of a SMPS entering deep standby

(output un−loaded). So care must be taken when calculating

CC

aux

nom

stby

CC

As one can see, tweaking the R

value will allow the

limit

selection of a given overvoltage output level. Theoretically

predicting the auxiliary drop from nominal to standby is an

almost impossible exercise since many parameters are

involved, including the converter time constants. Fine

R

limit

1) to not excess the maximum pin current in normal

operation but 2) not to drop too much voltage over R

when entering standby. Otherwise the DSS could reactivate

and the standby performance would degrade. We are thus

limit

tuning of R

thus requires a few iterations and

limit

experiments on a breadboard to check V variations but

aux

able to bound R

between two equations:

limit

also output voltage excursion in fault. Once properly

adjusted, the fail−safe protection will preclude any lethal

voltage runaways in case a problem would occur in the

feedback loop.

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10

NCP1015

Drain

V

= 8.5 V

= 7.5 V

CC(off)

CC(on)

-

+

Startup Source

V

CC

Rlimit

D1

+

−

+

CVCC

CAux

Laux

Ground

Figure 17. A Detailed View of the NCP1015 with Properly Connected Auxiliary Winding

u30 ms

Figure 18. The Burst Frequency becomes So Low that it is Difficult to

Keep an Adequate Level on the Auxiliary V_CC

Lowering the Standby Power with Skip−cycle

excited by the skipping pulses. A possible solution,

Skip cycle offers an efficient way to reduce the standby

power by skipping unwanted cycles at light loads. However,

the recurrent frequency in skip often enters the audible range

and a high peak current obviously generates acoustic noise

in the transformer. The noise takes its origins in the

resonance of the transformer mechanical structure which is

successfully implemented in the NCP1200 series, also

authorizes skip cycle but only when the power demand as

dropped below a given level. At this time, the peak current

is reduced and no noise can be heard. Figure 19 shows the

peak current evolution of the NCP1015 entering standby:

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11

NCP1015

100%

Peak current

at nominal power

Skip−cycle

current limit

25%

Figure 19. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation

Full power operation involves the nominal switching

the benefit to artificially reduce the measurement noise on

a standard EMI receiver and pass the tests more easily. The

frequency and thus avoids any noise when running.

Experiments carried on a 5 W universal mains board

unveiled a standby power of 300 mW @ 230 Vac with the

DSS activated and dropped to less than 100 mW when an

auxiliary winding is connected.

EMI sweep is implemented by routing the V

ripple

CC

(induced by the DSS activity) to the internal oscillator. As a

result, the switching frequency moves up and down to the

DSS rhythm. Typical deviation is 4% of the nominal

frequency. With a 1 V peak−to−peak ripple, the frequency

will equal 65 kHz in the middle of the ripple and will

Frequency Jittering for Improved EMI Signature

By sweeping the switching frequency around its nominal

value, it spreads the energy content on adjacent frequencies

rather than keeping it centered in one single ray. This offers

increase as V rises or decrease as V ramps down.

CC

Figure 20 shows the behavior we have adopted:

VCC

OFF

V

CC

Ripple

67.6 kHz

65 kHz

62.4 kHz

VCC

Internal Sawtooth

ON

Figure 20. The V_CCRipple Causes the Frequency Jittering on the Internal Oscillator Saw−tooth

(65 kHz version)

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12

NCP1015

Soft−Start

soft−start is also activated during the over current burst

(OCP) sequence. Every re−start attempt is followed by a

soft−start activation. Generally speaking, the soft−start will

The NCP1015 features an internal 1 ms soft−start

activated during the power on sequence (P ). As soon as

ON

V

CC

reaches V

, the peak current is gradually

be activated when V ramps up either from zero (fresh

CC(off)

CC

increased from nearly zero up to the maximum internal

clamping level (e.g. 350 mA). This situation lasts 1 ms and

further to that time period, the peak current limit is blocked

to the maximum until the supply enters regulation. The

power−on sequence) or 4.5 V, the latch−off voltage

occurring during OCP. Figure 21 shows the soft−start

behavior. The time scales are purposely shifted to offer a

better zoom portion.

8.5 V

V

CC

0 V (Fresh PON)

or

4.7 V (Overload)

Current

Sense

Max Ip

1.0 ms

Figure 21. Soft−Start is Activated During a Start−up Sequence or an OCP Condition

Non−latching Shutdown

and ground. By pulling FB below the internal skip level

In some cases, it might be desirable to shut off the part

temporarily and authorize its re−start once the default has

disappeared. This option can easily be accomplished

through a single NPN bipolar transistor wired between FB

(V ), the output pulses are disabled. As soon as FB is

skip

relaxed, the IC resumes its operation. Figure 22 shows the

application example:

1

2

3

4

8

7

5

Transformer

ON/OFF

+

CV

CC

Figure 22. A Non−latching Shutdown where Pulses are Stopped as long as the NPN is Biased

Full Latching Shutdown

Other applications require a full latching shutdown, e.g.

When the OVP level exceeds the zener breakdown voltage,

the NPN biases the PNP and fires the equivalent SCR,

permanently bringing down the FB pin. The switching

pulses are disabled until the user un−plugs the power supply.

when an abnormal situation is detected (over temp or

overvoltage). This feature can easily be implemented

through two external transistors wired as a discrete SCR.

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13

NCP1015

Rhold

12 k

OVP

1

2

3

4

8

7

10 k

BAT54

5

Transformer

+

CV

CC

0.1 mF

10 k

Figure 23. Two Bipolar Transistors Ensures a Total Latch−off of the SMPS in Presence of an OVP

T

_J(max)* T_AMB(max)

R

ensures that the SCR stays on when fired. The bias

hold

P_max

+

(eq. 12)

current flowing through R

the V ramp up (8.5 V) and down (7.5 V) when the SCR

should be small enough to let

hold

R_qJA

CC

which gives around 1 W for an ambient of 50°C. The losses

inherent to the MOSFET R

following formula:

is fired. The NPN base can also receive a signal from a

temperature sensor. Typical bipolar can be MMBT2222 and

MMBT2907 for the discrete latch. The NST3946 features

two bipolar NPN + PNP in the same package and could also

be used.

can be evaluated using the

DS(on)

1

3

P_mos

+

@ I_p²@ D @ R_DS(on)

(eq. 13)

where I is the worse case peak current (at the lowest line

p

Power Dissipation and Heatsinking

The power dissipation of NCP1015 consists of the

dissipation DSS current−source (when active) and the

input), D is the converter operating duty−cycle and R

DS(on)

the MOSFET resistance for T = 100°C. This formula is only

J

valid for Discontinuous Conduction Mode (DCM)

operation where the turn−on losses are null (the primary

current is zero when you re−start the MOSFET). Figure 24

gives a possible layout to help dropping the thermal

resistance. When measured on a 35 mm (1 oz.) copper

thickness PCB, we obtained a thermal resistance of 75°C/W:

dissipation of MOSFET. Thus P = P

+ P

.

tot

DSS

MOSFET

When the PDIP7 package is surrounded by copper, it

becomes possible to drop its thermal resistance

junction−to−ambient, R

down to 75°C/W and thus

qJA

dissipate more power. The maximum power the device can

thus evacuate is:

Clamping Elements

To Secondary Diode

DC

Figure 24. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

Design Procedure

The design of a SMPS around a monolithic device does

1. In any case, the lateral MOSFET body−diode shall

never be forward biased, either during start−up

(because of a large leakage inductance) or in

normal operation as shown by Figure 25.

not differ from that of a standard circuit using a controller

and a MOSFET. However, one needs to be aware of certain

characteristics specific of monolithic devices:

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14

NCP1015

350

250

150

50.0

−50.0

> 0 !!

1.004M

1.011M

1.018M

1.025M

1.032M

Figure 25. The Drain−Source Wave Shall Always be Positive . . .

As a result, the Flyback voltage which is reflected on

the drain at the switch opening cannot be larger than

the input voltage. When selecting components, you

thus must adopt a turn ratio which adheres to the

following equation:

e.g. the V target is almost reached and I is still

out p

pushed to the maximum.

Taking into account all previous remarks, it becomes

possible to calculate the maximum power that can be

transferred at low line:

When the switch closes, V is applied across the primary

in

N @ (V_out) V_f) t V_IN(min)

(eq. 14)

inductance L until the current reaches the level imposed by

p

For instance, if you operate from a 120 V dc rail and

you deliver 12 V, we can select a reflected voltage of

100 VDC maximum: 120 − 100 > 0. Therefore, the

turn ratio Np : Ns must be smaller than 100 / (12 +

1) = 7.7 or Np : Ns < 7.7. We will see later on how

it affects the calculation.

the feedback loop. The duration of this event is called the ON

time and can be defined by:

L_p@ I_p

V_in

t_on

+

(eq. 16)

At the switch opening, the primary energy is transferred

to the secondary and the flyback voltage appears across L ,

2. Current−mode architecture is, by definition,

sensitive to subharmonic oscillations.

p

reseting the transformer core with a slope of:

Subharmonic oscillations only occur when the

SMPS is operating in Continuous Conduction

Mode (CCM) together with a duty−cycle greater

than 50%. As a result, we recommend operating

the device in DCM only, whatever duty−cycle it

implies (max. = 65%).

N @ (V_out) V_f)

@ t_off

L_p

the t time is thus:

off

L_p@ I_p

N @ (V_out) V_f)

t_off

+

(eq. 17)

If one wants to keep DCM only, but still need to pass the

maximum power, we will not allow a dead−time after the

core is reset, but rather immediately re−start. The switching

3. Lateral Mosfets have a poorly doped body−diode

which naturally limits their ability to sustain the

avalanche. A traditional RCD clamping network

shall thus be installed to protect the MOSFET. In

some low power applications, a simple capacitor

can also be used since:

time t can be expressed by:

sw

1

ǒ

Ǔ

t

_sw+ t_off) t_on+ L_p@ I_p@

)

(eq. 18)

V_inN @ (V_out) V_f)

L_f

C_tot

The Flyback transfer formula dictates that:

V

_DRAIN(max)+ V_in) N @ (V_out) V_f) ) I_p@

Ǹ

(eq. 15)

P_out

1

+

@ L_p@ I_p²@ f_sw

(eq. 19)

where L is the leakage inductance, C the total

h

f

tot

2

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

which, by extracting I and plugging into Equation 19 leads to:

p

source), N the Np : Ns turn ratio, V the output

2 @ P_out

h @ f_sw@ L_p

out

1

_@ǒ

Ǔ _{(eq. 20)}

t_sw+ L

)

_pǸ

voltage, V the secondary diode forward drop and

V_inN @ (V_out) V_f)

f

finally, I the maximum peak current. Worse case

p

Extracting L from Equation 20 gives:

occurs when the SMPS is very close to regulation,

p

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15

NCP1015

(V_in@ V_r)²@ h

2 @ f_sw@ [P_out@ (V_r²) 2 @ V_r@ V_in) V_in²)]

L_Pcritical

+

(eq. 21)

with V = N . (V + V ) and h the efficiency.

where V corresponds to the lowest bulk voltage,

IN(min)

r

out

f

If L critical gives the inductance value above which

hence the longest ton duration or largest duty−cycle. I

p

P(max)

DCM operation is lost, there is another expression we can

is the available peak current from the considered part, e.g.

450 mA typical for the NCP1015 (however, the minimum

value of this parameter shall be considered for reliable

evaluation). Combining Equations 21 and 22 gives the

maximum theoretical power you can pass respecting the

peak current capability of the NCP1015, the maximum

duty−cycle and the discontinuous mode operation:

write to connect L , the primary peak current bounded by the

p

NCP1015 and the maximum duty−cycle that needs to stay

below 50%:

D

_max@ V_IN(min)@ t_sw

L_P(max)

+

(eq. 22)

I_P(max)

f_sw

P

_max+ t_sw²@ V_IN(min)²@ V_r²@ h @

(eq. 23)

2

(2L_P(max)V_r²) 4L_P(max)V_rV_IN(min)) V_IN(min)

)

From Equation 22 we obtain the operating duty−cycle D:

I_p@ L_p

D +

(eq. 24)

V_in@ t_sw

This lets us calculate the RMS current circulating in the

MOSFET:

Applying the above equations leads to :

Selected maximum reflected voltage = 120 V

D

with V = 12 V, secondary drop = 0.5 V ³ Np : Ns = 1 : 0.1

out

Ǹ

I_D(rms)+ I_p@

(eq. 25)

3

L critical = 3.9 mH

p

From this equation, we obtain the average dissipation in

the MOSFET:

I = 250 mA

p

D

max

= 0.39

1

P_avg

+

@ I_p²@ D @ R_DS(on)

(eq. 26)

I

= 90 mA

DRAIN(rms)

3

P

= 202 mW at R

= 25 W (T > 100°C)

MOSFET

DS(on) J

to which switching losses shall be added.

If we stick to Equation 23, compute Lp and follow the

above calculations, we will discover that a power supply

built with the NCP1015 and operating from a 100 Vac line

minimum will not be able to deliver more than 7 W

continuous, regardless of the selected switching frequency

= 1.2 mA x 350 V = 420 mW, if DSS is used

DSS

Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V

(e.g. a MBRS360T3, 3 A / 60 V would fit)

Example 2.: A 12 V 16 W SMPS Operating on Narrow

European Mains with NCP1015:

(however the transformer core size will go down as f is

sw

increased). This number grows up significantly when

operated from single European mains (18 W).

For more different flyback converters then are the below

examples we recommend use following support:

1) Application note AND8125/D “Evaluating the power

capability of the NCP101X members”

2) Application note AND8134/D “Designing Converters

with the NCP101X members.”

3) Application note AND8142/D “A 6W/12W Universal

mains adapter with NCP101X series”.

V = 230 Vac 15%, or 276 Vdc ÷ 370 Vdc

Efficiency = 80%

in

V

out

= 12 V, I = 1.25 A

out

f

I

= 65 kHz

sw

= 450 mA − 10% = 405 mA

P(max)

Applying the equations leads to :

Selected maximum reflected voltage = 250 V

with V = 12 V, secondary drop = 0.5 V ³ Np : Ns = 1:0.05

out

L = 7,2 mH

p

4) The PSpice or Orcad simulation models

I = 0.27 mA

p

Example 1.: A 12 V 7.0 W SMPS Operating on a Large

Mains with NCP1015:

D

max

= 0.41

I

= 100 mA

DRAIN(rms)

V

= 100 Vac ÷ 250 Vac or 140 Vdc ÷ 350 Vdc once

in

rectified, assuming a low bulk ripple

P

= 250 mW at R

= 25 W (T > 100°C)

MOSFET

DS(on) J

Efficiency = 80%

= 1.2 mA x 370 V = 444 mW, if DSS is used below an

DSS

ambient of 50°C.

V

out

= 12 V, I = 580 mA

out

Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V

(e.g. a MBRS340T3, 3 A / 40 V)

f

I

= 65 kHz

sw

= 450 mA − 10% = 405 mA

P(max)

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16

NCP1015

MOSFET Protection

Please note that these calculations assume a flat DC rail

whereas a 10 ms ripple naturally affects the final voltage

available on the transformer end. Once the Bulk capacitor

has been selected, one should check that the resulting ripple

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

which is 700 V. Figures 26A, B, and C present possible

implementations:

(min V ?) is still compatible with the above calculations.

bulk

As an example, to benefit from the largest operating range,

a 7 W board was built with a 47 mF bulk capacitor which

ensured discontinuous operation even in the ripple

minimum waves.

HV

Rclamp

Cclamp

D

Dz

D

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CVc

c

CVcc

C

NCP1015

C

B

A

Figure 26. Different Options to Clamp the Leakage Spike

Figure 26A: The simple capacitor limits the voltage

according to Equation 15. This option is only valid for low

power applications, e.g. below 5 W, otherwise chances exist

to destroy the MOSFET. After evaluating the leakage

inductance, you can compute C with Equation 15. Typical

values are between 100 pF and up to 470 pF. Large

capacitors increase capacitive losses.

current. Worse case occurs when I and V are maximum

p in

and V is close to reach the steady−state value.

out

Figure 26C: This option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 volts above

the reflected output voltage when the supply is heavily

loaded.

Figure 26B: The most standard circuitry called the RCD

network. You calculate R

following formulas:

and C

using the

clamp

2 @ V_clamp@ (V_clamp* (V_out) V_fsec) @ N)

L_leak@ I_p²@ f_sw

R_clamp

+

(eq. 27)

V_clamp

C_clamp

+

(eq. 28)

V_ripple@ f_sw@ R_clamp

V

clamp

is usually selected 50−80 V above the reflected

value N x (V + V ). The diode needs to be a fast one and

out

f

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

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17

NCP1015

Typical Application Examples

A 6.5 W NCP1015−based Flyback converter. (For

evaluation a universal NCP1012 demo−board can be used)

Figure 27 shows a converter originally built with a

NCP1012 which can be easily used for evaluation of

NCP1015 device delivering 6.5 W from a universal volts

input range. The board uses the Dynamic Self−Supply and

a simplified zener−type feedback. This configuration was

selected for cost reasons and a more precise circuitry can be

used, e.g. based on a TL431:

D6

B150

TR1

1

4

8

7

D1

1N4007

D2

1N4007

E3

470 m/25 V

C1

2n2/Y

R2

150 k

D5

U160

2

1

6

5

E1

R1

47 R

10 m/400 V

IC1

NCP1012

ZD1

11 V

J2

CZM5/2

1

5

4

8

IC2

PC817

1

2

V

CC

DRAIN

FB

R3

100 R

2

3

7

GND

E2

10 m/63 V

J1

CEE7.5/2

R4

180 R

D3

1N4007

D4

1N4007

GND GND

C2

2n2/Y

Figure 27. A NCP1012−based Flyback Converter Delivering 6.5 W

The converter built according to Figure 28 layouts, gave

the following results:

• Efficiency at V = 100 Vac and P = 6.5 W = 75.7%

in

out

• Efficiency at V = 230 Vac and P = 6.5 W = 76.5%

in

out

Figure 28. The NCP1012−based PCB Layout and its Associated Component Placement

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18

NCP1015

A 7.0 W NCP1015−based Flyback Converter Featuring Low Standby Power

Figure 29 shows another typical application showing a

NCP1015−65 kHz operating in a 7 W converter up to 70°C

of ambient temperature. We can grow−up the output power

since an auxiliary winding is used, the DSS is disabled, and

thus offering more room for the MOSFET. In this

application, the feedback is made via a TLV431 whose low

bias current (100 mA min) helps to lower the no−load

standby power.

Vbulk

1N4148

D4

R4 22

C8

L2

22 mH

D2

R7

100 k/

1 W

MBRS360T3

10 nF

12 V @

0.5 A

400 V

T1

+

C10

33 mF/25 V

100 mF/16 V

+

Aux

C7

GND

C6 C8

470 mF/16 V

T1

D3

MUR160

R2

3.3 k

R3

1 k

NCP1015

C2

47 mF/

450 V

+

R5

39 k

1

8

V

CC

GND

2 NC

3 NC

4 FB

NC 7

DRAIN

5

+

100 mF/10 V

C3

C4

C9

1 nF

IC1

SFH6156−2

100 nF

IC2

TLV431

R6

4.3 k

C5

2.2 nF

Y1 Type

Figure 29. A Typical Converter Delivering 5 W from a Universal Mains

Measurements have been taken from a demonstration

board implementing Figure 12 12’s sketch and the following

results were achieved, with either the auxiliary winding in

place or through the Dynamic Self−Supply:

For a quick evaluation of Figure 29 application example,

the following transformers are available from Coilcraft:

A9619−C, L = 3 mH, Np : Ns = 1: 0.1, 7 W application on

p

universal mains, including auxiliary winding, NCP1015−

V = 230 Vac, auxiliary winding, P = 0, P = 60 mW

65 kHz

in

out

in

V = 100 Vac, auxiliary winding, P = 0, P = 42 mW

A0032−A, L = 6 mH, Np : Ns = 1: 0.055, 10 W application

in

out

in

p

on European mains, DSS operation only, NCP1015−65 kHz

V

= 230 Vac, Dynamic Self−Supply, P

= 0, P

=

in

out

in

300 mW

Coilcraft

1102 Silver Lake Road

CARY, IL 60013

Email: info@coilcraft.com

Tel. : 847−639−6400

Fax.: 847−639−1469

V

= 100 Vac, Dynamic Self−Supply, P

= 0, P

in

out

in

130 mW

P

out

P

out

= 7 W, h = 81% @ 230 Vac, with aux winding

= 7 W, h = 81.3% @ 100 Vac, with aux winding

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19

NCP1015

ORDERING INFORMATION

Frequency

(kHz)

R

DSon

(W)

†

Device Order Number

Package Type

Shipping

Ipk (mA)

NCP1015AP065G

65

100

65

PDIP−7

11

450

(Pb−Free)

50 Units / Rail

NCP1015AP100G

NCP1015ST65T3G

NCP1015ST100T3G

PDIP−7

(Pb−Free)

450

SOT−223

(Pb−Free)

4000 / Tape & Reel

100

SOT−223

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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20

NCP1015

PACKAGE DIMENSIONS

PDIP−7

AP SUFFIX

CASE 626A−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).

8

5

4. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

5. DIMENSIONS A AND B ARE DATUMS.

B

L

M

1

4

MILLIMETERS

INCHES

MIN

J

DIM MIN

MAX

10.16

6.60

4.45

0.51

1.78

MAX

0.400

0.260

0.175

0.020

0.070

A

B

C

D

F

9.40

6.10

3.94

0.38

1.02

0.370

0.240

0.155

0.015

0.040

F

NOTE 3

A

G

H

J

2.54 BSC

0.100 BSC

0.76

0.20

2.92

1.27

0.30

3.43

0.030

0.008

0.115

0.050

0.012

0.135

K

L

C

7.62 BSC

0.300 BSC

M

N

---

0.76

10

_

1.01

---

0.030

10

_

0.040

−T−

N

SEATING

PLANE

D

K

G

H

M

B

0.13 (0.005)

T A

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21

NCP1015

PACKAGE DIMENSIONS

SOT−223

ST SUFFIX

CASE 318E−04

ISSUE L

NOTES:

D

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

b1

MILLIMETERS

INCHES

NOM

0.064

0.002

0.030

0.121

0.012

0.256

0.138

0.091

0.037

0.069

0.276

−

4

2

DIM

A

A1

b

b1

c

D

E

e

e1

L1

MIN

1.50

0.02

0.60

2.90

0.24

6.30

3.30

2.20

0.85

1.50

6.70

0°

NOM

1.63

0.06

0.75

3.06

0.29

6.50

3.50

2.30

0.94

1.75

7.00

−

MAX

1.75

0.10

0.89

3.20

0.35

6.70

3.70

2.40

1.05

2.00

7.30

10°

MIN

0.060

0.001

0.024

0.115

0.009

0.249

0.130

0.087

0.033

0.060

0.264

0°

MAX

0.068

0.004

0.035

0.126

0.014

0.263

0.145

0.094

0.041

0.078

0.287

10°

H

E

1

3

b

e1

e

H

E

C

q

A

0.08 (0003)

A1

L1

SOLDERING FOOTPRINT*

3.8

0.15

2.0

0.079

6.3

0.248

2.3

0.091

2.3

0.091

2.0

0.079

mm

inches

ǒ

Ǔ

1.5

0.059

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1015/D

http://onsemi.com

22

型号:	NCP1015ST100T3G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
生命周期：	Active
IHS 制造商：	ON SEMICONDUCTOR
零件包装代码：	SOT-223
包装说明：	SOP, SOT-223
针数：	4
制造商包装代码：	0.0318
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.5
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
标称输入电压：	8 V
JESD-30 代码：	R-PDSO-G4
JESD-609代码：	e3
长度：	6.5 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	4
最大输出电流：	1 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOT-223
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	SINGLE
最大切换频率：	110 kHz
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	2.3 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.5 mm
Base Number Matches：	1

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