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  • 北京元坤伟业科技有限公司

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  • 深圳市恒嘉威智能科技有限公司

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产品型号NCP81103MNTXG的概述

芯片NCP81103MNTXG的概述 NCP81103MNTXG是一款低功耗、高效率的电压调节器,主要用于为各种电子设备提供稳定的功率支持。该芯片广泛应用于包括消费电子、计算设备、通信设备等多个领域,是现代电源管理系统中不可或缺的组件。NCP81103MNTXG设计精密,能够在极小的空间内提供高效的电源管理方案。 芯片NCP81103MNTXG的详细参数 NCP81103MNTXG提供了一系列强大的参数,使其在不同的应用场景中表现出色。以下是一些主要参数: - 输入电压范围:4.5V 至 20V - 输出电压范围:可调输出电压范围为 0.8V 至 5V,并具有较小的误差。 - 输出电流:最大输出电流可达 10A。 - 效率:在多种负载条件下,效率高达95%以上。 - 工作温度范围:-40°C 到 125°C,适应恶劣的工作环境。 - 封装类型:MNTXG,具有紧凑的尺寸,方便嵌入到各种...

产品型号NCP81105的Datasheet PDF文件预览

NCP81105, NCP81105H  
DrMOS Supporting, 1/2/3  
Phase Power Controller  
with SVID Interface for  
Desktop and Notebook  
VR12.5 & VR12.6 CPU  
Applications  
http://onsemi.com  
MARKING  
DIAGRAM  
The NCP81105 is a DrMOS supporting controller optimized for  
Intel® VR12.5 & VR12.6 compatible CPUs. The controller combines  
true differential voltage sensing, differential inductor DCR current  
sensing, input voltage feedforward, and adaptive voltage positioning  
to provide accurately regulated power for both Desktop and Notebook  
CPU applications. The control system is based on DualEdge  
pulsewidth modulation (PWM), to provide the fastest initial response  
to dynamic load events plus reduced system cost. The NCP81105 is  
compatible with DrMOS type power stages such as NCP5367,  
NCP5368, NCP5369 and NCP5338.  
The NCP81105’s output can be configured to operate in single phase  
during light load operation improving overall system efficiency. A  
high performance operational error amplifier is provided to simplify  
compensation of the system. Patented Dynamic Reference Injection  
further simplifies loop compensation by eliminating the need to  
compromise between closedloop transient response and Dynamic  
VID performance. Patented Total Current Summing provides highly  
accurate current monitoring for droop and digital current monitoring.  
1
NCP  
81105  
AWLYYWWG  
36  
1
QFN36  
CASE 485CC  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
G
= Year  
= Work Week  
= PbFree Package  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 35 of this data sheet.  
Features  
Meets Intel’s VR12.5 Specifications  
Reduced Enable to First SVID Command Latency  
PhasetoPhase Dynamic Current Balancing  
Switching Frequency Range of 280 kHz to 1.5 MHz  
Implements VR12.6 PS4 State and SVID Reporting  
Mixed Voltage/Current Mode, Dual Edge Modulation  
for Fastest Initial Response to Transient Loading  
High Impedance Differential Voltage Amplifier  
Starts up into PreCharged Loads while Avoiding False  
OVP  
High Performance Operational Error Amplifier  
High Impedance Total Current Sense Amplifier  
True Differential Current Sense Amplifiers for  
Balancing Current in Each Phase  
Digital Soft Start Ramp  
Dynamic Reference Injection  
Accurate Total Summing Current Amplifier  
“Lossless” Inductor DCR Current Sensing  
Summed, Thermally Compensated Inductor Current  
Sensing for Adaptive Voltage Positioning (AVP)  
48 mV/ms Fast Output Slew Rate (NCP81105)  
10 mV/ms Fast Output Slew Rate (NCP81105H)  
Programmable Slow Slew Rates as a Fraction of Fast  
Slew Rate  
Compatible with DrMOS Power Stages  
Powersaving Phase Shedding  
Vin Feedforward Ramp Slope Compensation  
Pin Programming for Internal SVID parameters  
Output Over Voltage Protection (OVP) & Under  
Voltage Protection (UVP)  
Over Current Protection (OCP)  
Power Good Output with Internal Delays  
This is a PbFree Device  
Applications  
Desktop and Notebook Microprocessors  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
October, 2013 Rev. 2  
NCP81105/D  
NCP81105, NCP81105H  
1.3V  
CSREF  
1
2
EN  
ENABLE  
UVLO & EN  
COMPARATORS  
VCC  
VSP  
VSN  
OVP  
36  
35  
34  
VSP  
VSP  
VSN  
VRMP  
DIFF  
AMP  
OVP  
THERMAL  
MONITOR  
_
3
VRHOT#  
VSN  
DAC  
DAC  
DAC  
CSCOMP  
DIFFOUT  
4
5
6
SDIO  
ALERT#  
SCLK  
SVID  
DAC  
ENABLE  
DRVON  
OCP  
INTERFACE  
& LOGIC  
FEED  
FORWARD  
SCALING  
OVP  
_
+
33  
FB  
PS#  
ENABLE  
DATA  
REGISTERS  
ERROR  
AMP  
1.3V  
VR READY  
OVERCURRENT  
COMPARATORS  
8
VR_RDY  
32  
28  
LOGIC  
MUX  
COMP  
IOUT  
CURRENT  
MONITOR  
OCP  
7
ROSC  
TSENSE  
IMAX  
IOUT  
9
Buffer  
OVERCURRENT  
PROGRAMMING  
27  
26  
25  
24  
ILIM  
16  
17  
30  
31  
29  
(VSP VSN)  
CSCOMP  
CSSUM  
CSREF  
ADC  
INT_SEL  
VBOOT  
DGAIN  
VRMP  
ENABLE  
_
+
IOUT  
PS#  
CURRENT  
SENSE  
AMP  
OVP  
OSCILLATOR  
MAX  
OVP  
& RAMP  
VRMP  
GENERATORS  
VRMP  
23  
22  
21  
20  
19  
18  
15  
CSN2  
CSP2  
CSN3  
CSP3  
CSN1  
CSP1  
DRVON  
COMP  
CURRENT  
BALANCE  
PWM  
AMPLIFIERS  
GENERATORS  
I2  
I3  
I1  
DRVON  
PS#  
11  
14  
SMOD  
PWM1  
ZERO  
CURRENT  
OVP  
DETECTION  
OCP  
DRVON  
13  
12  
10  
PWM3  
PWM2  
OD#  
PS#  
POWER  
STATE  
GATE  
NCP81105  
Figure 1. Block Diagram  
http://onsemi.com  
2
NCP81105, NCP81105H  
EN  
VCC  
1
2
3
4
5
6
7
8
9
27  
26  
25  
24  
23  
22  
21  
20  
19  
ILIM  
CSCOMP  
CSSUM  
CSREF  
CSN2  
VRHOT#  
SDIO  
NCP81105  
ALERT#  
SCLK  
TAB: GROUND  
CSP2  
ROSC  
CSN3  
VR_RDY  
TSENSE  
CSP3  
CSN1  
Figure 2. Pin Connections  
(Top View)  
http://onsemi.com  
3
NCP81105, NCP81105H  
PIN LIST AND DESCRIPTION  
Pin  
No.  
Symbol  
Description  
Logic input. Logic high enables the NCP81105 and logic low disables it.  
Power for the internal control circuits. A decoupling capacitor must be connected from this pin to ground.  
Open drain (logic level) output for overtemperature reporting. Low indicates high temp.  
Bidirectional Serial VID data interface.  
1
2
3
4
5
6
7
EN  
VCC  
VR_HOT#  
SDIO  
ALERT#  
SCLK  
Open drain Serial VID ALERT# output.  
Serial VID clock input.  
ROSC  
This pin outputs a constant current. A resistance from this pin to ground programs the switching fre-  
quency.  
8
9
VR_RDY  
TSENSE  
OD#  
Open drain output. High indicates that the NCP81105 is regulating the output.  
Temperature sense input.  
10  
Phase Disabling Output, tied to the Enable, SMOD or ZCD_EN# pin of phases 2 and 3 DrMOS. Except  
in PS0 mode, this output pulls low to disable the DrMOS if connected to an enable input. If connected to  
a DrMOS SMOD or ZCD_EN# input, both HS & LS FETs are held off since PWM2 & PWM3 are also low.  
Actively pulls high in PS0 mode.  
11  
SMOD  
Phase 1 Zero Cross Detection (ZCD) disable output. In PS2 & PS3, SMOD pulls LOW when phase 1  
inductor current is negative to perform (or allow the DrMOS ZCD function to perform) diode emulation,  
and pulls HIGH when phase 1 inductor current is positive. In PS0 & PS1, SMOD stays high to force the  
phase 1 DrMOS into Continuous Conduction.  
12  
13  
14  
15  
16  
17  
PWM2  
PWM3  
PWM1  
DRVON  
IMAX  
PWM output to Phase 2 DrMOS  
PWM output to Phase 3 DrMOS  
PWM output to Phase 1 DrMOS  
Enable output for DrMOS  
During startup, a resistor from this pin to ground programs ICC_MAX.  
INT_SEL  
During startup, a resistor from this pin to ground programs the low frequency compensator pole of the  
NCP81105 voltage control feedback loop.  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
CSP1  
CSN1  
Positive input to phase 1 current sense amplifier for balancing phase currents  
Negative input to phase 1 current sense amplifier  
CSP3  
Positive input to phase 3 current sense amplifier for balancing phase currents  
Negative input to phase 3 current sense amplifier  
CSN3  
CSP2  
Positive input to phase 2 current sense amplifier for balancing phase currents  
Negative input to phase 2 current balance sense amplifier  
CSN2  
CSREF  
CSSUM  
CSCOMP  
ILIM  
Noninverting input for the total output current sense amplifier. Also, the absolute OVP input.  
Inverting input of total output current sense amplifier.  
Output of total output current sense amplifier.  
Input to program the overcurrent shutdown threshold.  
IOUT  
Total current monitor output. A resistor from this pin to ground calibrates SVID output current reporting.  
VRMP  
VDC applied to this pin provides feedforward compensation for the pulsewidth modulator. The current  
into this pin controls the slope of PWM ramp. A low voltage on this pin will inhibit NCP81105 startup.  
30  
31  
VBOOT  
DGAIN  
During startup, a resistor from this pin to ground programs the BOOT voltage  
During startup, a resistor from this pin to ground programs the scaling of the output Droop with respect to  
the total output current signal produced between CSCOMP and CSREF.  
32  
33  
34  
35  
36  
37  
COMP  
FB  
Output of the error amplifier.  
Error amplifier voltage feedback input.  
DIFFOUT  
VSN  
Output of the differential remote sense amplifier.  
Inverting input to the differential remote sense amplifier (VSS sense).  
Noninverting input to the differential remote sense amplifier (VCC sense).  
Power supply return (QFN Flag)  
VSP  
GND  
http://onsemi.com  
4
NCP81105, NCP81105H  
VCIN  
VIN  
BOOT  
DRVON  
PWM1  
SMOD  
EN  
CB1  
DRMOS  
PWM  
PHASE  
VSWH  
SMOD  
NCP81105  
VCIN  
EN  
VIN  
BOOT  
CB2  
DRMOS  
PWM  
PWM2  
OD#  
PHASE  
VSWH  
SMOD  
VCIN  
EN  
VIN  
BOOT  
CB3  
DRMOS  
PWM  
PWM3  
PHASE  
VSWH  
SMOD  
COUT  
Figure 3. Three Phase Application Diagram  
http://onsemi.com  
5
NCP81105, NCP81105H  
R162  
130  
R155  
130  
R157  
75.0  
R156  
54.9  
37  
EPAD  
VSP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
36  
35  
34  
33  
32  
31  
30  
29  
28  
OD#  
SMOD  
PWM2  
PWM3  
PWM1  
DRVON  
IMAX  
VSN  
DIFFOUT  
FB  
COMP  
DGAIN  
VBOOT  
VRMP  
IOUT  
INT_SEL  
CSP1  
Figure 4. Three Phase Control Circuit Application  
http://onsemi.com  
6
NCP81105, NCP81105H  
2
1
2
1
6
6
GH  
GL  
GH  
GL  
36  
36  
42  
14  
13  
12  
11  
10  
9
42  
14  
13  
12  
11  
10  
9
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
41  
5
41  
5
CGND  
CGND  
CGND  
CGND  
CGND  
CGND  
37  
37  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
8
8
38  
4
38  
4
THWN  
BOOT  
THWN  
BOOT  
2
1
6
GH  
GL  
36  
42  
14  
13  
12  
11  
10  
9
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
41  
5
CGND  
CGND  
CGND  
37  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
8
38  
4
THWN  
BOOT  
Figure 5. Three Phase Power Stage Circuit  
http://onsemi.com  
7
NCP81105, NCP81105H  
R162  
130  
R155  
130  
R157  
75.0  
R156  
54.9  
37  
EPAD  
VSP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
36  
35  
34  
33  
32  
31  
30  
29  
28  
OD#  
SMOD  
PWM2  
PWM3  
PWM1  
DRVON  
IMAX  
VSN  
DIFFOUT  
FB  
COMP  
DGAIN  
VBOOT  
VRMP  
IOUT  
INT_SEL  
CSP1  
Figure 6. Two Phase Control Circuit Application  
http://onsemi.com  
8
NCP81105, NCP81105H  
2
1
2
1
6
6
GH  
GL  
GH  
GL  
36  
36  
42  
14  
13  
12  
11  
10  
9
42  
14  
13  
12  
11  
10  
9
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
41  
5
41  
5
CGND  
CGND  
CGND  
CGND  
CGND  
CGND  
37  
37  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
8
8
38  
4
38  
4
THWN  
BOOT  
THWN  
BOOT  
Figure 7. Two Phase Power Stage Circuit  
http://onsemi.com  
9
NCP81105, NCP81105H  
R162  
130  
R155  
130  
R157  
75.0  
R156  
54.9  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
EPAD  
VSP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
OD#  
SMOD  
PWM2  
PWM3  
PWM1  
DRVON  
IMAX  
VSN  
DIFFOUT  
FB  
COMP  
DGAIN  
VBOOT  
VRMP  
IOUT  
INT_SEL  
CSP1  
Figure 8. Single Phase Control Circuit Application  
http://onsemi.com  
10  
NCP81105, NCP81105H  
2
1
6
GH  
GL  
36  
42  
14  
13  
12  
11  
10  
9
VIN  
41  
5
37  
CGND  
CGND  
CGND  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
PGND  
8
38  
4
THWN  
BOOT  
Figure 9. Single Phase Power Stage Circuit  
http://onsemi.com  
11  
NCP81105, NCP81105H  
ABSOLUTE MAXIMUM RATINGS  
ELECTRICAL INFORMATION all signals referenced to GND unless noted otherwise.  
Pin Symbol  
V
MAX  
V
MIN  
I
I
SINK  
SOURCE  
COMP, CSCOMP, DIFFOUT  
VCC + 0.3 V  
GND + 300 mV  
VCC + 0.3 V  
6.5 V  
0.3 V  
GND 300 mV  
0.3 V  
3 mA  
3 mA  
VSN  
VR_RDY  
N/A  
N/A  
5 mA  
N/A  
VCC  
0.3 V  
VRMP  
+25 V  
0.3 V  
VR_HOT#, SDIO & ALERT#  
VCC + 0.3 V  
VCC + 0.3 V  
0.3 V  
0 mA  
5 mA  
30 mA  
5 mA  
OD#, SMOD, PWM1, PWM2,  
PWM3 & DRVON  
0.3 V  
All Other Pins  
VCC + 0.3 V  
0.3 V  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
THERMAL INFORMATION  
Description  
Symbol  
Typ  
Unit  
Thermal Characteristic  
QFN36 Package (Notes 1 and 2)  
R
_C/W  
q
JA  
68  
Operating Junction Temperature Range*  
Operating Ambient Temperature Range  
Maximum Storage Temperature Range  
Moisture Sensitivity Level  
T
10 to 125  
10 to 100  
40 to +150  
1
_C  
_C  
_C  
J
T
STG  
MSL  
*The maximum package power dissipation must be observed.  
1. JESD 515 (1S2P DirectAttach Method) with 0 LFM  
2. JESD 517 (1S2P DirectAttach Method) with 0 LFM  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
VCC INPUT  
Supply Voltage Range  
4.75  
5.25  
29  
V
mA  
mA  
mA  
V
EN = high; PS0, 1, 2 modes  
EN = high; PS3 Mode  
EN = low  
23  
14  
Quiescent Current  
17.5  
30  
VCC rising  
4.5  
UVLO Threshold  
VCC falling  
4.0  
V
UVLO Hysteresis  
VRMP (VIN monitor)  
UVLO Threshold  
160  
mV  
VRMP falling  
3.0  
3.2  
3.4  
V
UVLO Hysteresis  
600  
800  
mV  
mA  
nA  
nA  
Leakage current  
PS0, PS1, PS2, PS3; V  
= 3.2 V  
70  
VRMP  
Leakage current  
PS4, V  
= 20 V  
500  
500  
VRMP  
Leakage current  
V
EN  
= 0 V, V  
= 20 V  
VRMP  
ENABLE INPUT  
Enable High Input Leakage Current  
External 1k pullup to 3.3 V  
1.0  
mA  
http://onsemi.com  
12  
 
NCP81105, NCP81105H  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
ENABLE INPUT  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Upper Threshold  
Lower Threshold  
Total Hysteresis  
V
0.8  
V
V
UPPER  
V
0.3  
LOWER  
V
V  
300  
mV  
UPPER  
LOWER  
Time from Enable transitioning HI to when  
DRVON goes high.  
Enable Delay Time  
2.4  
ms  
SCLK, SDIO, ALERT#  
SCLK Input Low Voltage  
VILSCLK  
VIHSCLK  
VILSDIO  
VIHSDIO  
VHYS  
0.45  
0.42  
V
V
SCLK Input High Voltage  
SDIO Input Low Voltage  
0.66  
0.72  
V
SDIO Input High Voltage  
V
Hysteresis Voltage (SCLK, SDIO)  
Output High Voltage (SDIO, ALERT#)  
Output Low Voltage (SDIO, ALERT#)  
Buffer On Resistance (SDIO, ALERT#)  
Leakage Current  
100  
1.05  
100  
5
mV  
V
VOH  
External resistive pullup to 1.05 V  
Sinking 20 mA  
VOL  
mV  
W
RON  
Measured sinking 4 mA  
13  
100  
4.0  
Pin voltage between 0 and 1.05 V  
100  
mA  
pF  
Pin Capacitance  
Time between SCLK rising edge and valid  
SDIO level  
VR clock to data delay  
Setup time  
T
4
7
8.3  
ns  
ns  
ns  
CO  
Time before SCLK falling (sampling) edge  
that SDIO level must be valid  
TSU  
Time after SCLK falling edge that the  
SDIO level remains valid  
Hold time  
THLD  
14  
VR12.5 & VR12.6 DAC  
1.5 V DAC < 2.3 V, 10°C T 85°C  
0.5  
8  
0.5  
8
%
A
System Voltage Accuracy  
1.0 V DAC < 1.49 V, 10°C T 85°C  
mV  
mV  
A
0.5 V DAC < 0.99 V, 10°C T 85°C  
10  
10  
A
DAC SLEW RATES (NCP81105)  
Soft Start Slew Rate  
SVID Register 2Ah = default  
12  
3 24  
48  
mV/ms  
mV/ms  
mV/ms  
Slew Rate Slow  
Selectable Fraction of Fast Slew  
Slew Rate Fast  
DAC SLEW RATES (NCP81105H)  
Soft Start Slew Rate  
SVID Register 2Ah = default  
2.5  
1 5  
10  
mV/ms  
mV/ms  
mV/ms  
Slew Rate Slow  
Selectable Fraction of Fast Slew  
Slew Rate Fast  
DIFFERENTIAL SUMMING AMPLIFIER  
VSP Input Leakage Current  
VSN Bias Current  
V
= 1.3 V  
0
15  
1
mA  
mA  
pC  
VSP  
0.3 V V  
0.3 V V  
0.3 V  
1  
VSN  
DVID UP Feedforward Charge  
0.5 V  
6.8  
VSN  
Charge per 5 mV DAC increment  
VSP Input Voltage Range  
VSN Input Voltage Range  
3dB Bandwidth  
0.3  
0.3  
3.0  
0.3  
V
V
C = 20 pF to GND, R = 10 kW to GND  
10  
MHz  
V/V  
L
L
DC gain VSx to DIFFOUT  
VSP VSN = 0.5 V to 2.3 V  
1.0  
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13  
NCP81105, NCP81105H  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
DIFFERENTIAL SUMMING AMPLIFIER  
Maximum Output Voltage  
Minimum Output Voltage  
ERROR AMPLIFIER  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
I
= 2 mA  
3.0  
V
V
SOURCE  
I
= 2 mA  
0.5  
25  
SINK  
Input Bias Current  
V
FB  
= 1.3 V; Internal integrator active  
25  
mA  
CL = 20 pF to GND,  
Open Loop DC Gain  
80  
20  
dB  
RL = 10 kW to GND  
CL = 20 pF to GND,  
RL = 10 kW to GND  
Open Loop Unity Gain Bandwidth  
MHz  
DVin = 100 mV, G = 10 V/V,  
DVout = 1.5 V 2.5 V,  
Load = 20 pF to GND + 10 kW to GND  
Slew Rate  
20  
V/ms  
Maximum Output Voltage  
I
= 2.0 mA  
3.5  
V
V
SOURCE  
Minimum Output Voltage  
I
= 2.0 mA  
1
SINK  
VR_RDY (Power Good) OUTPUT  
Output Low Saturation Voltage  
I
= 4 mA  
0.3  
V
VR_RDY  
1 kW external pullup to 3.3 V,  
= 45 pF  
Rise Time  
Fall Time  
100  
10  
ns  
C
TOT  
1 kW external pullup to 3.3 V,  
= 45 pF  
ns  
C
TOT  
Output Voltage at Powerup  
Output Leakage Current When High  
VR_RDY Delay (rising)  
VR_RDY pulled up to 5 V via 2 kW  
VR_RDY = 5.0 V  
1.0  
1.0  
6
V
1.0  
mA  
ms  
ms  
DAC = TARGET to VR_RDY high  
From OCP or OVP to VR_RDY low  
5.5  
5
VR_RDY Delay (falling)  
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)  
Absolute Over Voltage Threshold  
During SoftStart  
2.8  
2.9  
3.0  
V
Over Voltage Threshold Above DAC  
Over Voltage Delay  
VSP rising  
VSP rising to PWMx low  
VSP falling  
350  
400  
50  
425  
mV  
ns  
Under Voltage Threshold Below DAC  
Undervoltage Delay  
300  
5
mV  
ms  
CURRENT BALANCE AMPLIFIERS  
Input Bias Current (after phase  
detection)  
CSPx = CSNx = 1.7 V  
50  
50  
nA  
Common Mode Input Voltage Range  
Differential Mode Input Voltage Range  
CSPx = CSNx  
CSNx = 1.7 V  
0
2.3  
V
100  
100  
mV  
Closed loop Input Offset Voltage  
Matching  
CSPx = CSNx = 1.7 V,  
Measured from the average offset  
1.5  
1.5  
mV  
Amplifier Gain  
0 V < CSPxCSNx 0.1 V  
5.7  
6.0  
8
6.3  
3
V/V  
%
Gain Matching  
10 mV CSPxCSNx 30 mV  
3  
3 dB Bandwidth  
MHz  
1 & 2 PHASE DETECTION  
CSN Pin Resistance to Ground  
CSN Pin Threshold Voltage  
During phase detection only  
50  
kW  
4.5  
V
Time from Enable transitioning HI to  
removal of phase detect resistance  
Phase Detect Timer  
3.5  
ms  
http://onsemi.com  
14  
NCP81105, NCP81105H  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
CURRENT SUMMING AMPLIFIER  
Offset Voltage  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
VOS  
V
= 1.0 V  
300  
7.5  
0
300  
7.5  
mV  
nA  
CSREF  
CSSUM Input Bias Current  
CSREF Input Bias Current  
Open Loop Gain  
CSSUM = CSREF = 1 V  
CSSUM = CSREF = 1 V  
4.25  
mA  
80  
10  
dB  
Current Sense Unity Gain Bandwidth  
Max CSCOMP Output Voltage  
C = 20 pF to GND, R = 10 kW to GND  
MHz  
V
L
L
Isource = 2 mA  
3.5  
Isink = 500 mA  
Isink = 25 mA  
100  
30  
mV  
mV  
Minimum CSCOMP Output Voltage  
7.0  
IOUT OUTPUT  
Maximum Output Voltage  
Input Referred Offset Voltage  
Output Source Current  
R
= 5 kW  
2.0  
1.9  
700  
V
IOUT  
ILIM minus CSREF  
1.9  
mV  
mA  
ILIM sink current = 80 mA  
(IOUT  
) / (ILIM  
IOUT  
);  
CURRENT  
CURRENT  
Current Gain  
AI  
R
= 20 kW; R = 5.0 kW;  
9.5  
10  
10.5  
A/A  
V
IOUT  
ILIM  
V
= 1.7 V  
CSREF  
DIMON Full Scale Voltage  
V
DIFS  
2.0  
OVERCURRENT PROTECTION (ILIM pin)  
3 & 2phase PS0 Threshold Current,  
1phase allPS Threshold Current  
Delayed shutdown  
mA  
I
9.0  
13.5  
10  
15  
11.0  
16.5  
DS  
IS  
Immediate shutdown  
I
3phase, nonPS0 Threshold Current  
Delayed shutdown  
mA  
mA  
ms  
I
PS1, 2 or 3 mode (1phase active)  
PS1, 2 or 3 mode (1phase active)  
4
6
DS  
IS  
Immediate shutdown  
I
2phase, nonPS0 Threshold Current  
Delayed shutdown  
I
PS1, 2 or 3 mode (1phase active)  
PS1, 2 or 3 mode (1phase active)  
6.7  
10  
DS  
Immediate shutdown  
I
IS  
Time for Delayed Shutdown  
OSCILLATOR  
55  
Maximum Switching Frequency  
Minimum Switching Frequency  
Switching Frequency Tolerance  
ROSC Pin Output Current  
MODULATORS (PWM Comparators)  
Minimum Pulse Width  
See Precision Oscillator description  
See Precision Oscillator description  
PS0 mode; RROSC = 110 kW  
1425  
kHz  
kHz  
kHz  
mA  
275  
1125  
10.5  
925  
9.5  
1025  
10  
V
ROSC  
= GND  
20  
ns  
V
COMP voltage when the PWM outputs  
remain Lo (Dualedge modulation only)  
0% Duty Cycle  
1.3  
COMP voltage when the PWM outputs  
remain HI, VRMP = 12.0 V; (Dualedge  
modulation only)  
100% Duty Cycle  
PWM Phase Angle Error  
2.5  
V
Between adjacent phases, 3phase  
20  
20  
20  
deg  
V
operation  
Ramp Feedforward Voltage range  
VRMP pin voltage  
5
PWM OUTPUTS (PWM1/2/3)  
V
CC  
0.2  
Output High Voltage  
Output Low Voltage  
Sourcing 500 mA  
Sinking 500 mA  
V
V
0.7  
http://onsemi.com  
15  
NCP81105, NCP81105H  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
PWM OUTPUTS (PWM1/2/3)  
CL (PCB) = 50 pF, measured between  
Rise and Fall Times  
10  
ns  
10% & 90% of V  
CC  
DRVON OUTPUT  
Output High Voltage  
Output Low Voltage  
Rise Time  
Sourcing 500 mA  
Sinking 500 mA  
3.0  
V
V
0.1  
CL (PCB) = 20 pF, DVo = 10% to 90%  
CL (PCB) = 20 pF, DVo = 90% to 10%  
Time from DRVON high to first PWM  
EN = Low  
150  
5
ns  
ns  
ms  
kW  
Fall Time  
PWM delay time  
Internal Pull Down Resistance  
OD# OUTPUT  
110  
3.0  
120  
70  
Output High Voltage  
Output Low Voltage  
Sourcing 500 mA  
Sinking 500 mA  
V
V
0.1  
15  
Entering PS0; from fall of the earlier of  
PWM2 or PWM3 to OD# rising  
PS0 Delay  
ns  
Rise/Fall Time  
C (PCB) = 20 pF, DVo = 10% to 90%  
10  
70  
ns  
L
Internal Pull Down Resistance  
SMOD OUTPUT  
EN = Low  
kW  
Output High Voltage  
Output Low Voltage  
PS2/3 Delay  
Sourcing 500 mA  
Sinking 500 mA  
3.0  
10  
V
V
0.1  
50  
PS2&3; PWM1 rising to SMOD rising  
ns  
ns  
kW  
Rise/Fall Time  
C (PCB) = 20 pF, DVo = 10% to 90%  
10  
70  
L
Internal Pull Down Resistance  
VR_HOT# OUTPUT  
Output Low Voltage  
Output Leakage Current  
TSENSE INPUT  
EN = Low  
I
= 4 mA  
0.3  
1.0  
V
_VRHOT#  
High Impedance State, V  
= 3.3 V  
1.0  
mA  
VRHOT#  
Alert# Assert Threshold  
Alert# Deassert Threshold  
VRHOT# Assert Threshold  
VRHOT# Deassert Threshold  
TSENSE Bias Current  
VBOOT PIN  
T = 85°C  
458  
476  
437  
457  
60  
mV  
mV  
mV  
mV  
mA  
A
T = 85°C  
A
T = 85°C  
A
T = 85°C  
A
V
= 0.4 V, T = 85°C  
57.7  
9.5  
62.7  
10.5  
TSENSE  
A
Sensing Current  
VVBOOT = GND  
VIMAX = GND  
10  
mA  
IMAX PIN  
Sensing Current  
I
10  
mA  
IMAX  
IMAX Full Scale Voltage  
INT_SEL PIN  
V
2.0  
V
IMAXFS  
Sensing Current  
VINT_SEL = GND  
VDGAIN = GND  
10  
10  
mA  
mA  
V
DGAIN PIN  
Sensing Current  
ADC  
Input Voltage Range  
0
2
http://onsemi.com  
16  
NCP81105, NCP81105H  
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 2.0 V, C = 0.1 mF unless specified otherwise) Min/Max values are valid  
VCC  
CC  
EN  
for the temperature range 10°C T 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
ADC  
Total Unadjusted Error (TUE)  
Differential Nonlinearity (DNL)  
Power Supply Sensitivity  
Conversion Time  
1  
+1  
1
%
LSB  
%
8bit  
1
10  
ms  
Time to cycle through all inputs  
250  
ms  
http://onsemi.com  
17  
NCP81105, NCP81105H  
VR12.5 & VR12.6 VID TABLE  
Voltage  
(V)  
Voltage  
(V)  
VID7  
VID6  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
HEX  
VID7  
VID6  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
HEX  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF  
0.50  
0.51  
0.52  
0.53  
0.54  
0.55  
0.56  
0.57  
0.58  
0.59  
0.60  
0.61  
0.62  
0.63  
0.64  
0.65  
0.66  
0.67  
0.68  
0.69  
0.70  
0.71  
0.72  
0.73  
0.74  
0.75  
0.76  
0.77  
0.78  
0.79  
0.80  
0.81  
0.82  
0.83  
0.84  
0.85  
0.86  
0.87  
0.88  
0.89  
0.90  
0.91  
0.92  
0.93  
0.94  
0.95  
0.96  
0.97  
0.98  
0.99  
1.00  
1.01  
1.02  
1.03  
1.04  
1.05  
1.06  
1.07  
1.08  
1.09  
1.10  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.11  
1.12  
1.13  
1.14  
1.15  
1.16  
1.17  
1.18  
1.19  
1.20  
1.21  
1.22  
1.23  
1.24  
1.25  
1.26  
1.27  
1.28  
1.29  
1.30  
1.31  
1.32  
1.33  
1.34  
1.35  
1.36  
1.37  
1.38  
1.39  
1.40  
1.41  
1.42  
1.43  
1.44  
1.45  
1.46  
1.47  
1.48  
1.49  
1.50  
1.51  
1.52  
1.53  
1.54  
1.55  
1.56  
1.57  
1.58  
1.59  
1.60  
1.61  
1.62  
1.63  
1.64  
1.65  
1.66  
1.67  
1.68  
1.69  
1.70  
1.71  
1.72  
3E  
3F  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
http://onsemi.com  
18  
NCP81105, NCP81105H  
VR12.5 & VR12.6 VID TABLE  
Voltage  
(V)  
Voltage  
(V)  
VID7  
VID6  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
HEX  
VID7  
VID6  
VID5  
VID4  
VID3  
VID2  
VID1  
VID0  
HEX  
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.73  
1.74  
1.75  
1.76  
1.77  
1.78  
1.79  
1.80  
1.81  
1.82  
1.83  
1.84  
1.85  
1.86  
1.87  
1.88  
1.89  
1.90  
1.91  
1.92  
1.93  
1.94  
1.95  
1.96  
1.97  
1.98  
1.99  
2.00  
2.01  
7C  
7D  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.02  
2.03  
2.04  
2.05  
2.06  
2.07  
2.08  
2.09  
2.10  
2.11  
2.12  
2.13  
2.14  
2.15  
2.16  
2.17  
2.18  
2.19  
2.20  
2.21  
2.22  
2.23  
2.24  
2.25  
2.26  
2.27  
2.28  
2.29  
2.30  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
Setup and Hold times CPU Driving SDIO  
SCLK  
VR  
latch  
SDIO  
tHLD  
tSU  
VR Driving SDIO, Clock to Data Delay  
SCLK  
VR  
send  
SDIO  
TCO_VR = clock to data delay in VR  
TCO_VR  
Figure 10. SVID Timing Diagrams  
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19  
NCP81105, NCP81105H  
STATE TRUTH TABLE  
VR_RDY  
Pin  
Error AMP  
Comp Pin  
State  
OVP & UVP  
DRVON Pin  
SMOD Pin  
OD# Pin  
Method of Reset  
VCC UVLO  
0 < VCC < threshold  
VRMP > threshold  
N/A  
N/A  
N/A  
Low  
N/A  
Resistive pull  
down  
Resistive pull down  
Resistive pull down  
VRMP UVLO  
VCC > threshold  
0 < VRMP < threshold  
N/A  
N/A  
Resistive pull  
down  
Resistive pull down  
Low  
Resistive pull down  
Low  
Disabled  
Low  
Disabled  
Low  
EN < threshold  
VCC > threshold  
VRMP > threshold  
Start up Delay &  
Calibration  
Low  
Low  
Disabled  
Low  
Low  
Low  
EN > threshold  
VCC > threshold  
VRMP > threshold  
Soft Start  
Low  
Operational  
Operational  
Active  
Active  
High  
High  
Low until first PWM1  
pulse  
Low until first PWM2  
or PWM3 pulse  
EN > threshold  
VCC > threshold  
VRMP > threshold  
Normal Operation  
EN > threshold  
VCC > threshold  
VRMP > threshold  
High  
High in PS0 & PS1;  
High or may toggle in  
PS2 & PS3  
High in PS0; Low in  
PS1, PS2, & PS3  
N/A  
Over Voltage  
Low  
Low  
Low  
DAC + 400 mV  
High  
High  
High/ Toggles during  
output rampdown  
High/ Toggles during  
output rampdown  
EN low or cycle  
power  
Under Voltage  
Operational  
DACDroop  
300 mV  
High  
High  
Output voltage >  
DACDroop  
300 mV  
Over Current  
Low  
Low  
Operational  
Low  
Last DAC Code  
+ 400 mV  
Low  
Low  
Low  
Low  
Low  
EN low or cycle  
power  
VID Code = 00h  
Disabled  
High (PWM  
outputs low)  
Set Valid VID  
Code  
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20  
NCP81105, NCP81105H  
VCC > UVLO  
Controller  
POR  
Disable  
EN = 0  
EN = 1  
VCC < UVLO  
Calibrate  
Drive Off  
3.5 ms and CAL DONE  
VDRP > ILIM  
NO_CPU  
INVALID VID  
Phase  
Detect  
VCCP > UVLO and DRON HIGH  
Soft Start  
Ramp  
DAC = Vboot  
Soft Start  
Ramp  
OVP  
DAC = VID  
VS > OVP  
Normal  
VR_RDY  
VS > UVP  
VS < UVP  
UVP  
Figure 11. State Diagram  
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21  
NCP81105, NCP81105H  
General  
The NCP81105 is a single output, onetothree phase, dualedge modulated PWM controller with a serial VID control  
interface designed to meet the Intel VR12.5 & VR12.6 specifications. The NCP81105 implements PS0, PS1, PS2, PS3 and  
PS4 power states. It is designed to work in notebook and desktop CPU power supply applications.  
Power Status  
PWM Output Operating Mode  
PS0  
Multiphase, fixed frequency, dual edge modulation (RPM modulation when optioned for single phase), inter-  
leaved PWM outputs (CCM mode)  
PS1  
PS2  
PS3  
PS4  
Singlephase (PWM1) COT (CCM mode; Phases 2 & 3 disabled by OD#)  
Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)  
Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)  
No switching; Memory retained; SVID active  
For 81105, the VID code change rate is controlled with the SVID interface with three options as below:  
Register Address (Contains  
the slew rate of VID code  
change)  
SVID Command  
Code  
DVID Option  
SetVID_Fast  
SetVID_Slow  
SetVID_Decay  
Feature  
48 mV/ms VID code change slew rate  
12 mV/ms VID code change slew rate**  
No control, VID code down  
01h  
02h  
03h  
24h  
25h  
N/A  
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.  
For 81105H, the VID code change rate is controlled with the SVID interface with three options as below:  
Register Address (Contains  
the slew rate of VID code  
change)  
SVID Command  
Code  
DVID Option  
SetVID_Fast  
SetVID_Slow  
SetVID_Decay  
Feature  
10 mV/ms VID code change slew rate  
2.5 mV/ms VID code change slew rate**  
No control, VID code down  
01h  
02h  
03h  
24h  
25h  
N/A  
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.  
Serial VID  
The NCP81105 supports the Intel serial VID (SVID) interface. It communicates with the microprocessor through three wires  
(SCLK, SDIO, ALERT#). The table of supported registers is shown below.  
Index  
Name  
Description  
Access  
Default  
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to  
ON Semiconductor is 0x1Ah  
00h  
Vendor ID  
Product ID  
R
R
R
1Ah  
01h  
Uniquely identifies the VR product. The VR vendor assigns this number.  
15h  
Product  
Revision  
Uniquely identifies the revision or stepping of the VR control IC. The VR  
vendor assigns this data.  
02h  
04h  
Product date  
code ID  
03h  
05h  
R
R
00  
Protocol ID  
Capability  
Identifies the SVID Protocol the NCP81105 supports  
03h  
Informs the Master of the NCP81105’s Capabilities,  
1 for supported, 0 for not supported  
Bit 7: Iout_format; Reg 15 FFh = Icc_Max (=1)  
Bit 6: ADC Measurement of Temp; Supported (= 1)  
Bit 5: ADC Measurement of Pin; Not supported (= 0)  
Bit 4: ADC Measurement of Vin; Supported (= 1)  
Bit 3: ADC Measurement of Iin; Not supported (= 0)  
Bit 2: ADC Measurement of Pout; Supported (= 1)  
Bit 1: ADC Measurement of Vout; Supported (= 1)  
Bit 0: ADC Measurement of Iout; Supported (= 1)  
06h  
10h  
R
R
D7h  
00h  
Data register read after the ALERT# signal is asserted. Conveying the status  
of the VR.  
Status_1  
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22  
NCP81105, NCP81105H  
Index  
Name  
Description  
Access  
Default  
11h  
Status_2  
Data register showing optional status_2 data.  
R
00h  
Data register showing temperature zones the system is operating in  
(thermometer format with 3 degree resolution).  
12h  
15h  
Temp zone  
I_out  
R
R
00h  
01h  
8 bit binary word ADC of current. This register reads 0xFF when the output  
current is at ICC_Max  
8 bit binary word ADC of output voltage, measured between VSP and VSN.  
LSB size is 8 mV  
16h  
17h  
18h  
V_out  
VR_Temp  
P_out  
R
R
R
01h  
01h  
01h  
8 bit binary word ADC of temperature. Binary format in deg C, IE 100C = 64h.  
8 bit binary word representative of output power. The output voltage is  
multiplied by the output current value and the result is stored in this register.  
8 bit binary word ADC of input voltage, measured at VRMP pin. LSB size is  
112 mV  
1Ah  
1Ch  
V_in  
R
R
00h  
00h  
Status 2 Last  
read  
When the status 2 register is read, its contents are copied into this register.  
The format is the same as the Status 2 Register.  
Data register containing the ICC_Max supported by the platform. The value is  
measured at the IMAX pin upon power up and placed in this register. From  
that point on, the register is read only.  
21h  
22h  
24h  
ICC_Max  
Temp_Max  
SR_fast  
R
00h  
64h  
Data register containing the max temperature the platform supports and the  
level VR_hot asserts. This value defaults to 100°C and is programmable over  
the SVID Interface  
R/W  
Slew Rate for SetVID_fast commands. Binary format in mV/ms.  
NCP81105  
NCP81105H  
R
R
32h  
0Ah  
Slew Rate for SetVID_slow commands. A fraction of the SR_fast rate (register  
24h) determined by register 2Ah. Binary format in mV/ms  
25h  
26h  
2Ah  
SR_slow  
Vboot  
NCP81105  
NCP81105H  
R
R
0Ch  
03h  
The Boot voltage is programmed using a resistor on the VBOOT pin which is  
sensed on power up. The NCP81105 will ramp to Vboot and hold at Vboot until  
it receives a new SVID SetVID command to move to a different voltage.  
R
00h  
02h  
0001 = Fast_SR/2  
SR_Slow  
selector  
0010 = Fast_SR/4: default  
0100 = Fast_SR/8  
R/W  
1000 = Fast_SR/16  
Reflects the latency of exiting the PS4 state. The exit latency is defined as the  
time duration, in us, from the ACK of the SETVID Slow/Fast command to the  
beginning of the output voltage ramp.  
PS4 exit  
latency  
2Bh  
2Ch  
R
R
8Ch  
55h  
Reflects the latency of exiting the PS3 state. The exit latency is defined as the  
time duration, in us, from the ACK of the SETVID Slow/Fast command until the  
NCP81105 is capable of supplying max current of the commanded PS state.  
PS3 exit  
latency  
Reflects the latency from Enable assertion to the VR controller being ready to  
Enable to  
ready for SVID  
time  
accept an SVID command. The latency is defined as the time duration, in ms:  
Y
2Dh  
30h  
(x/16)*2 .  
R
CAh  
B5h  
X = bits [3:0]: 4 bit value 0000 to 1111  
Y = bits [7:4]: 4 bit value 0000 to 1111  
Programmed by master and sets the maximum VID the VR will support. If a  
higher VID code is received, the VR will respond with a “not supported”  
acknowledgement. VR12.5 & VR12.6 VID format, e.g., B5h = 2.3 V (see VID  
Table)  
Vout_Max  
RW  
Data register containing currently programmed VID voltage. VID data format.  
VR12.5 & VR12.6 VID format, e.g., 97h = 2.0 V  
31h  
32h  
VID setting  
Pwr State  
RW  
RW  
00h  
00h  
Register containing the current programmed power state.  
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23  
NCP81105, NCP81105H  
Index  
Name  
Description  
Access  
Default  
Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is  
sign bit, 0 = positive margin, 1 = negative margin. Remaining 7 BITS are # VID  
steps for margin 2s complement.  
00h=no margin  
01h=+1 VID step  
33h  
Offset  
RW  
00h  
02h=+2 VID steps  
FFh=1 VID step  
FEh=2 VID steps.  
Bit 0 set to 1 causes VR_RDY to respond to a SetVID (0.0 V) command as a  
valid VID voltage setting instead of a disable command (only after ramping to a  
nonzero VID after startup).  
34h  
MultiVR Config  
RW  
00h  
Bit 1 set to 1 locks the current VID and Power State settings until such time as  
the VR is issued a SetPS(00h) command.  
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24  
NCP81105, NCP81105H  
Phase Detection Sequence  
During startup, the number of operational phases is determined by the internal circuitry monitoring the CSN inputs.  
Normally, NCP81105 operates as a 3phase PWM controller. Connecting the CSN2 pin to V programs 2phase operation  
CC  
using phases 1 and 3. Connecting the CSN3 pin to V programs 1phase operation using phase 1.  
CC  
Prior to soft start, while ENABLE is high, the CSN2 and CSN3 pins have approximately 50 kW to ground. An internal  
comparator checks the voltage of the CSN pins and compares them to a reference voltage. If either pin is tied to V , its voltage  
CC  
is above the reference voltage and the controller is configured for reducedphase operation. Otherwise, the resistance pulls the  
pin voltages to ground, which is below the reference, and the part operates in 3 phase mode.  
PHASE COUNT TABLE  
Number  
of Phases  
Programming Pins (CSNx)  
What to do with Unused Pins  
No unused pins  
3
2
All CSN pins connected normally  
Tie CSN2 to VCC through 2 kW;  
CSN3, CSN1 connected normally  
Tie CSP2 to ground;  
Float PWM2  
1
Tie CSN3 to VCC through 2 kW;  
CSN1 connected normally  
Tie CSN2, CSP2 & CSP3 to ground;  
Float PWM2, PWM3 & OD#  
BOOT Voltage Programming  
The NCP81105 has a VBOOT voltage register that can be externally programmed. The Boot voltage for the NCP81105 is  
set using the VBOOT pin on power up. A 10 mA current is sourced from the VBOOT pin into an external resistance connected  
to ground, and the resulting voltage is measured. This is compared with the thresholds in the table below and the corresponding  
value is placed in the VBOOT register (26h). This value is set on power up and cannot be changed after the initial power up  
sequence is complete.  
BOOT VOLTAGE TABLE  
Resistance  
30.1k  
49.9k  
Boot Voltage  
0 V  
1.65 V  
69.8k  
1.70 V  
Open  
1.75 V  
Addressing the NCP81105  
The NCP81105 has fixed SVID device address 0000.  
Remote Sense Amplifier  
A high performance, high input impedance, differential amplifier is provided to accurately sense the output voltage of the  
regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense  
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage and a voltage to bias the  
output above ground.  
ǒ
Ǔ
ǒ
Ǔ
ǒ
Ǔ
VDIFFOUT + VVSP * VVSN ) 1.3 V * VDAC * VDROOP * VCSREF  
VDROOP + VCSCOMP   Droop Gain Scaling (see the Droop Gain Table)  
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25  
NCP81105, NCP81105H  
High Performance Voltage Error Amplifier  
The Remote Sense Amplifier output is applied to a Type 3 compensation network formed by the error amplifier, external  
tuning components, and internal integrator. The noninverting input of the error amplifier is connected to the same reference  
voltage used to bias the Remote Sense Amplifier output. The integrating function of the Type 3 feedback compensation is  
performed internally and does not require external capacitor Cf1 (see below).  
Cf  
Rin1  
Cf1  
Rf  
Cin  
Rin2  
_
COMP  
+
Vbias  
ERROR  
Figure 12. Traditional Type 3 External Compensation  
Cf  
Rin1  
Cin  
Rin2  
Rf  
_
COMP  
ERROR  
+
Vbias  
Figure 13. NCP81105 Modified Type 3 External Compensation  
Initial tuning should be based on traditional Type 3 compensation. When ideal Type 3 component values have been  
determined, the closest setting for the internal integrator is given by the following equation:  
INT_SETTING + 4.83   1012   Rf   Rin1   CF1; Rf & Rin1 in Ohms , Cf1 in nF  
The internal integrator is programmed using the INT_SEL pin according to the following table:  
INTEGRATOR TABLE  
R
INT_SETTING  
INT_SEL  
10k  
1
2
22k  
36k  
4
51k  
8
68k  
10  
12  
16  
32  
64  
91k  
120k  
160k  
220k  
Recalculation of the initial tuning should be performed using the Cf1 value given by the Cf1 equation below in order to  
determine whether readjustment of other components would provide more optimal compensation.  
Cf1 (nF) + 2.07   105   INT_SETTINGń(Rf   Rin1)  
If an acceptable tuning cannot be produced by the closest Equivalent Type 3 Cf1, then reoptimization should be tried with  
a different internal integrator setting.  
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26  
NCP81105, NCP81105H  
Differential Current Balance Amplifiers  
Each phase has a low offset differential amplifier to sense the current of that phase in order to balance current. The CSNx  
and CSPx pins are high impedance inputs, but it is recommended that the external filter resistor RCSN not exceed 10 kW to  
avoid offset due to leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for best current  
balance. The external filter RCSN and CCSN time constant should match the inductor L/DCR time constant, but fine tuning  
of this time constant is not required.  
RCSN  
DCR  
CCSN  
SWNx  
VOUT  
LPHASE  
RCSN  
+
LPHASE  
CCSN * DCR  
1
2
Figure 14.  
The individual phase current signals are combined with the COMP and ramp signals at each PWM comparator input. In this  
way, current is balanced via a current mode control approach.  
Total Current Sense Amplifier  
The NCP81105 uses a patented approach to sum the phase currents into a single, temperature compensated, total current  
signal. This signal is then used to produce the output voltage droop, monitor total output current, and shut off switching if  
current exceeds the set limit.  
The Rref resistors average the voltages at the output sides of the inductors to create a low impedance reference voltage at  
CSREF. The Rph resistors sum currents from the switchnodes to the virtual CSREF potential created at the CSSUM pin by  
the amplifier. The total current signal at the amplifier output is the difference between CSCOMP and CSREF. The amplifier  
lowpass filters and amplifies the voltage across the inductors to extract only the voltage across the inductor series resistances  
(DCR).  
CSN1  
Cref  
Rref1  
Rref2  
CSN2  
CSN3  
SWN1  
SWN2  
SWN3  
CSREF  
CSSUM  
CSCOMP  
Rref3  
Rph1  
Ccs1  
Ccs2  
Rph2  
Rph3  
RCS1  
RCS2  
Rth  
Figure 15.  
The equation for the DC total current signal is:  
Rcs1*Rth  
Rcs2 ) Rcs1)Rth  
ǒ * DCRǓ  
* IoutTotal  
VCSCOMPCSREF +   
Rph  
Set the DC gain by adjusting the value of the Rph resistors to make the ratio of total current signal to output current equal  
to the desired loadline. The Rph resistor value must be high enough to keep Rph current below 0.5 mA when switchnodes are  
at nominal input voltage. If the voltage from CSCOMP to CSREF at ICCMAX is less than 100 mV, increase the gain of the  
CSCOMP amp by a multiple of 2 until it is at or above 100 mV, and insert the resistor between the DGAIN pin and ground  
that results in the correct loadline. See the Droop Gain Table. This is recommended to provide a high enough total current signal  
to avoid impacts of offset voltage on current monitoring and the overcurrent shutdown threshold.  
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27  
NCP81105, NCP81105H  
An NTC thermistor (Rth) in the feedback network placed near the Phase 1 inductor senses the inductor temperature and  
compensates both the DC gain and the filter time constant for the DCR change with temperature. The values of Rcs1 and Rcs2  
are set based on the effect of temperature on both the thermistor and inductor. The thermistor should be placed near the Phase  
1 inductor so that it measures the temperature of the inductor providing current in the PS1 power mode.  
The pole frequency (F ) of the CSCOMP filter should be set equal to the zero frequency (F ) of the output inductor. This  
P
Z
causes the total current signal to contain only the component of inductor voltage caused by the DCR voltage, and therefore to  
be proportional to inductor current. Connecting Ccs2 in parallel with Ccs1 allows fine tuning of the pole frequency using  
commonly available capacitor values. It is best to perform fine tuning during transient testing.  
DCR@25° C  
FZ  
+
2 * PI * LPhase  
1
FP  
+
Rcs1*Rth@25° C  
ǒ
Ǔ* Ccs1 ) Ccs2  
(
)
2 * PI * Rcs2 ) Rcs1)Rth@25° C  
Programming the Loadline (Droop Gain)  
An output loadline is a power supply characteristic wherein the regulated (DC) output voltage decreases proportional to load  
current. This characteristic reduces the amount of output capacitance needed to minimize output voltage variation during load  
transients that exceed the speed of the regulation loop. In the NCP81105, a loadline is produced by adding a signal proportional  
to output load current to the output voltage feedback signal thereby satisfying the voltage regulator at an output voltage  
reduced in proportion to load current.  
The loadline is programmed by the combined gains of the Total Current Sense Amplifier and the gain from the output of  
this amplifier to the input of the Remote Sense Amplifier. The latter gain is referred to as Droop Gain Scaling, and has four  
possible values programmed by the value of resistance connected from the DGAIN pin to ground. For systems with full load  
output voltage droop greater than 100 mV, the Droop Gain Scaling can be 100%. Other systems should use lower Droop Gain  
Scaling and correspondingly higher Total Current Sense Amplifier gain, such that at full load the CSCOMP to CSREF voltage  
is 100 mV or greater. The following table shows the DGAIN resistances required to program different Droop Scalings.  
Droop Gain Table  
R
Droop Gain Scaling  
Effect  
Droop equals the CSCOMP to CSREF voltage  
Droop equals half of the CSCOMP to CSREF voltage  
Droop equals one quarter of the CSCOMP to CSREF voltage  
Zero milliohm loadline (no loadline)  
DGAIN  
10k  
25k  
100%  
50%  
25%  
0%  
45k  
w70k  
Programming the Current Limit  
The current limit thresholds are programmed with a resistor between the ILIM and CSCOMP pins. The ILIM pin voltage  
is a buffered replica of the CSREF voltage. The ILIM current is mirrored internally to the current limit comparators and to IOUT  
(increased by the IOUT Current Gain). The 100% current limit trips if ILIM current exceeds the Delayed Shutdown Threshold  
for the Delayed Shutdown Time. Current limit trips with minimal delay if ILIM current exceeds the Immediate Shutdown  
Threshold. Set the value of the current limit resistor based on the CSCOMPCSREF voltage as shown below.  
Rcs1*Rth  
Rcs2 ) Rcs1)Rth * IoutLIMIT * DCR  
ǒ
Ǔ
VCSCOMPCSREF@ILIMIT  
Rph  
RLIMIT  
+
or RLIMIT +  
IDS  
IDS  
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28  
NCP81105, NCP81105H  
Rth  
Rcs2  
Rcs1  
SWN1  
SWN2  
SWN3  
Ccs2  
Ccs1  
Rph1  
Rph2  
Rph3  
CONTROLLER  
SCALING  
_
+
CSSUM  
CSREF  
CSCOMP  
DGAIN  
CSN1  
CSN2  
CSN3  
Rref1  
Rref2  
Rref3  
Rdgain  
to Remote  
Cref  
Sense Amplifier  
ILIM  
Rilim  
IOUT  
buffer  
Riout  
Current  
Mirror  
Current Limit  
Comparators  
Figure 16.  
Programming IOUT  
The IOUT pin sources a current equal to the ILIM current gained by the IOUT Current Gain. The voltage on the IOUT pin  
is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to  
ICCMAX generates a 2 V signal on IOUT. A pullup resistor to 5 V V can be used to offset the IOUT signal positive if  
CC  
needed.  
V
DIMAX * RLIMIT  
RIOUT  
+
R
*Rth  
CS1  
R
)
ȡ
CS2  
ȣ
* IoutICC_MAX * DCR  
R
)Rth  
CS1  
AIIOUT  
*
ȧ
ȧ
Rph  
Ȣ
Ȥ
Programming ICC_MAX  
The SVID interface conveys the platform ICC_MAX value to the CPU from register 21h. A resistor to ground on the  
IMAX pin programs this register at the time the part in enabled. Current is sourced from this pin to generate a voltage on the  
program resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less  
than 10k.  
R * IIMAX * 256 A  
ICC_MAX21h  
+
VIMAXFS  
Improving Dynamic VID (DVID) Settling Time  
Upon each increment of the internal DAC following a DVID UP command, the NCP81105 outputs a pulse of current from  
the VSN pin. If a parallel RC network is inserted into the path from VSN to VSS_SENSE, the voltage between VSP and VSN  
is temporarily decreased, which causes the output voltage during DVID to be regulated slightly higher to compensate for the  
response of the Droop function to output current flowing into the output capacitors.  
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29  
NCP81105, NCP81105H  
VCC_SENSE  
VSS_SENSE  
VSP  
VSN  
REMOTE SENSE  
+
AMPLIFIER  
_
RFF  
CFF  
CONTROLLER  
+
_
DVID UP  
INCREMENT  
CURRENT  
PULSES  
DAC  
DAC  
VSN  
Figure 17.  
The R and C values should be chosen according to the following equations:  
Loadline * Cout  
1.35 * 109  
RFF  
+
W
200  
CFF  
+
nF  
RFF  
Programming TSENSE  
A temperature sense input is provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage  
on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter and  
then digitally converted to temperature and stored in SVID register 17h. A 220k NTC similar to the Murata  
NCP15WM224E03RC should be used.  
Precision Oscillator  
A programmable precision oscillator is provided to control the switching frequency of each phase. The oscillator serves as  
the master clock to the ramp generator circuits, which each run at the same frequency. The ROSC pin sources a current into  
an external programming resistor. The voltage present at the ROSC pin is read by the internal ADC and used to set the frequency  
according to the following table.  
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30  
NCP81105, NCP81105H  
SWITCHING FREQUENCY TABLE (PS0)  
ROSC  
(kW)  
Frequency  
(kHz)  
ROSC  
(kW)  
Frequency  
(kHz)  
ROSC  
(kW)  
Frequency  
(kHz)  
ROSC  
(kW)  
Frequency  
(kHz)  
10  
246  
272  
298  
323  
348  
373  
397  
421  
37.4  
42.2  
46.4  
49.9  
54.9  
60.4  
64.9  
69.8  
445  
468  
492  
515  
538  
561  
584  
605  
75  
656  
720  
127  
133  
143  
150  
162  
169  
187  
210  
1132  
1185  
1236  
1285  
1333  
1377  
1426  
1475  
13.3  
16.2  
19.6  
23.2  
26.1  
29.4  
33.2  
80.6  
86.6  
93.1  
100  
105  
113  
121  
785  
845  
906  
966  
1023  
1078  
Ramp Generator Circuits  
In PS0, the oscillator controls the frequency of triangle ramps for the pulse width modulator. Ramp amplitude depends on  
the VRMP pin voltage in order to provide input voltage feed forward compensation. The ramps have equal phase displacement  
with respect to each other.  
Ramp FeedForward Circuit and Ramp UVLO  
The ramp generator includes voltage feedforward control that varies the ramp magnitude proportional to the VRMP pin  
voltage. The PWM ramp voltage is changed according to the following:  
Vin  
VRAMPpk+pkPP + 0.1 * VVRMP  
Vramp_pp  
CompIL  
Duty  
The VRMP pin also has a UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin  
is a high impedance input when the controller is disabled or put into PS4. The resistance of an RC filter at the VRMP pin should  
not exceed 10 kW.  
PWM Comparators  
The noninverting input of each comparator (one for each phase) is connected to the summation of the output of the error  
amplifier (COMP) and each phase current (I * DCR * Phase Balance Gain Factor). The inverting input is connected to the  
L
triangle ramp voltage of that phase. The output of the comparator generates the PWM output.  
During steady state PS0 operation, the main rail PWM pulses are centered on the valley of the triangle ramp waveforms and  
both edges of the PWM signals are modulated. During a transient event, the duty cycle can increase rapidly as the error amp  
signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load.  
Power State 1 (PS1)  
The NCP81105 supports PS1 by providing the OD# output. When the OD# output is connected to the phase 2 and 3 DrMOS  
ZCD inputs, the PS1 state causes the NCP81105 to send low levels on OD#, PWM2 and PWM3, causing the power stages of  
phases 2 and 3 to be tristated (both high and low side FETs off). The modulation mode changes from constantfrequency  
dualedge modulation to Constant ON Time modulation.  
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31  
NCP81105, NCP81105H  
PS0  
PS1  
PS2  
PS1  
PS0  
(PWM2 & PWM3 ACTIVE)  
(PWM2 & PWM3 ACTIVE)  
(PWM2 & PWM3 LOW)  
(PWM2 & PWM3 LOW)  
(PWM2 & PWM3 LOW)  
OD#  
PWM1  
DRVH1SW1  
PH1  
INDUCTOR  
CURRENT  
AVERAGE PHASE CURRENT  
0
SMOD  
DRVL1  
Figure 18.  
Zero Cross Detect (ZCD) Enabling (PS2)  
The NCP81105 supports the DrMOS ZCD function (diode emulation) by providing the SMOD output.  
When the controller receives an SVID command asking for PS2 mode (lighter load current condition), PWM2, PWM3 and  
OD# are held low, causing the power stages of phases 2 and 3 to be inactive (open circuit). When the NCP81105 detects that  
inductor current is no longer positive, SMOD is pulled LOW to enable the DrMOS diode emulation function, and the PWM1  
output continues fullrange twostate outputs (from 0 V to the V rail).  
CC  
For DrMOS without a ZCD function, when SMOD goes low in response to the NCP81105 detecting that inductor current  
is no longer positive, DrMOS synchronous rectification is immediately disabled.  
For PS0 and PS1 states, SMOD stays HIGH, disabling the DrMOS ZCD function.  
Protection Features  
Input Under Voltage Protection  
NCP81105 monitors the VCC supply voltage at the VCC pin and the VDC power source at the VRMP pin in order to provide  
under voltage protection. If either supply dips below their threshold, the controller will shut down the outputs. Upon recovery  
of the supplies, the controller reenters its startup sequence, and soft start begins.  
Soft Start  
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the  
predetermined slew rate in the spec table. The CSN2 and CSN3 pins will start out applying a test resistance to collect data on  
phase count. After the configuration data is collected, the controller is enabled and sets the OD# and SMOD signals low to force  
the drivers to stay in diode mode. DRVON will then be asserted to enable the drivers. A period of time after the controller senses  
that DRVON is high, the COMP pin is released to begin softstart. The DAC ramps from zero to the target DAC code and the  
PWM outputs will begin to fire. SMOD will go high when the first PWM1 pulse is produced to preclude discharge of a  
precharged output. Upon PWM2 or PWM3 going high for the first time, OD# is set high.  
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32  
NCP81105, NCP81105H  
SoftStart Sequence  
VCC  
EN  
TA  
DrMOS Enabled  
DRON  
Softstart Delay  
DAC  
COMP  
PWM1  
SMOD  
PWM2  
OD#  
VOUT  
Figure 19.  
Over Current LatchOff Protection  
The NCP81105 provides two different types of current limit protection. During normal operation a programmable total  
current limit is provided that is scaled back during reducedphase, power saving operation. This limit is programmed with a  
resistor between the CSCOMP and ILIM pins. The current from the ILIM pin to this resistor is then compared to internal I  
DS  
and I currents. If the ILIM pin current exceeds the I level, an internal latchoff timer starts. When the timer expires, the  
IS  
DS  
controller shuts down if the fault is not removed. If the current into the pin exceeds I , the controller will shut down  
IS  
immediately. To recover from an OCP fault, the EN pin must be cycled low.  
The overcurrent limit is programmed by a resistor from the ILIM pin to the CSCOMP pin. The resistor value can be  
calculated by the following equation:  
VCSCOMP * VCSREF  
RILIM  
+
IDS  
Output Under Voltage Monitor  
The output voltage is monitored by a dedicated differential amplifier. If the output falls below target by more than the “Under  
Voltage Threshold Below DACDroop”, the UVL comparator sends the VR_RDY signal low.  
Over Voltage Protection  
During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage  
exceeds the DAC voltage by the “Over Voltage Threshold Above DAC”, PWMs will be forced low, and the SMOD pin will  
also go low when the voltage drops below that threshold. After the OVP trip the DAC will ramp slowly down to zero to avoid  
a negative output voltage spike during shutdown. If the DAC + OVP Threshold drops below the output, SMOD will again go  
high, and will toggle between low and high as the output voltage follows the DAC + OVP Threshold down. When the DAC  
gets to zero, the PWMs will be held low and the SMOD and DRVON pin voltages will remain high. To reset the part, the EN  
pin must be cycled low. During softstart, the OVP threshold is set to the Absolute Over Voltage Threshold. This allows the  
controller to start up without false triggering the OVP if residual voltage from a prior period of operation is already present  
at the output.  
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33  
NCP81105, NCP81105H  
OVP Threshold Behavior Normal PS0 and PS1 Operation  
VSPVSN  
VSPVSN  
DAC  
DAC  
Fault  
Fault  
(VSP short  
to ground)  
(VSP short  
to ground)  
OVP  
OVP  
Triggered  
Triggered  
Rampdown  
Latched  
Rampdown  
Latched  
DAC  
DAC  
Latch Off  
Latch Off  
PWM  
SMOD  
OD#  
PWM  
SMOD  
OD#  
PS0  
PS1  
Figure 20.  
OVP Threshold Behaviour During Softstart into Precharged Output  
OVP Threshold during Softstart  
OVP Threshold after Softstart  
VSPVSN (precharged)  
Target VID  
Reached  
DAC  
0
PWM  
SMOD  
OD#  
Figure 21.  
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34  
NCP81105, NCP81105H  
Printed Circuit Board Layout Notes  
The NCP81105 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues  
related to layout for easy design use. To ensure proper function there are some general PCB layout rules to follow:  
Careful layout for perphase and total current sensing are critical for jitter minimization, accurate current balancing and  
limiting, and IOUT reporting. Give the first priority in component placement and trace routing to per phase and total current  
sensing circuits. The per phase inductor current sense RC filters should always be placed as close to the CSN and CSP pins  
on the controller as possible. The filter cap from CSCOMP to CSSUM should also be close to the controller. The temperature  
compensating thermistor should be placed as close as possible to the Phase 1 inductor. The wiring path between Rcs2 and Rphx  
should be kept as short as possible and well away from switch node lines. The above layout notes are shown in the following  
diagram:  
CONTROLLER  
CSCOMP  
43  
Ccs2  
Ccs1  
Rcs1  
Rth  
PLACE AS CLOSE  
AS POSSIBLE TO  
PHASE 1 INDUCTOR  
KEEP THIS PATH AS SHORT  
AS POSSIBLE, AND WELL AWAY  
FROM SWITCHNODE LINES  
_
+
CSSUM  
CSREF  
42  
40  
Rcs2  
Rph1  
Rph2  
Rref1  
Rref2  
TO INDUCTOR  
SWITCHNODE  
TERMINAL  
_
+
CSP1  
CSN1  
34  
35  
Rcsp1  
Rcsp2  
Ccsp1  
Ccsp2  
TO INDUCTOR  
VOUT TERMINAL  
TO INDUCTOR  
SWITCHNODE  
TERMINAL  
_
+
CSP2  
CSN2  
38  
39  
TO INDUCTOR  
VOUT TERMINAL  
PER PHASE CURRENT SENSE  
RC SHOULD BE PLACED  
CLOSE TO CSPx PINS  
Figure 22.  
Place the V decoupling caps as close as possible to the controller VCC pin. For any RC filter on the VCC pin, the resistor  
CC  
should be no higher than 5 W to prevent large voltage drop.  
The small feedback cap from COMP to FB should be as close to the controller as possible. Keep the FB traces short to  
minimize their capacitance to ground.  
ORDERING INFORMATION  
Device  
NCP81105MNTXG  
Package  
Shipping  
QFN36  
(PbFree)  
5000 / Tape & Reel  
NCP81105HMNTXG  
QFN36  
(PbFree)  
5000 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
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35  
NCP81105, NCP81105H  
PACKAGE DIMENSIONS  
QFN36 5x5, 0.4P  
CASE 485CC  
ISSUE O  
NOTES:  
L
L
A
B
D
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSIONS: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.15 AND 0.30mm FROM THE TERMINAL TIP.  
4. COPLANARITY APPLIES TO THE EXPOSED  
PAD AS WELL AS THE TERMINALS.  
L1  
PIN ONE  
LOCATION  
DETAIL A  
ALTERNATE  
CONSTRUCTIONS  
E
MILLIMETERS  
DIM MIN  
MAX  
1.00  
0.05  
A
A1  
A3  
b
0.80  
−−−  
0.15  
C
EXPOSED Cu  
MOLD CMPD  
0.20 REF  
0.15  
0.25  
0.15  
C
D
D2  
E
E2  
e
K
5.00 BSC  
TOP VIEW  
3.40  
3.60