NCV7356D2R2G全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

NCV7356

Single Wire CAN Transceiver

The NCV7356 is a physical layer device for a single wire data link

capable of operating with various Carrier Sense Multiple Access

with Collision Resolution (CSMA/CR) protocols such as the Bosch

Controller Area Network (CAN) version 2.0. This serial data link

network is intended for use in applications where high data rate is not

required and a lower data rate can achieve cost reductions in both the

physical media components and in the microprocessor and/or

dedicated logic devices which use the network.

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MARKING DIAGRAMS

8

The network shall be able to operate in either the normal data rate

mode or a high−speed data download mode for assembly line and

service data transfer operations. The high−speed mode is only

intended to be operational when the bus is attached to an off−board

service node. This node shall provide temporary bus electrical loads

which facilitate higher speed operation. Such temporary loads should

be removed when not performing download operations.

The bit rate for normal communications is typically 33 kbit/s, for

high−speed transmissions like described above a typical bit rate of

83 kbit/s is recommended. The NCV7356 is designed in accordance

to the Single Wire CAN Physical Layer Specification GMW3089

V2.4 and supports many additional features like undervoltage

lockout, timeout for faulty blocked input signals, output blanking

time in case of bus ringing and a very low sleep mode current.

V7356

ALYW

G

1

SOIC−8

D SUFFIX

CASE 751

1

14

1

NCV7356G

AWLYWW

14

1

SOIC−14

D SUFFIX

CASE 751A

A

= Assembly Location

WL, L = Wafer Lot

= Year

WW, W = Work Week

G or G = Pb−Free Package

Y

PIN CONNECTIONS

TxD

MODE0

MODE1

RxD

1

2

3

4

8

7

6

5

GND

Features

CANH

LOAD

• Fully Compatible with J2411 Single Wire CAN Specification

• 60 mA (max) Sleep Mode Current

V

BAT

• Operating Voltage Range 5.0 to 27 V

• Up to 100 kbps High−Speed Transmission Mode

• Up to 40 kbps Bus Speed

(Top View)

GND

TxD

1

2

3

4

5

6

7

14 GND

13 NC

• Selective BUS Wake−Up

MODE0

MODE1

RxD

CANH

LOAD

12

11

10

9

• Logic Inputs Compatible with 3.3 V and 5 V Supply Systems

• Control Pin for External Voltage Regulators (14 Pin Package Only)

• Standby to Sleep Mode Timeout

• Low RFI Due to Output Wave Shaping

• Fully Integrated Receiver Filter

• Bus Terminals Short−Circuit and Transient Proof

• Loss of Ground Protection

• Protection Against Load Dump, Jump Start

• Thermal Overload and Short Circuit Protection

• ESD Protection of 4.0 kV on CANH Pin (2.0 kV on Any Other Pin)

• Undervoltage Lock Out

• Bus Dominant Timeout Feature

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

V

BAT

NC

INH

GND

8

GND

(Top View)

ORDERING INFORMATION

†

Device

NCV7356D1G

Package

Shipping

SOIC−8

(Pb−Free)

98 Units / Rail

NCV7356D1R2G SOIC−8

(Pb−Free)

2500 Tape & Reel

NCV7356D2

SOIC−14

55 Units / Rail

NCV7356D2G

SOIC−14

(Pb−Free)

NCV7356D2R2

SOIC−14

2500 Tape & Reel

NCV7356D2R2G SOIC−14

(Pb−Free)

• Pb−Free Packages are Available

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

©

Semiconductor Components Industries, LLC, 2007

1

Publication Order Number:

January, 2007 − Rev. 5

NCV7356/D

NCV7356

V

BAT

NCV7356

5 V Supply

and

References

Biasing and

Monitor

V

BAT

Reverse

Current

Protection

RC−OSC

Wave Shaping

CAN Driver

CANH

Time Out

TxD

Feedback

Loop

Input Filter

LOAD

MODE0

MODE1

MODE

CONTROL

Loss of

Ground

Detection

Receive

Comparator

RxD

Reverse

Current

Protection

RxD Blanking

Time Filter

GND

Figure 1. 8−Pin Package Block Diagram

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2

NCV7356

V

BAT

INH

NCV7356

5 V Supply

and

References

Biasing and

Monitor

V

BAT

Reverse

Current

Protection

RC−OSC

Wave Shaping

CAN Driver

CANH

Time Out

TxD

Feedback

Loop

Input Filter

LOAD

MODE0

MODE1

MODE

CONTROL

Loss of

Ground

Detection

Receive

Comparator

RxD

Reverse

Current

Protection

RxD Blanking

Time Filter

GND

Figure 2. 14−Pin Package Block Diagram

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3

NCV7356

PACKAGE PIN DESCRIPTION

SOIC−8

SOIC−14

Symbol

TxD

Description

1

2

3

4

5

6

7

8

−

2

Transmit data from microprocessor to CAN.

Operating mode select input 0.

3

MODE0

MODE1

RxD

4

Operating mode select input 1.

5

Receive data from CAN to microprocessor.

Battery input voltage.

10

11

V

BAT

LOAD

CANH

GND

NC

Resistor load (loss of ground detection low side switch).

Single wire CAN bus pin.

12

1, 7, 8, 14

6, 13

9

Ground

No Connection (Note 1)

INH

Control pin for external voltage regulator (high voltage high side switch) (14 pin package only)

1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package.

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4

NCV7356

Electrical Specification

All voltages are referenced to ground (GND). Positive

currents flow into the IC. The maximum ratings given in

the table below are limiting values that do not lead to a

permanent damage of the device but exceeding any of these

limits may do so. Long term exposure to limiting values

may affect the reliability of the device.

MAXIMUM RATINGS

Rating

Symbol

Condition

Min

Max

Unit

Supply Voltage, Normal Operation

V

−

−0.3

−

18

40

V

BAT

Short−Term Supply Voltage, Transient

V

Load Dump; t < 500 ms

Jump Start; t < 1.0 min

ISO 7637/1 Pulse 1 (Note 2)

ISO 7637/1 Pulses 2 (Note 2)

ISO 7637/1 Pulses 3A, 3B

V (peak)

BAT.LD

−

27

V

Transient Supply Voltage

CANH Voltage

V

−50

−

BAT.TR1

BAT.TR2

BAT.TR3

100

200

−200

−20

−40

−50

−

V

CANH

V

< 27 V

= 0 V

BAT

40

V

Transient Bus Voltage

V

ISO 7637/1 Pulse 1 (Note 3)

ISO 7637/1 Pulses 2 (Note 3)

ISO 7637/1 Pulses 3A, 3B (Note 3)

Via RT > 2.0 kW

−

V

CANHTR1

CANHTR2

CANHTR3

Transient Bus Voltage

100

200

40

Transient Bus Voltage

−200

−40

−0.3

−4000

DC Voltage on Pin LOAD

DC Voltage on Pins TxD, MODE1, MODE0, RxD

ESD Capability of CANH

V

LOAD

V

−

7.0

DC

ESDBUS

V

Human Body Model

4000

(with respect to V

and GND)

BAT

Eq. to Discharge 100 pF with 1.5 kW

ESD Capability of Any Other Pin

V

ESD

Human Body Model

−2000

2000

V

Eq. to Discharge 100 pF with 1.5 kW

Maximum Latchup Free Current at Any Pin

Storage Temperature

I

−

−500

−55

−40

−

500

150

mA

°C

LATCH

T

STG

−

Junction Temperature

T

J

150

Lead Temperature Soldering

Reflow: (SMD styles only)

SOIC−14

SOIC−8

T

sld

60 s − 150 s above 183°C

60 s − 150 s above 217°C

240 peak

260 peak

−

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. ISO 7637 test pulses are applied to V

via a reverse polarity diode and >1.0 mF blocking capacitor.

BAT

3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.

4. ESD measured per Q100−002 (EIA/JESD22−A114−A).

TYPICAL THERMAL CHARACTERISTICS

Test Condition, Typical Value

Min Pad Board

1, Pad Board

Parameter

Unit

SOIC−8

Junction−to−Lead (psi−JL7, Y ) or Pins 6−7

57 (Note 5)

51 (Note 6)

°C/W

JL8

Junction−to−Ambient (R , q

)

187 (Note 5)

128 (Note 6)

q

JA JA

SOIC−14

Junction−to−Lead (psi−JL8, Y

Junction−to−Ambient (R , q

)

30 (Note 7)

30 (Note 8)

84 (Note 8)

°C/W

JL8

)

122 (Note 7)

q

JA JA

2

5. 1 oz copper, 53 mm coper area, 0.062″ thick FR4.

2

6. 1 oz copper, 716 mm coper area, 0.062″ thick FR4.

2

7. 1 oz copper, 94 mm coper area, 0.062″ thick FR4.

2

8. 1 oz copper, 767 mm coper area, 0.062″ thick FR4.

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5

NCV7356

ELECTRICAL CHARACTERISTICS (V

= 5.0 to 27 V, T = −40 to +125°C, unless otherwise specified.)

BAT

A

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

GENERAL

Undervoltage Lock Out

V

−

3.5

−

5.0

−

4.8

6.0

8.0

35

V

BATuv

Supply Current, Recessive,

All Active Modes

I

V

= 18 V,

Not High Speed Mode

High Speed Mode

= 27 V, MODE0 = MODE1 = H,

BAT

mA

BATN

BAT

TxD Open

−

Normal Mode Supply Current,

Dominant

I

V

−

30

mA

BATN

(Note 10)

TxD = L, R

= 200 W

load

High−Speed Mode Supply Current,

Dominant

I

V

BAT

= 16 V, MODE0 = H, MODE1 = L,

−

70

60

75

BATN

(Note 10)

TxD = L, R

= 75 W

load

Wake−Up Mode Supply Current,

Dominant

I

V

= 27 V,

BATW

BAT

(Note 10)

MODE0 = L, MODE1 = H,

TxD = L, R = 200 W

load

Sleep Mode Supply Current (Note 9)

I

V

= 13 V, T = 85°C,

−

30

60

mA

BATS

BAT

A

TxD, RxD, MODE0,

MODE1 Open

Thermal Shutdown (Note 10)

Thermal Recovery (Note 10)

CANH

T

−

155

126

−

180

150

°C

SD

T

REC

Bus Output Voltage

V

R > 200 W, Normal Mode

4.4

3.4

4.2

9.9

−

5.1

V

oh

L

6.0 V < V

< 27 V

BAT

Bus Output Voltage

Low Battery

V

oh

R > 200 W, Normal High−Speed Mode

L

5.0 V < V

< 6.0 V

BAT

Bus Output Voltage

High−Speed Mode

V

oh

R > 75 W, High−Speed Mode

5.1

L

8.0 V < V

< 16 V

BAT

HV Fixed Wake−Up

Output High Voltage

V

Wake−Up Mode, R > 200 W,

12.5

ohWuFix

L

11.4 V < V

< 27 V

BAT

HV Offset Wake−Up

Output High Voltage

V

Wake−Up Mode, R > 200 W,

V

–1.5

V

BAT

ohWuOffset

L

BAT

5.0 V < V

< 11.4 V

BAT

Recessive State

Output Voltage

V

Recessive State or Sleep Mode,

= 6.5 kW

−0.20

0.20

ol

R

load

Bus Short Circuit Current

−I

V

CANH

= 0 V, V = 27 V, TxD = 0 V

BAT

50

−

350

10

mA

CAN_SHORT

Bus Leakage Current

During Loss of Ground

I

Loss of Ground, V

= 0 V

−50

mA

LKN_CAN

CANH

(Note 11)

Bus Leakage Current, Bus Positive

Bus Input Threshold

I

TxD High

Normal, High−Speed Mode, HVWU

−10

2.0

−

10

mA

LKP_CAN

V

ih

2.1

2.2

V

6.0 v V v 27 V

BAT

Bus Input Threshold Low Battery

V

Normal, V

= 5.0 V to 6.0 V

1.6

6.6

1.7

−

2.2

7.9

V

ihlb

BAT

Fixed Wake−Up from Sleep

Input High Voltage Threshold

V

Sleep Mode, V

> 10.9 V

ihWuFix

(Note 10)

BAT

Offset Wake−Up from Sleep

Input High Voltage Threshold

V

Sleep Mode

V

BAT

−4.3

−

V −3.25

BAT

V

ihWuOffset

(Note 10)

LOAD

Voltage on Switched Ground Pin

V

I

= 1.0 mA

= 5.0 mA

−

0.1

0.5

1.0

V

W

LOAD_1mA

LOAD

V

LOAD

−

LOAD

V

R

I

= 7.0 mA, V

= 0 V

LOAD_LOB

LOAD

BAT

Load Resistance During Loss of

Battery

V

= 0

R

LOAD

+35%

BAT

LOAD

−10%

9. Characterization data supports I

10.Thresholds not tested in production, guaranteed by design.

11. Leakage current in case of loss of ground is the summary of both currents I

< 65 mA with conditions V

= 18 V, T = 125°C

BATS

BAT A

and I

.

LKN_CAN

LKN_LOAD

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6

NCV7356

ELECTRICAL CHARACTERISTICS (continued)(V

= 5.0 to 27 V, T = −40 to +125°C, unless otherwise specified.)

BAT

A

Characteristic

TXD, MODE0, MODE1

High Level Input Voltage

Low Level Input Voltage

TxD Pullup Current

Symbol

Condition

Min

Typ

Max

Unit

V

ih

6.0 < V

< 27 V

2.0

−

V

BAT

V

il

6.0 < V

< 27 V

0.8

50

BAT

−I

IL_TXD

TxD = L, MODE0 and 1 = H

5.0 < V < 27 V

10

mA

BAT

MODE0 and 1 Pulldown Resistor

R

10

−

50

kW

MODE_pd

RXD

Low Level Output Voltage

High Level Output Leakage

RxD Output Current

V

I

= 2.0 mA

−

−10

−

0.4

10

70

V

ol_rxd

RxD

I

V

= 5.0 V

mA

ih_rxd

RxD

Irxd

RxD

INH (14 Pin Package Only)

High Level Output Voltage

Leakage Current

V

I

= −180 mA

V

−0.8

V

BAT

−0.5

V

BAT

V

oh_INH

INH

BAT

I

MODE0 = MODE1 = L, INH = 0 V

−5.0

−

5.0

mA

INH_lk

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7

NCV7356

TIMING MEASUREMENT LOAD CONDITIONS

Normal and High Voltage Wake−Up Mode

High−Speed Mode

min load / min tau

min load / max tau

max load / min tau

max load / max tau

3.3 kW / 540 pF

3.3 kW / 1.2 nF

200 W / 5.0 nF

200 W / 20 nF

Additional 140 W tool resistance

to ground in parallel

Additional 120 W tool resistance

to ground in parallel

ELECTRICAL CHARACTERISTICS (5.0 V ≤ V

AC CHARACTERISTICS (See Figures 3, 4, and 5)

≤ 27 V, −40°C ≤ T ≤ 125°C, unless otherwise specified.)

A

BAT

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

Transmit Delay in Normal and Wake−Up Mode,

Bus Rising Edge (Notes 12, 13)

t

Tr

Min and Max Loads per Timing

Measurement Load Conditions

2.0

−

6.3

ms

Transmit Delay in Wake−Up Mode to V

Bus Rising Edge (Notes 12, 14)

,

t

Min and Max Loads per Timing

Measurement Load Conditions

2.0

1.8

−

18

10

ms

ihWU

TWUr

Transmit Delay in Normal Mode,

Bus Falling Edge (Notes 12, 13)

t

Tf

Min and Max Loads per Timing

Measurement Load Conditions

Transmit Delay in Wake−Up Mode,

Bus Falling Edge (Notes 12, 13)

t

Min and Max Loads per Timing

Measurement Load Conditions

3.0

13.7

1.5

3.0

TWU1f

Transmit Delay in High−Speed Mode,

Bus Rising Edge (Note 15)

t

Min and Max Loads per Timing

Measurement Load Conditions

0.1

THSr

THSf

Transmit Delay in High−Speed Mode,

Bus Falling Edge (Note 16)

Min and Max Loads per Timing

Measurement Load Conditions

0.04

Receive Delay, All Active Modes (Note 17)

t

CANH High to Low Transition

CANH Low to High Transition

0.3

−

1.0

ms

DR

RD

Input Minimum Pulse Length,

All Active Modes (Note 17)

t

CANH High to Low Transition

CANH Low to High Transition

0.1

−

1.0

mpDR

mpRD

Wake−Up Filter Time Delay

t

See Figure 4

10

0.5

−

70

6.0

−

ms

WUF

t

rb

See Figure 5

Receive Blanking Time, After TxD L−H Transition

TxD Timeout Reaction Time

t

Normal and High−Speed Mode

Wake−Up Mode

−

17

−

ms

tout

TxD Timeout Reaction Time

t

−

toutwu

Delay from Normal to High−Speed and

High Voltage Wake−Up Mode

t

−

30

dnhs

Delay from High−Speed and High Voltage

Wake−Up to Normal Mode

t

−

30

ms

dhsn

Delay from Normal to Standby Mode

Delay from Sleep to Normal Mode

t

V

BAT

V

BAT

V

BAT

= 6.0 V to 27 V

−

500

50

ms

dsby

t

dsnwu

dsleep

Delay from Standby to Sleep Mode (Note 18)

t

100

250

500

12.Minimum t loads measured from measured TxD voltage threshold to CANH = 1.0 V.

13.Maximum t load measured from measured TxD voltage threshold to CANH = 3.5 V @ V

= 27 V, CANH = 2.8 V @ V

= 5.0 V.,

BAT

CANH Threshold = V

+ V

.

ihMAX

goff

14.Maximum t load measured from measured TxD voltage threshold to CANH = 9.2 V.

= V , MAX + V = 7.9 V + 1.3 V = 9.2 V.

V

ihWUMAX

ihWUFIX

goff

15.Minimum t loads measured from measured TxD voltage threshold to CANH = 1.0 V.

Maximum t load measured from measured TxD voltage threshold to CANH = 3.5 V

V

ihMAX

+ V

= 2.2 V + 1.3 V = 3.5 V.

goff

16.Minimum t loads measured from measured TxD voltage threshold to CANH = 3.5 V.

+ V = 2.2 V + 1.3 V = 3.5 V.

V

ihMAX

goff

Maximum t loads measured from measured TxD voltage threshold to CANH = 1.0 V.

17.Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising

(Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising

and falling edges is 50 V/ms. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V.

For HVWU mode testing the high level on bus is V

in future revisions of GMW3089.

− 2 V. Relaxation of this non−critical parameter from 0.15 ms to 0.10 ms may be addressed

BAT

18.Tested on 14 Pin package only.

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8

NCV7356

BUS LOADING REQUIREMENTS

Characteristic

Symbol

Min

Typ

Max

Unit

Number of System Nodes

−

2

−

32

60

−

m

W

Network Distance Between Any Two ECU Nodes

Node Series Inductor Resistance (If required)

Ground Offset Voltage

Bus Length

R

ind

−

3.5

V

−

1.3

V

goff

−

Ground Offset Voltage, Low Battery

Device Capacitance (Unit Load)

Network Total Capacitance

V

−

0.1 x V

0.7

V

gofflowbat

BAT

C

ul

135

396

6435

2000

200

1.0

−

150

300

19000

6565

−

pF

W

C

tl

−

6490

−

Device Resistance (Unit Load)

R

ul

Device Resistance (Min Load)

R

min

W

Network Total Resistance

R

tl

−

4596

4.0

W

Network Time Constant (Note 19)

Network Time Constant in High−Speed Mode

High−Speed Mode Network Resistance to GND

t

−

ms

W

t

−

1.5

R

load

75

−

135

19.The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum

value is selected to ensure proper communication modes. Not all combinations of R and C are possible.

TIMING DIAGRAMS

V

TxD

50%

t

T

V

CANH

V max + V max

ih

goff

1 V

t

R

t

F

t

D

t

DR

V

RxD

50%

t

Figure 3. Input/Output Timing

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9

NCV7356

TIMING DIAGRAMS

V

CANH

V

ih

+ V

goff

t

WU

t

WU

t

WUF

V

RxD

wake−up

interrupt

t

< t

WUF

WU

t

Figure 4. Wake−Up Filter Time Delay

V

TxD

50%

t

V

CANH

V

ih

t

V

RxD

50%

t

RB

Figure 5. Receive Blanking Time

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10

NCV7356

FUNCTIONAL DESCRIPTION

TxD Input Pin

High Voltage Wake−Up Mode

This bus includes a selective node awake capability,

which allows normal communication to take place among

some nodes while leaving the other nodes in an undisturbed

sleep state. This is accomplished by controlling the signal

voltages such that all nodes must wake−up when they

receive a higher voltage message signal waveform. The

communication system communicates to the nodes

information as to which nodes are to stay operational

(awake) and which nodes are to put themselves into a non

communicating low power “sleep” state. Communication

at the lower, normal voltage levels shall not disturb the

sleeping nodes.

TxD Polarity

• TxD = logic 1 (or floating) on this pin produces an

undriven or recessive bus state (low bus voltage)

• TxD = logic 0 on this pin produces either a bus normal

or a bus high voltage dominant state depending on the

transceiver mode state (high bus voltage)

If the TxD pin is driven to a logic low state while the sleep

mode (Mode 0 = 0 and Mode 1 = 0) is activated, the

transceiver can not drive the CANH pin to the dominant

state.

The transceiver provides an internal pullup current on the

TxD pin which will cause the transmitter to default to the

bus recessive state when TxD is not driven.

Normal Mode

TxD input signals are standard CMOS logic levels.

Transmission bit rate in normal communication is

33 Kbits/s. In normal transmission mode the NCV7356

supports controlled waveform rise and overshoot times.

Waveform trailing edge control is required to assure that

high frequency components are minimized at the

beginning of the downward voltage slope. The remaining

fall time occurs after the bus is inactive with drivers off and

is determined by the RC time constant of the total bus load.

Timeout Feature

In case of a faulty blocked dominant TxD input signal,

the CANH output is switched off automatically after the

specified TxD timeout reaction time to prevent a dominant

bus.

The transmission is continued by next TxD L to H

transition without delay.

RxD Output Pin

Logic data as sensed on the single wire CAN bus.

MODE0 and MODE1 Pins

The transceiver provides a weak internal pulldown

current on each of these pins which causes the transceiver

to default to sleep mode when they are not driven. The

mode input signals are standard CMOS logic level for

3.3 V and 5 V supply voltages.

RxD Polarity

• RxD = logic 1 on this pin indicates a bus recessive

state (low bus voltage)

• RxD = logic 0 on this pin indicates a bus normal or

high voltage bus dominant state

MODE0

MODE1

Mode

RxD in Sleep Mode

L

H

L

Sleep Mode

RxD does not pass signals to the microprocessor while in

sleep mode until a valid wake−up bus voltage level is

received or the MODE0 and MODE 1 pins are not 0, 0

respectively. When the valid wake−up bus voltage signal

awakens the transceiver, the RxD pin signals an interrupt

(logic 0). If there is no mode change within 250 ms (typ),

the transceiver re−enters the sleep mode.

When not in sleep mode all valid bus signals will be sent

out on the RxD pin.

RxD will be placed in the undriven or off state when in

sleep mode.

High−Speed Mode

High Voltage Wake−Up

Normal Mode

H

Sleep Mode

Transceiver is in low power state, waiting for wake−up

via high voltage signal or by mode pins change to any state

other than 0,0. In this state, the CANH pin is not in the

dominant state regardless of the state of the TxD pin.

High−Speed Mode

RxD Typical Load

This mode allows high−speed download with bit rates up

to 100 Kbit/s. The output wave shapingaping circuit is

disabled in this mode. Bus transmitter drive circuits for

those nodes which are required to communicate in

high−speed mode are able to drive reduced bus resistance

in this mode.

Resistance: 2.7 kW

Capacitance: < 25 pF

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11

NCV7356

Bus LOAD Pin

Wave Shaping in High−Speed Mode

Resistor ground connection with internal open−on−loss−

of−ground protection

Wave shaping control of the rising and falling waveform

edges are disabled during high−speed mode. EMI

emissions requirements are waived during this mode. The

waveform rise time in this mode is less than 1.0 ms.

When the ECU experiences a loss of ground condition,

this pin is switched to a high impedance state.

The ground connection through this pin is not interrupted

in any transceiver operating mode including the sleep

mode. The ground connection only is interrupted when

there is a valid loss of ground condition.

This pin provides the bus load resistor with a path to

ground which contributes less than 0.1 V to the bus offset

voltage when sinking the maximum current through one

unit load resistor. This path exists in all operating modes,

including the sleep mode.

Short Circuits

If the CAN BUS pin is shorted to ground for any duration

of time, the current is limited as specified in the Electrical

Characteristics Table until an overtemperature shutdown

circuit disables the output high side drive source transistor

preventing damage to the IC.

Loss of Ground

In case of a valid loss of ground condition, the LOAD pin

is switched into high impedance state. The CANH

transmission is continued until the undervoltage lock out

voltage threshold is detected.

The transceiver’s maximum bus leakage current

contribution to V from the LOAD pin when in a loss of

ol

ground state is 50 mA over all operating temperatures and

3.5 < V

< 27 V.

BAT

Loss of Battery

In case of loss of battery (V

transceiver does not disturb bus communication. The

maximum reverse current into the power supply system

= 0 or open) the

BAT

V_BATInput Pin

Vehicle Battery Voltage

The transceiver is fully operational as described in the

Electrical Characteristics Table over the range 6.0 V <

(V ) doesn’t exceed 500 mA.

BAT

V

< 18 V as measured between the GND pin and the

pin.

INH Pin (14 pin package only)

BAT

The INH pin is a high−voltage highside switch used to

control the ECU’s regulated microcontroller power supply.

After power−on, the transceiver automatically enters an

intermediate standby mode, the INH output will go high

BAT

For 5.0 V < V < 6.0 V, the bus operates in normal

Bat

mode with reduced dominant output voltage and reduced

receiver input voltage. High voltage wake−up is not

possible (dominant output voltage is the same as in normal

or high−speed mode).

(up to V ) turning on the external voltage regulator. The

BAT

external regulator provides power to the ECU. If there is no

mode change within 250 ms (typ), the transceiver re−enters

the sleep mode and the INH output goes to logic 0

(floating).

When the transceiver has detected a valid wake−up

condition (bus HVWU traffic which exceeds the wake−up

filter time delay) the INH output will become high (up to

The transceiver operates in normal mode when 18 V <

V

Bat

< 27 V at 85°C for one minute.

CAN BUS

Input/Output Pin

Wave Shaping in Normal and High Voltage Wake−Up

Mode

V ) again and the same procedure starts as described

BAT

after power−on. In case of a mode change into any active

mode, the sleep timer is stopped and INH stays high (up to

Wave shaping is incorporated into the transmitter to

minimize EMI radiated emissions. An important

contributor to emissions is the rise and fall times during

output transitions at the “corners” of the voltage waveform.

The resultant waveform is one half of a sin wave of

frequency 50−65 kHz at the rising waveform edge and one

quarter of this sin wave at falling or trailing edge.

V ). If the transceiver enters the sleep mode, INH goes

BAT

to logic 0 (floating) after 250 ms (typ) when no wake−up

signal is present.

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12

NCV7356

HVWU Mode

MODE0

low

MODE1

high

MODE0/1 => High

High−Speed Mode

V on

BAT

MODE0

high

MODE1

low

MODE0&1 => Low

Normal Mode

MODE0

high

MODE1

high

MODE0/1 => High

(If V

on)

CC_ECU

V_BATstandby

MODE0/1

low

RxD

CAN

float

after 250 ms

−> no mode change

−> no valid wake−up

(1)

high/low

wake−up

request

from Bus

Sleep Mode

MODE0/1

low

CAN

float

(1)

low after HVWU, high after V

on & V

present

BAT

CCECU

Figure 6. State Diagram, 8 Pin Package

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13

NCV7356

HVWU Mode

MODE0 MODE1

low high

INH

V

BAT

MODE0/1 => High

High−Speed Mode

V on

BAT

MODE0 MODE1

INH

high

low

V

BAT

MODE0&1 => Low

Normal Mode

MODE0 MODE1

high high

INH

V

BAT

MODE0/1 => High

(If V

on)

CC_ECU

V_BATstandby

MODE0/1 INH

low

RxD

CAN

float

after 250 ms

−> no mode change

−> no valid wake−up

(1)

V

high/low

BAT

wake−up

request

from Bus

Sleep Mode

MODE0/1

low

INH/CAN

floating

(1)

low after HVWU, high after V

on & V

present

BAT

CCECU

Figure 7. State Diagram, 14 Pin Package

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14

NCV7356

MRA4004T3

*

V

BAT

V

+

BAT_ECU

Voltage Regulator

V

BAT

+5 V

100 nF

ECU Connector to

Single Wire CAN Bus

100 pF

+

2.7 kW

V

BAT

1 k

5

47 mH

4

RxD

7

6

CANH

LOAD

NCV7356

100 pF

6.49 kW

2

3

1

MODE0

MODE1

TxD

ESD Protection −

NUP1105L

8

GND

*Recommended capacitance at V

> 1.0 mF (immunity to ISO7637/1 test pulses)

BAT_ECU

Figure 8. Application Circuitry, 8 Pin Package

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15

NCV7356

MRA4004T3

*

V

BAT

V

+

BAT_ECU

Voltage Regulator

INH

V

BAT

+5 V

100 nF

ECU Connector to

Single Wire CAN Bus

100 pF

+

2.7 kW

V

BAT

1 k

9

10

47 mH

5

RxD

12

11

CANH

LOAD

NCV7356

100 pF

6.49 kW

3

4

2

MODE0

MODE1

TxD

ESD Protection −

NUP1105L

1, 7, 8, 14

GND

*Recommended capacitance at V

> 1.0 mF (immunity to ISO7637/1 test pulses)

BAT_ECU

Figure 9. Application Circuitry, 14 Pin Package

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16

NCV7356

SOIC−8 Thermal Information

Test Condition, Typical Value

Min Pad Board

1, Pad Board

(Note 20)

(Note 21)

Parameter

Junction−to−Lead (psi−JL7, Y ) or Pins 6−7

Unit

°C/W

57

51

JL8

Junction−to−Ambient (R , q

)

187

128

q

JA JA

2

20.1 oz copper, 53 mm coper area, 0.062″ thick FR4.

2

21.1 oz copper, 716 mm coper area, 0.062″ thick FR4.

Package Construction

with and without Mold Compound

Various copper areas used

for heat spreading

Active Area (red)

Lead #1

Figure 10. Internal construction of the

package simulation.

Figure 11. Min pad is shown as the red traces.

1, pad includes the yellow area. Internal

construction is shown for later reference.

190

180

170

160

150

140

130

120

110

100

1.0 oz. Cu

2.0 oz. Cu

0

100

200

300

400

500

600

700

800

2

Copper Area (mm )

Figure 12. SOIC−8, q_JAas a Function of the Pad Copper

Area Including Traces,

Board Material

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17

NCV7356

Table 1. SOIC−8 Thermal RC Network Models*

2

53 mm

719 mm

Copper Area

53 mm2

719 mm

Copper Area

Cauer Network

Foster Network

C’s

Units

W−s/C

Tau

Units

sec

5.86E−06

2.29E−05

6.98E−05

3.68E−04

3.75E−04

1.57E−03

2.05E−02

9.13E−02

2.64E−01

1.66E+01

R’s

5.86E−06

2.29E−05

6.97E−05

3.68E−04

3.74E−04

1.56E−03

2.24E−02

7.35E−02

1.22E+00

9.74E+00

R’s

1.00E−06

1.00E−05

1.00E−04

1.99E−04

1.00E−03

1.64E−02

5.60E−01

4.50E+00

7.61E+01

3.00E+01

R’s

1.00E−06

1.00E−05

1.00E−04

1.99E−04

1.00E−03

1.64E−02

5.60E−01

4.50E+00

7.61E+01

3.00E+01

R’s

0.22

C/W

1.30E−01

2.82E−01

8.91E−01

0.17

1.30E−01

2.82E−01

8.91E−01

0.18

C/W

0.50

1.30

1.80

1.79

0.95

0.96

1.88

7.43

7.37

7.15

7.24

31.19

31.59

19.80

16.27

59.97

47.70

30.1

54.7

75.79

28.63

14.1

23.3

4.41

6.15

109.0

21.3

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

are computed by the square root of time constant R(t) = 130 * sqrt(time(sec)). The constant is derived based on the active area of the device

with silicon and epoxy at the interface of the heat generation.

The Cauer networks generally have physical

significance and may be divided between nodes to separate

thermal behavior due to one portion of the network from

another. The Foster networks, though when sorted by time

constant (as above) bear a rough correlation with the Cauer

networks, are really only convenient mathematical models.

Both Foster and Cauer networks can be easily implemented

using circuit simulating tools, whereas Foster networks

may be more easily implemented using mathematical tools

(for instance, in a spreadsheet program), according to the

following formula:

n

−tńtau

i

ǒ

R 1−e

i

Ǔ

R(t) +

S

i + 1

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18

NCV7356

R

1

R

2

R

3

R

n

Junction

C

1

C

2

C

n

C

3

Ambient

Time constants are not simple RC products.

(thermal ground)

Amplitudes of mathematical solution are not the resistance values.

Figure 13. Grounded Capacitor Thermal Network (“Cauer” Ladder)

R

Junction

1

2

3

n

C

n

C

Each rung is exactly characterized by its RC−product time constant; Am-

plitudes are the resistances

Ambient

(thermal ground)

Figure 14. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)

1000

100

10

2

Cu Area = 53 mm 1.0 oz.

2

Cu Area = 93 mm 1.0 oz.

2

Cu Area = 719 mm 1.0 oz.

1

0.1

0.000001

0.00001

0.0001

0.001

0.01

Time (s)

0.1

1

10

100

1000

Figure 15. SOIC−8 Single Pulse Heating Curve

1000

D = 0.50

100

10

0.20

0.10

0.05

0.02

1

0.01

Single Pulse

0.00001 0.0001

0.1

0.000001

0.001

0.01

Time (s)

0.1

1

10

100

1000

Figure 16. SOIC−8 Thermal Duty Cycle Curves on 1, Spreader Test Board

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19

NCV7356

SOIC−14 Thermal Information

Test Condition, Typical Value

Min Pad Board

1, Pad Board

(Note 22)

(Note 23)

Parameter

Unit

°C/W

Junction−to−Lead (psi−JL8, Y

)

JL8

30

84

Junction−to−Ambient (R , q

)

122

q

JA JA

2

22.1 oz copper, 94 mm coper area, 0.062″ thick FR4.

2

23.1 oz copper, 767 mm coper area, 0.062″ thick FR4.

Figure 18. Min pad is shown as the red traces.

1 inch pad includes the yellow area. Pin 1, 7, 8

and 14 are connected to flag internally to the

package and externally to the heat spreading area.

Figure 17. Internal construction of the package

simulation.

150

140

130

120

1.0 oz. Cu

110

Sim 1.0 oz.

Sim 2.0 oz.

100

2.0 oz. Cu

90

80

70

60

0

100

200

300

400

500

600

700

800

900

2

Copper Area (mm )

Figure 19. SOIC−14, q_JAas a Function of the Pad Copper Area Including Traces,

Board Material

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20

NCV7356

Table 2. SOIC−14 Thermal RC Network Models*

2

96 mm

767 mm

Copper Area

96 mm

767 mm

Copper Area

Cauer Network

Foster Network

C’s

Units

W−s/C

Tau

Units

sec

3.12E−05

1.21E−04

3.53E−04

1.19E−03

4.86E−03

2.17E−02

8.94E−02

0.304

3.12E−05

1.21E−04

3.50E−04

1.19E−03

5.05E−03

7.16E−03

3.51E−02

0.262

1.00E−06

1.00E−05

1.00E−04

0.028

1.00E−06

1.00E−05

1.00E−04

0.001

0.009

0.047

0.875

7.53

0.001

0.280

2.016

16.64

1.71

2.43

59.47

68.4

411

92.221

R’s

2.44E−02

5.28E−02

1.67E−01

3.5

0.041

0.095

0.279

1.154

5.621

13.180

23.823

53.332

24.794

0.041

°C/W

2.44E−02

5.28E−02

1.67E−01

0.7

°C/W

0.096

0.281

0.995

6.351

0.7

0.1

1.910

8.7

5.8

21.397

27.150

25.276

0.218

15.9

16.4

31.9

27.1

61.3

29.0

4.3

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device

with silicon and epoxy at the interface of the heat generation.

The Cauer networks generally have physical

significance and may be divided between nodes to separate

thermal behavior due to one portion of the network from

another. The Foster networks, though when sorted by time

constant (as above) bear a rough correlation with the Cauer

networks, are really only convenient mathematical models.

Both Foster and Cauer networks can be easily implemented

using circuit simulating tools, whereas Foster networks

may be more easily implemented using mathematical tools

(for instance, in a spreadsheet program), according to the

following formula:

n

−tńtau

i

ǒ

R 1−e

i

Ǔ

R(t) +

S

i + 1

R

1

R

2

R

3

R

n

Junction

C

1

C

2

C

n

C

3

Ambient

Time constants are not simple RC products.

Amplitudes of mathematical solution are not the resistance values.

(thermal ground)

Figure 20. Grounded Capacitor Thermal Network (“Cauer” Ladder)

R

C

R

Junction

1

2

3

n

C

2

C

n

C

3

1

Each rung is exactly characterized by its RC−product time constant; Am-

plitudes are the resistances

Ambient

(thermal ground)

Figure 21. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)

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21

NCV7356

1000

100

10

2

Cu Area = 96 mm 1.0 oz.

2

Cu Area = 767 mm 1.0 oz.

2

Cu Area = 767 mm 1.0 oz. 1S2P

1

0.1

0.01

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

Time (s)

Figure 22. SOIC−14 Single Pulse Heating

1000

D = 0.50

0.20

0.10

0.05

100

10

0.01

2

Cu Area = 717 mm 1.0 oz.

1

0.1

0.01

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

PULSE DURATION (sec)

Figure 23. SOIC−14 Thermal Duty Cycle Curves on 1, Spreader Test Board

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22

NCV7356

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−A−

14

8

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−B−

P 7 PL

M

B

0.25 (0.010)

7

1

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

F

R X 45

_

C

A

B

C

D

F

8.55

3.80

1.35

0.35

0.40

8.75 0.337 0.344

4.00 0.150 0.157

1.75 0.054 0.068

0.49 0.014 0.019

1.25 0.016 0.049

−T−

SEATING

PLANE

J

M

K

G

J

K

M

P

R

1.27 BSC

0.050 BSC

0.25 0.008 0.009

0.25 0.004 0.009

_

D 14 PL

0.19

0.10

0

M

S

A

0.25 (0.010)

T B

7

0

7

_

5.80

0.25

6.20 0.228 0.244

0.50 0.010 0.019

SOLDERING FOOTPRINT*

7X

7.04

14X

1.52

1

14X

0.58

1.27

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

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23

NCV7356

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

−Z−

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCV7356/D

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24

型号:	NCV7356D2R2G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
生命周期：	Active
IHS 制造商：	ON SEMICONDUCTOR
零件包装代码：	SOIC
包装说明：	SOP, SOP14,.25
针数：	14
制造商包装代码：	751A-03
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	1.12
Is Samacsys：	N
数据速率：	100 Mbps
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e3
长度：	8.65 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	14
收发器数量：	1
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5/27 V
认证状态：	Not Qualified
筛选级别：	AEC-Q100
座面最大高度：	1.75 mm
子类别：	Network Interfaces
标称供电电压：	16 V
表面贴装：	YES
电信集成电路类型：	INTERFACE CIRCUIT
温度等级：	AUTOMOTIVE
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm
Base Number Matches：	1

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