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产品型号NM27C256Q-150的概述

芯片NM27C256Q-150的概述 NM27C256Q-150是一款由NEC公司(现为Renesas Electronics的一部分)生产的EPROM(可擦除可编程只读存储器)。该芯片属于28位地址的256K位(32K字节)EPROM,通常用于需要非挥发性存储的应用场景。这种存储器的最大特点在于其可编程和可擦除的特性,能够在应用中提供持久的存储解决方案。 该芯片特别适合用于各种嵌入式系统、微控制器、仿真软件以及各种工业应用。EPROMS的使用使开发者能够在原型阶段进行代码修改,同时确保数据在断电后能够持久保留。 芯片NM27C256Q-150的详细参数 NM27C256Q-150的主要参数包括: 1. 存储容量: 256 Kbit(32 KB) 2. 地址位宽: 28 位 3. 数据位宽: 8 位 4. 编程时间: 约20毫秒 5. 擦除时间: 约0.1秒 6. 电源电压: 5V(典...

产品型号NM27C256Q100的Datasheet PDF文件预览

July 1998  
NM27C256  
262,144-Bit (32K x 8) High Performance CMOS EPROM  
The NM27C256 is one member of a high density EPROM Family  
which range in densities up to 4 Mb.  
General Description  
The NM27C256 is a 256K Electrically Programmable Read Only  
Memory. It is manufactured in Fairchild’s latest CMOS split gate  
EPROM technology which enables it to operate at speeds as fast  
as 90 ns access time over the full operating range.  
Features  
High performance CMOS  
90 ns access time  
The NM27C256 provides microprocessor-based systems exten-  
JEDEC standard pin configuration  
sive storage capacity for large portions of operating system and  
— 28-pin PDIP package  
application software. Its 90 ns access time provides high speed  
— 32-pin chip carrier  
operation with high-performance CPUs. The NM27C256 offers a  
— 28-pin CERDIP package  
single chip solution for the code storage requirements of 100%  
Drop-in replacement for 27C256 or 27256  
firmware-based equipment. Frequently-used software routines  
are quickly executed from EPROM storage, greatly enhancing  
system utility.  
Manufacturer’s identification code  
The NM27C256 is configured in the standard EPROM pinout  
which provides an easy upgrade path for systems which are  
currently using standard EPROMs.  
Block Diagram  
Data Outputs O - O  
0
7
V
CC  
GND  
V
PP  
OE  
Output Enable  
and Chip Enable Logic  
Output  
Buffers  
CE/PGM  
Y Decoder  
Y Gating  
A
- A  
14  
0
Address  
Inputs  
X Decoder  
DS010833-1  
1
© 1998 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
Connection Diagrams  
27C080 27C040 27C020 27C010 27C512  
27C512 27C010 27C020 27C040  
27C080  
DlP  
NM27C256  
A
A
A
A
XX/V XX/V  
PP  
XX/V  
A
V
V
V
V
19  
16  
15  
12  
PP  
PP  
CC  
CC  
CC  
CC  
A
A
A
A
A
A
XX/PGM XX/PGM  
A
A
A
A
A
16  
15  
12  
16  
16  
18  
17  
14  
13  
18  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
A
A
A
A
V
1
V
A
A
A
A
A
XX  
A
A
A
A
15  
12  
15  
12  
15  
12  
PP  
CC  
14  
13  
8
17  
14  
13  
17  
A
2
A
A
A
A
12  
14  
13  
14  
13  
14  
A
A
A
A
A
A
A
A
A
A
A
A
A
O
O
O
3
A
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
2
13  
A
A
A
A
A
4
A
A
A
A
A
8
A
9
8
9
8
9
8
9
8
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
5
A
A
A
A
9
6
A
11  
A
A
A
A
11  
11  
11  
11  
11  
7
OE  
A
OE/V  
A
OE  
OE  
OE  
OE/V  
PP  
PP  
8
A
A
A
A
10  
10  
10  
10  
10  
10  
9
CE/PGM  
CE/PGM  
CE  
CE  
CE/PGM CE/PGM  
10  
11  
12  
13  
14  
O
7
O
6
O
5
O
4
O
7
O
6
O
5
O
4
O
7
O
6
O
5
O
4
O
7
O
6
O
5
O
4
O
O
O
O
O
O
O
O
O
O
7
6
5
4
3
7
6
5
4
3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
GND GND  
GND  
GND GND  
GND  
O
3
O
3
O
3
O
3
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins.  
DS010833-2  
Commercial Temp. Range (0°C to +70°C)  
VCC = 5V ±10%  
Pin Names  
Description  
Symbol  
A0–A14  
CE/PGM  
OE  
Parameter/Order Number Access Time (ns)  
Addresses  
NM27C256 Q, N, V 90  
NM27C256 Q, N, V 100  
NM27C256 Q, N, V 120  
NM27C256 Q, N, V 150  
NM27C256 Q, N, V 200  
90  
Chip Enable/Program  
Output Enable  
Outputs  
100  
120  
150  
200  
O0–O7  
XX  
Don’t Care (during Read)  
PLCC  
Extended Temp. Range (-40°C to +85°C)  
VCC = 5V ±10%  
Parameter/Order Number Access Time (ns)  
4
3
2
1 32 31 30  
NM27C256 QE, NE, VE 120  
NM27C256 QE, NE, VE 150  
NM27C256 QE, NE, VE 200  
120  
150  
200  
5
6
7
8
29  
28  
27  
26  
25  
24  
23  
22  
21  
A8  
A9  
A11  
XX  
OE  
A10  
CE/PGM  
O7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
XX  
O0  
Note: Surface mount PLCC package available for commercial and extended  
temperature ranges only.  
9
Package Types: NM27C256 Q, N, V XXX  
Q = Quartz-Windowed Ceramic DIP  
N = Plastic OTP DIP  
10  
11  
12  
13  
V = Surface-Mount PLCC  
O6  
All Packages conform to the JEDEC standard.  
14 15 16 17 18 19 20  
All versions are guaranteed to function for slower speeds.  
DS010833-3  
Top  
2
www.fairchildsemi.com  
ESD Protection  
> 2000V  
Absolute Maximum Ratings (Note 1)  
All Output Voltages with  
Respect to Ground  
Storage Temperature  
-65°C to +150°C  
VCC + 1.0V to GND -0.6V  
All Input Voltages except A9 with  
Respect to Ground  
-0.6V to +7V  
-0.7V to +14V  
-0.6V to +7V  
Operating Range  
VPP and A9 with Respect  
to Ground  
Range  
Comm’l  
Temperature  
VCC  
0°C to +70°C  
-40°C to +85°C  
+5V ±10%  
+5V ±10%  
VCC Supply Voltage with  
Respect to Ground  
Industrial  
Read Operation  
DC Electrical Characteristics Over Operating Range with VPP = VCC  
Symbol  
VIL  
Parameter  
Test Conditions  
Min  
-0.5  
2.0  
Max  
0.8  
Units  
Input Low Level  
V
V
VIH  
Input High Level  
VCC +1  
0.4  
VOL  
Output Low Voltage  
Output High Voltage  
IOL = 2.1 mA  
V
VOH  
IOH = -2.5 mA  
3.5  
V
ISB1  
(Note 11)  
VCC Standby Current  
(CMOS)  
CE = VCC ±0.3V  
100  
µA  
ISB2  
ICC1  
VCC Standby Current (TTL)  
CE = VIH  
1
mA  
mA  
VCC Active Current  
TTL Inputs  
CE = OE = VIL,f=5 MHz  
Inputs = VIH or VIL, I/O = 0 mA  
35  
IPP  
VPP  
ILI  
VPP Supply Current  
VPP Read Voltage  
VPP = VCC  
10  
VCC  
1
µA  
V
VCC - 0.7  
-1  
Input Load Current  
Output Leakage Current  
VIN = 5.5V or GND  
VOUT = 5.5V or GND  
µA  
µA  
ILO  
-10  
10  
AC Electrical Characteristics Over Operating Range with VPP = VCC  
Symbol  
Parameter  
90  
100  
120  
150  
200  
Units  
Min Max Min Max Min Max Min Max Min Max  
tACC  
tCE  
Address to Output Delay  
CE to Output Delay  
OE to Output Delay  
90  
90  
35  
30  
100  
100  
50  
120  
120  
50  
150  
150  
50  
200  
200  
50  
ns  
tOE  
tDF  
(Note 2)  
Output Disable to  
Output Float  
30  
35  
45  
45  
tOH  
(Note 2)  
Output Hold from  
Addresses,  
0
0
0
0
0
CE or OE, Whichever  
Occurred First  
Capacitance (Note 2) TA = +25˚C, f = 1 MHz  
Symbol  
CIN  
Parameter  
Conditions Typ Max Units  
Input Capacitance  
VIN = 0V  
6
9
12  
12  
pF  
pF  
COUT  
Output Capacitance VOUT = 0V  
3
www.fairchildsemi.com  
AC Test Conditions  
Output Load  
1 TTL Gate and CL = 100 pF (Note 8)  
Input Rise and Fall Times  
Input Pulse Levels  
5 ns  
0.45 to 2.4V  
Timing Measurement Reference Level (Note 10)  
Inputs  
Outputs  
0.8V and 2.0V  
0.8V and 2.0V  
AC Waveforms (Note 6) (Note 7) (Note 9)  
2.0V  
ADDRESSES  
ADDRESSES VALID  
0.8V  
2.0V  
CE  
0.8V  
tCE  
tCE  
(Notes 4, 5)  
2.0V  
OE  
0.8V  
tOE  
(Note 3)  
tDF  
(Notes 4, 5)  
2.0V  
Hi-Z  
Hi-Z  
OUTPUT  
0.8V  
VALID OUTPUT  
tACC  
(Note 3)  
tOH  
DS010833-4  
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability.  
Note 2: This parameter is only sampled and is not 100% tested.  
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC  
.
Note 4: The tDF and tCF compare level is determined as follows:  
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;  
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.  
Note 5: TRI-STATE may be attained using OE or CE.  
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device  
between VCC and GND.  
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.  
Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 µA.  
CL = 100 pF includes fixture capacitance.  
Note 9: VPP may be connected to VCC except during programming.  
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.  
Note 11: CMOS inputs: VIL = GND ±0.3V, VIH = VCC ±0.3V.  
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
4
www.fairchildsemi.com  
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15) (Continued)  
Symbol  
tAS  
Parameter  
Address Setup Time  
OE Setup Time  
Conditions  
Min  
Typ  
Max  
Units  
µs  
1
1
1
1
1
0
1
0
tOES  
tVPS  
tVCS  
tDS  
µs  
VPP Setup Time  
µs  
VCC Setup Time  
Data Setup Time  
Address Hold Time  
Data Hold Time  
µs  
µs  
tAH  
µs  
tDH  
µs  
tDF  
Output Enable to Output  
Float Delay  
CE = VIL  
60  
ns  
tPW  
tOE  
IPP  
Program Pulse Width  
Data Valid from OE  
45  
50  
105  
100  
30  
µs  
ns  
CE = VIL  
CE = VIL  
VPP Supply Current  
mA  
during Programming Pulse  
ICC  
TA  
VCC Supply Current  
50  
30  
mA  
°C  
V
Temperature Ambient  
Power Supply Voltage  
Programming Supply Voltage  
Input Rise, Fall Time  
20  
6.25  
12.5  
5
25  
6.5  
VCC  
VPP  
tFR  
6.75  
13.0  
12.75  
V
ns  
V
VIL  
Input Low Voltage  
0.0  
4.0  
0.45  
VIH  
tIN  
Input High Voltage  
2.4  
0.8  
0.8  
V
Input Timing Reference Voltage  
Output Timing Reference Voltage  
2.0  
2.0  
V
tOUT  
V
Programming Waveforms (Note 14)  
PROGRAM  
VERIFY  
PROGRAM  
2.0V  
ADDRESSES  
ADDRESS N  
0.8V  
tAS  
tAH  
2.0V  
DATA IN STABLE  
ADD N  
DATA OUT VALID  
ADD N  
DATA  
VCC  
0.8V  
tDS  
tDH  
tDF  
5.25V  
tVCS  
12.75V  
VPP  
tVPS  
2.0V  
0.8V  
CE  
OE  
tOES  
tOE  
tPW  
2.0V  
0.8V  
DS010833-5  
Note 12: Fairchild’s standard product warranty applies to devices programmed to specifications described herein.  
Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with  
voltage applied to VPP or VCC  
.
Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to  
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients  
which may damage the device.  
Note 15: During power up the PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP  
.
5
www.fairchildsemi.com  
Turbo Programming Algorithm Flow Chart  
VCC = 6.5V VPP = 12.75V  
n = 0  
ADDRESS = FIRST LOCATION  
PROGRAM ONE 50µs PULSE  
INCREMENT n  
NO  
YES  
FAIL  
DEVICE  
FAILED  
VERIFY  
BYTE  
n = 10?  
PASS  
INCREMENT  
ADDRESS  
n = 0  
LAST  
ADDRESS  
?
NO  
YES  
ADDRESS = FIRST LOCATION  
FAIL  
VERIFY  
BYTE  
PASS  
PROGRAM ONE  
50 µs  
INCREMENT  
ADDRESS  
PULSE  
LAST  
NO  
ADDRESS  
?
YES  
CHECK ALL BYTES  
1ST: VCC = VPP = 6.0V  
2ND: VCC = VPP = 4.3V  
Note:  
The standard National Semiconductor algorithm may also be used but it will have longer programming time.  
DS010833-6  
FIGURE 1.  
6
www.fairchildsemi.com  
The EPROM is in the programming mode when the VPP power  
supply is at 12.75V and OE is at VIH. It is required that at least a  
0.1 µF capacitor be placed across VPP, VCC to ground to suppress  
spurious voltage transients which may damage the device. The  
data to be programmed is applied 8 bits in parallel to the data  
output pins. The levels required for the address and data inputs  
are TTL.  
Functional Description  
DEVICE OPERATION  
The six modes of operation of the EPROM are listed in Table 1. It  
should be noted that all inputs for the six modes are at TTL levels.  
The power supplies required are VCC and VPP. The VPP power  
supply must be at 12.75V during the three programming modes,  
andmustbeat5Vintheotherthreemodes. TheVCC powersupply  
must be at 6.5V during the three programming modes, and at 5V  
in the other three modes.  
Whentheaddressanddataarestable,anactivelow,TTLprogram  
pulse is applied to the CE/PGM input. A program pulse must be  
applied at each address location to be programmed. The EPROM  
is programmed with the Turbo Programming Algorithm shown in  
Figure 1. Each Address is programmed with a series of 50 µs  
pulses until it verifies good, up to a maximum of 10 pulses. Most  
memorycellswillprogram withasingle50µspulse.(Thestandard  
National Semiconductor Algorithm may also be used but it will  
have longer programming time.)  
Read Mode  
The EPROM has two control functions, both of which must be  
logically active in order to obtain data at the outputs. Chip Enable  
(CE/PGM) is the power control and should be used for device  
selection. Output Enable (OE) is the output control and should be  
used to gate data to the output pins, independent of device  
selection. Assuming that addresses are stable, address access  
time (tACC) is equal to the delay from CE to output (tCE). Data is  
available at the outputs tOE after the falling edge of OE, assuming  
that CE/PGM has been low and addresses have been stable for  
The EPROM must not be programmed with a DC signal applied to  
the CE/PGM input.  
Programming multiple EPROM in parallel with the same data can  
be easily accomplished due to the simplicity of the programming  
requirments.LikeinputsoftheparallelEPROMmaybeconnected  
together when they are programmed with the same data. A low  
level TTL pulse applied to the CE/PGM input programs the  
paralleled EPROM.  
at least tACC –tOE  
.
Standby Mode  
The EPROM has a standby mode which reduces the active power  
dissipation by over 99%, from 385 mW to 0.55 mW. The EPROM  
is placed in the standby mode by applying a CMOS high signal to  
the CE/PGM input. When in standby mode, the outputs are in a  
high impedance state, independent of the OE input.  
Program Inhibit  
Programming multiple EPROMs in parallel with different data is  
also easily accomplished. Except for CE/PGM, all like inputs  
(including OE) of the parallel EPROMs may be common. A TTL  
low level program pulse applied to an EPROM’s CE/PGM input  
withVPP at12.75VwillprogramthatEPROM. ATTLhighlevelCE/  
PGM input inhibits the other EPROMs from being programmed.  
Output Disable  
The EPROM is placed in output disable by applying a TTL high  
signal to the OE input. When in output disable all circuitry is  
enabled, except the outputs are in a high impedance state (TRI-  
STATE).  
Program Verify  
Averifyshouldbeperformedontheprogrammedbitstodetermine  
whether they were correctly programmed. The verify may be  
performed with VPP at 12.75V. VPP must be at VCC, except during  
programming and program verify.  
Output OR-Typing  
Because the EPROM is usually used in larger memory arrays,  
Fairchild has provided a 2-line control function that accommo-  
dates this use of multiple memory connections. The 2-line control  
function allows for:  
AFTER PROGRAMMING  
Opaque labels should be placed over the EPROM window to  
prevent unintentional erasure. Covering the window will also  
preventtemporaryfunctionalfailureduetothegenerationof photo  
currents.  
1. the lowest possible memory power dissipation, and  
2. complete assurance that output bus contention will not  
occur.  
To most efficiently use these two control lines, it is recommended  
that CE/PGM be decoded and used as the primary device select-  
ing function, while OE be made a common connection to all  
devices in the array and connected to the READ line from the  
system control bus. This assures that all deselected memory  
devices are in their low power standby modes and that the output  
pinsareactiveonlywhendataisdesiredfromaparticularmemory  
device.  
MANUFACTURER’S IDENTIFICATION CODE  
The EPROM has a manufacturer’s identification code to aid in  
programming. When the device is inserted in an EPROM pro-  
grammer socket, the programmer reads the code and then  
automatically calls up the specific programming algorithm for the  
part. This automatic programming control is only possible with  
programmers which have the capability of reading the code.  
The Manufacturer’s Identification code, shown in Table 2, specifi-  
cally identifies the manufacturer and device type. The code for  
NM27C256 is “8F04”, where “8F” designates that it is made by  
Fairchild Semiconductor, and “04” designates a 256K part.  
Programming  
CAUTION:Exceeding14Vonpin1(VPP)willdamagetheEPROM.  
Initially, and after each erasure, all bits of the EPROM are in the  
“1’s” state. Data is introduced by selectively programming “0’s”  
into the desired bit locations. Although only “0’s” will be pro-  
grammed, both “1’s” and “0’s” can be presented in the data word.  
The only way to change a “0” to a “1” is by ultraviolet light erasure.  
The code is accessed by applying 12V ±0.5V to address pin A9.  
Addresses A1–A8, A10–A16, and all control pins are held at VIL.  
Address pin A0 is held at VIL for the manufacturer’s code, and held  
at VIH for the device code. The code is read on the eight data pins,  
O0 –O7. Proper code access is only guaranteed at 25°C to ±5°C.  
7
www.fairchildsemi.com  
be checked to make certain full erasure is occurring. Incomplete  
erasure will cause symptoms that can be misleading. Program-  
mers, components, and even system designs have been errone-  
ously suspected when incomplete erasure was the problem.  
Functional Description (Continued)  
ERASURE CHARACTERISTICS  
The erasure characteristics of the device are such that erasure  
begins to occur when exposed to light with wavelengths shorter  
than approximately 4000 Angstroms (Å). It should be noted that  
sunlight and certain types of fluorescent lamps have wavelengths  
in the 3000Å–4000Å range.  
SYSTEM CONSIDERATION  
The power switching characteristics of EPROMs require careful  
decoupling of the devices. The supply current, ICC, has three  
segments that are of interest to the system designer: the standby  
current level, the active current level, and the transient current  
peaks that are produced by voltage transitions on input pins. The  
magnitude of these transient current peaks is dependent of the  
output capacitance loading of the device. The associated VCC  
transient voltage peaks can be suppressed by properly selected  
decoupling capacitors. It is recommended that at least a 0.1 µF  
ceramic capacitor be used on every device between VCC and  
GND. This should be a high frequency capacitor of low inherent  
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor  
shouldbeusedbetweenVCC andGNDforeacheightdevices.The  
bulk capacitor should be located near where the power supply is  
connected to the array. The purpose of the bulk capacitor is to  
overcome the voltage drop caused by the inductive effects of the  
PC board traces.  
The recommended erasure procedure for the EPROM is expo-  
sure to short wave ultraviolet light which has a wavelength of  
2537Å. Theintegrateddose(i.e., UVintensityxexposuretime)for  
erasure should be a minimum of 15W-sec/cm2.  
The EPROM should be placed within 1 inch of the lamp tubes  
during erasure. Some lamps have a filter on their tubes which  
should be removed before erasure  
Anerasuresystemshouldbecalibratedperiodically. Thedistance  
fromlamptodeviceshouldbemaintainedatoneinch.Theerasure  
time increases as the square of the distance from the lamp (if  
distance is doubled the erasure time increases by factor of 4).  
Lamps lose intensity as they age. When a lamp is changed, the  
distance has changed, or the lamp has aged, the system should  
Mode Selection  
The modes of operation of NM27C256 listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels  
except for VPP and A9 for device signature.  
TABLE 1. Modes Selection  
Pins  
CE/PGM  
OE  
VPP  
VCC  
Outputs  
Mode  
Read  
VIL  
VIL  
VIH  
VCC  
VCC  
5.0V  
5.0V  
DOUT  
Output Disable  
X
High-Z  
(Note 16)  
Standby  
VIH  
VIL  
VIH  
VIH  
X
VCC  
5.0V  
6.25V  
6.25V  
6.25V  
High-Z  
DIN  
Programming  
Program Verify  
Program Inhibit  
VIH  
VIL  
VIH  
12.75V  
12.75V  
12.75V  
DOUT  
High-Z  
Note 16: X can be VIL or VIH  
.
TABLE 2. Manufacturer’s Identification Code  
Pins  
A0  
(10)  
VIL  
A9  
(24)  
12V  
12V  
O7  
(19)  
1
O6  
(18)  
0
O5  
(17)  
0
O4  
(16)  
0
O3  
(15)  
1
O2  
O1  
(12)  
1
O0  
Hex  
Data  
8F  
(13)  
(11)  
Manufacturer Code  
Device Code  
1
1
1
0
VIH  
0
0
0
0
0
0
04  
8
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Physical Dimensions inches (millimeters) unless otherwise noted  
1.450  
[36.83]  
MAX  
28  
15  
R 0.025  
[0.64]  
0.520 ± 0.006  
[13.21 ±0.15]  
0.600  
[15.24]  
MAX  
Glass  
1
14  
0.280 ±0.010  
[7.11 ±0.25]  
UV WINDOW  
R 0.030-0.055  
[0.76 - 1.40]  
TYP  
0.050-0.060  
TYP  
0.590-0.620  
[14.99 - 15.75]  
Glass  
Sealant  
0.005 MIN  
TYP  
0.175  
MAX  
0.225 MAX TYP  
0.125 MIN  
TYP  
95° ±5°  
TYP  
0.015 -0.060  
TYP  
0.010 ±0.002  
[0.25 ±0.05]  
TYP  
86°-94°  
0.150 MIN  
TYP  
TYP  
0.090-0.110  
TYP  
0.015-0.021  
TYP  
0.060-0.100  
TYP  
+0.025  
0.685  
-0.060  
+0.64  
-1.52  
17.40  
UV Window Cavity Dual-In-Line CerDIP Package (Q)  
Order Number NM27C256QXXX  
Package Number J28AQ  
2827 26 25 24 23 22 21 20 19 18 17 16 15  
0.030  
(0.762)  
Max  
0.600 - 0.620  
0.062  
(1.575)  
RAD  
0.510 ±0.005  
(15.24 - 15.75)  
(12.95 ±0.127)  
95° ±5°  
0.008-0.015  
(0.229-0.381)  
Pin #1  
IDENT  
1
2
3
4
5
6
7
8 9 10 11 12 13 14  
0.580  
(14.73)  
1.393 - 1.420  
(35.38 - 36.07)  
+0.025  
0.625  
-0.015  
+0.635  
-0.381  
0.050  
(1.270)  
Typ  
(
15.88  
(
0.053 - 0.069  
0.125-0.165  
(3.175-4.191)  
(1.346 - 1.753)  
0.20  
(0.508)  
Min  
88° 94°  
Typ  
0.125-0.145  
(3.175-3.583)  
0.108 ±0.010  
(2.540 ±0.254)  
0.050 ±0.015  
(1.270 ±0.381)  
0.018 ±0.003  
(0.457 ±0.076)  
28-Lead Plastic One-Time-Programmable Dual-In-Line Package  
Order Number NM27C256NXXX  
Package Number N28B  
9
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.485-0.495  
[12.32-12.57]  
-H-  
Base  
Plane  
0.106-0.112  
[2.69-2.84]  
B
S
D-E  
S
0.007[0.18]  
0.449-0.453  
[11.40-11.51]  
0.023-0.029  
[0.58-0.74]  
0.015  
[0.38]  
Min Typ  
-A-  
0.045  
[1.143]  
B
S
D-E  
S
0.007[0.18]  
0.002[0.05]  
°
60  
B
S
0.000-0.010  
[0.00-0.25]  
Polished Optional  
0.490-0530  
[12.45-13.46]  
0.400  
[10.16]  
-D-  
(
)
1
30  
4
0.541-0.545  
[13.74-13-84]  
S
C
D-E, F-G  
S
0.015[0.38]  
5
29  
0.549-0.553  
[13.94-14.05]  
-G-  
-B-  
0.585-0.595  
[14.86-15.11]  
0.013-0.021  
[0.33-0.53]  
TYP  
-F-  
See detail A  
-J-  
C
D-E, F-G  
S
0.007[0.18]  
M
13  
21  
0.078-0.095  
[1.98-2.41]  
0.123-0.140  
[3.12-3.56]  
0.050  
14  
A
20  
-E-  
-C-  
0.004[0.10]  
0.002[0.05]  
0.007[0.18]  
S
0.005  
[0.13]  
Max  
0.0100  
[0.254]  
A
F-G  
S
S
0.020  
[0.51]  
A
F-G  
S
0.007[0.18]  
S
0.118-0.129  
[3.00-3.28]  
0.045  
[1.14]  
0.030-0.040  
[0.76-1.02]  
B
A
D-E, F-G  
0.025  
[0.64]  
0.010[0.25]  
L
S
R
Detail A  
Typical  
Rotated 90°  
Min  
B
0.042-0.048  
[1.07-1.22]  
45°X  
0.025  
[0.64]  
0.021-0.027  
[0.53-0.69]  
Min  
B
0.065-0.071  
[1.65-1.80]  
0.053-0.059  
[1.65-1.80]  
0.031-0.037  
[0.79-0.94]  
0.006-0.012  
[0.15-0.30]  
0.027-0.033  
[0.69-0.84]  
0.026-0.032  
[0.66-0.81]  
0.019-0.025  
[0.48-0.64]  
Typ  
S
Section B-B  
Typical  
H
D-E, F-G  
S
0.007[0.18]  
32-Lead Plastic Leaded Chip Carrier (PLCC)  
Order Number NM27C256VXXX  
Package Number VA32A  
10  
www.fairchildsemi.com  
Life Support Policy  
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written  
approval of the President of Fairchild Semiconductor Corporation. As used herein:  
1. Life support devices or systems are devices or systems which,  
(a)areintendedforsurgicalimplantintothebody,or(b)support  
or sustain life, and whose failure to perform, when properly  
used in accordance with instructions for use provided in the  
labeling, can be reasonably expected to result in a significant  
injury to the user.  
2. A critical component is any component of a life support device  
or system whose failure to perform can be reasonably ex-  
pected to cause the failure of the life support device or system,  
or to affect its safety or effectiveness.  
Fairchild Semiconductor  
Americas  
Fairchild Semiconductor  
Europe  
Fairchild Semiconductor  
Hong Kong  
Fairchild Semiconductor  
Japan Ltd.  
Customer Response Center  
Tel. 1-888-522-5372  
Fax:  
Tel:  
Tel:  
Tel:  
Tel:  
+44 (0) 1793-856858  
8/F, Room 808, Empire Centre  
68 Mody Road, Tsimshatsui East  
Kowloon. Hong Kong  
Tel; +852-2722-8338  
Fax: +852-2722-8383  
4F, Natsume Bldg.  
Deutsch  
English  
Français  
Italiano  
+49 (0) 8141-6102-0  
+44 (0) 1793-856856  
+33 (0) 1-6930-3696  
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Tokyo, 113-0034 Japan  
Tel: 81-3-3818-8840  
Fax: 81-3-3818-8841  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
11  
www.fairchildsemi.com  
配单直通车
NM27C256Q100产品参数
型号:NM27C256Q100
生命周期:Contact Manufacturer
IHS 制造商:ROCHESTER ELECTRONICS LLC
包装说明:DIP,
Reach Compliance Code:unknown
风险等级:5.82
最长访问时间:100 ns
JESD-30 代码:R-GDIP-T28
JESD-609代码:e0
内存密度:262144 bit
内存集成电路类型:UVPROM
内存宽度:8
功能数量:1
端子数量:28
字数:32768 words
字数代码:32000
工作模式:ASYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:32KX8
封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP
封装形状:RECTANGULAR
封装形式:IN-LINE
并行/串行:PARALLEL
座面最大高度:5.969 mm
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:NO
技术:CMOS
温度等级:COMMERCIAL
端子面层:TIN LEAD
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
宽度:15.24 mm
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